1 | /* |
2 | * ARM SSE-200 CPU_IDENTITY register block |
3 | * |
4 | * Copyright (c) 2019 Linaro Limited |
5 | * Written by Peter Maydell |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 or |
9 | * (at your option) any later version. |
10 | */ |
11 | |
12 | /* |
13 | * This is a model of the "CPU_IDENTITY" register block which is part of the |
14 | * Arm SSE-200 and documented in |
15 | * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf |
16 | * |
17 | * It consists of one read-only CPUID register (set by QOM property), plus the |
18 | * usual ID registers. |
19 | */ |
20 | |
21 | #include "qemu/osdep.h" |
22 | #include "qemu/log.h" |
23 | #include "qemu/module.h" |
24 | #include "trace.h" |
25 | #include "qapi/error.h" |
26 | #include "hw/sysbus.h" |
27 | #include "hw/registerfields.h" |
28 | #include "hw/misc/armsse-cpuid.h" |
29 | #include "hw/qdev-properties.h" |
30 | |
31 | REG32(CPUID, 0x0) |
32 | REG32(PID4, 0xfd0) |
33 | REG32(PID5, 0xfd4) |
34 | REG32(PID6, 0xfd8) |
35 | REG32(PID7, 0xfdc) |
36 | REG32(PID0, 0xfe0) |
37 | REG32(PID1, 0xfe4) |
38 | REG32(PID2, 0xfe8) |
39 | REG32(PID3, 0xfec) |
40 | REG32(CID0, 0xff0) |
41 | REG32(CID1, 0xff4) |
42 | REG32(CID2, 0xff8) |
43 | REG32(CID3, 0xffc) |
44 | |
45 | /* PID/CID values */ |
46 | static const int sysinfo_id[] = { |
47 | 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ |
48 | 0x58, 0xb8, 0x0b, 0x00, /* PID0..PID3 */ |
49 | 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ |
50 | }; |
51 | |
52 | static uint64_t armsse_cpuid_read(void *opaque, hwaddr offset, |
53 | unsigned size) |
54 | { |
55 | ARMSSECPUID *s = ARMSSE_CPUID(opaque); |
56 | uint64_t r; |
57 | |
58 | switch (offset) { |
59 | case A_CPUID: |
60 | r = s->cpuid; |
61 | break; |
62 | case A_PID4 ... A_CID3: |
63 | r = sysinfo_id[(offset - A_PID4) / 4]; |
64 | break; |
65 | default: |
66 | qemu_log_mask(LOG_GUEST_ERROR, |
67 | "SSE CPU_IDENTITY read: bad offset 0x%x\n" , (int)offset); |
68 | r = 0; |
69 | break; |
70 | } |
71 | trace_armsse_cpuid_read(offset, r, size); |
72 | return r; |
73 | } |
74 | |
75 | static void armsse_cpuid_write(void *opaque, hwaddr offset, |
76 | uint64_t value, unsigned size) |
77 | { |
78 | trace_armsse_cpuid_write(offset, value, size); |
79 | |
80 | qemu_log_mask(LOG_GUEST_ERROR, |
81 | "SSE CPU_IDENTITY: write to RO offset 0x%x\n" , (int)offset); |
82 | } |
83 | |
84 | static const MemoryRegionOps armsse_cpuid_ops = { |
85 | .read = armsse_cpuid_read, |
86 | .write = armsse_cpuid_write, |
87 | .endianness = DEVICE_LITTLE_ENDIAN, |
88 | /* byte/halfword accesses are just zero-padded on reads and writes */ |
89 | .impl.min_access_size = 4, |
90 | .impl.max_access_size = 4, |
91 | .valid.min_access_size = 1, |
92 | .valid.max_access_size = 4, |
93 | }; |
94 | |
95 | static Property armsse_cpuid_props[] = { |
96 | DEFINE_PROP_UINT32("CPUID" , ARMSSECPUID, cpuid, 0), |
97 | DEFINE_PROP_END_OF_LIST() |
98 | }; |
99 | |
100 | static void armsse_cpuid_init(Object *obj) |
101 | { |
102 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
103 | ARMSSECPUID *s = ARMSSE_CPUID(obj); |
104 | |
105 | memory_region_init_io(&s->iomem, obj, &armsse_cpuid_ops, |
106 | s, "armsse-cpuid" , 0x1000); |
107 | sysbus_init_mmio(sbd, &s->iomem); |
108 | } |
109 | |
110 | static void armsse_cpuid_class_init(ObjectClass *klass, void *data) |
111 | { |
112 | DeviceClass *dc = DEVICE_CLASS(klass); |
113 | |
114 | /* |
115 | * This device has no guest-modifiable state and so it |
116 | * does not need a reset function or VMState. |
117 | */ |
118 | |
119 | dc->props = armsse_cpuid_props; |
120 | } |
121 | |
122 | static const TypeInfo armsse_cpuid_info = { |
123 | .name = TYPE_ARMSSE_CPUID, |
124 | .parent = TYPE_SYS_BUS_DEVICE, |
125 | .instance_size = sizeof(ARMSSECPUID), |
126 | .instance_init = armsse_cpuid_init, |
127 | .class_init = armsse_cpuid_class_init, |
128 | }; |
129 | |
130 | static void armsse_cpuid_register_types(void) |
131 | { |
132 | type_register_static(&armsse_cpuid_info); |
133 | } |
134 | |
135 | type_init(armsse_cpuid_register_types); |
136 | |