1 | /* |
2 | * QEMU Sparc Sun4m ECC memory controller emulation |
3 | * |
4 | * Copyright (c) 2007 Robert Reif |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "hw/irq.h" |
27 | #include "hw/qdev-properties.h" |
28 | #include "hw/sysbus.h" |
29 | #include "migration/vmstate.h" |
30 | #include "qemu/module.h" |
31 | #include "trace.h" |
32 | |
33 | /* There are 3 versions of this chip used in SMP sun4m systems: |
34 | * MCC (version 0, implementation 0) SS-600MP |
35 | * EMC (version 0, implementation 1) SS-10 |
36 | * SMC (version 0, implementation 2) SS-10SX and SS-20 |
37 | * |
38 | * Chipset docs: |
39 | * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01, |
40 | * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf |
41 | */ |
42 | |
43 | #define ECC_MCC 0x00000000 |
44 | #define ECC_EMC 0x10000000 |
45 | #define ECC_SMC 0x20000000 |
46 | |
47 | /* Register indexes */ |
48 | #define ECC_MER 0 /* Memory Enable Register */ |
49 | #define ECC_MDR 1 /* Memory Delay Register */ |
50 | #define ECC_MFSR 2 /* Memory Fault Status Register */ |
51 | #define ECC_VCR 3 /* Video Configuration Register */ |
52 | #define ECC_MFAR0 4 /* Memory Fault Address Register 0 */ |
53 | #define ECC_MFAR1 5 /* Memory Fault Address Register 1 */ |
54 | #define ECC_DR 6 /* Diagnostic Register */ |
55 | #define ECC_ECR0 7 /* Event Count Register 0 */ |
56 | #define ECC_ECR1 8 /* Event Count Register 1 */ |
57 | |
58 | /* ECC fault control register */ |
59 | #define ECC_MER_EE 0x00000001 /* Enable ECC checking */ |
60 | #define ECC_MER_EI 0x00000002 /* Enable Interrupts on |
61 | correctable errors */ |
62 | #define ECC_MER_MRR0 0x00000004 /* SIMM 0 */ |
63 | #define ECC_MER_MRR1 0x00000008 /* SIMM 1 */ |
64 | #define ECC_MER_MRR2 0x00000010 /* SIMM 2 */ |
65 | #define ECC_MER_MRR3 0x00000020 /* SIMM 3 */ |
66 | #define ECC_MER_MRR4 0x00000040 /* SIMM 4 */ |
67 | #define ECC_MER_MRR5 0x00000080 /* SIMM 5 */ |
68 | #define ECC_MER_MRR6 0x00000100 /* SIMM 6 */ |
69 | #define ECC_MER_MRR7 0x00000200 /* SIMM 7 */ |
70 | #define ECC_MER_REU 0x00000100 /* Memory Refresh Enable (600MP) */ |
71 | #define ECC_MER_MRR 0x000003fc /* MRR mask */ |
72 | #define ECC_MER_A 0x00000400 /* Memory controller addr map select */ |
73 | #define ECC_MER_DCI 0x00000800 /* Disables Coherent Invalidate ACK */ |
74 | #define ECC_MER_VER 0x0f000000 /* Version */ |
75 | #define ECC_MER_IMPL 0xf0000000 /* Implementation */ |
76 | #define ECC_MER_MASK_0 0x00000103 /* Version 0 (MCC) mask */ |
77 | #define ECC_MER_MASK_1 0x00000bff /* Version 1 (EMC) mask */ |
78 | #define ECC_MER_MASK_2 0x00000bff /* Version 2 (SMC) mask */ |
79 | |
80 | /* ECC memory delay register */ |
81 | #define ECC_MDR_RRI 0x000003ff /* Refresh Request Interval */ |
82 | #define ECC_MDR_MI 0x00001c00 /* MIH Delay */ |
83 | #define ECC_MDR_CI 0x0000e000 /* Coherent Invalidate Delay */ |
84 | #define ECC_MDR_MDL 0x001f0000 /* MBus Master arbitration delay */ |
85 | #define ECC_MDR_MDH 0x03e00000 /* MBus Master arbitration delay */ |
86 | #define ECC_MDR_GAD 0x7c000000 /* Graphics Arbitration Delay */ |
87 | #define ECC_MDR_RSC 0x80000000 /* Refresh load control */ |
88 | #define ECC_MDR_MASK 0x7fffffff |
89 | |
90 | /* ECC fault status register */ |
91 | #define ECC_MFSR_CE 0x00000001 /* Correctable error */ |
92 | #define ECC_MFSR_BS 0x00000002 /* C2 graphics bad slot access */ |
93 | #define ECC_MFSR_TO 0x00000004 /* Timeout on write */ |
94 | #define ECC_MFSR_UE 0x00000008 /* Uncorrectable error */ |
95 | #define ECC_MFSR_DW 0x000000f0 /* Index of double word in block */ |
96 | #define ECC_MFSR_SYND 0x0000ff00 /* Syndrome for correctable error */ |
97 | #define ECC_MFSR_ME 0x00010000 /* Multiple errors */ |
98 | #define ECC_MFSR_C2ERR 0x00020000 /* C2 graphics error */ |
99 | |
100 | /* ECC fault address register 0 */ |
101 | #define ECC_MFAR0_PADDR 0x0000000f /* PA[32-35] */ |
102 | #define ECC_MFAR0_TYPE 0x000000f0 /* Transaction type */ |
103 | #define ECC_MFAR0_SIZE 0x00000700 /* Transaction size */ |
104 | #define ECC_MFAR0_CACHE 0x00000800 /* Mapped cacheable */ |
105 | #define ECC_MFAR0_LOCK 0x00001000 /* Error occurred in atomic cycle */ |
106 | #define ECC_MFAR0_BMODE 0x00002000 /* Boot mode */ |
107 | #define ECC_MFAR0_VADDR 0x003fc000 /* VA[12-19] (superset bits) */ |
108 | #define ECC_MFAR0_S 0x08000000 /* Supervisor mode */ |
109 | #define ECC_MFARO_MID 0xf0000000 /* Module ID */ |
110 | |
111 | /* ECC diagnostic register */ |
112 | #define ECC_DR_CBX 0x00000001 |
113 | #define ECC_DR_CB0 0x00000002 |
114 | #define ECC_DR_CB1 0x00000004 |
115 | #define ECC_DR_CB2 0x00000008 |
116 | #define ECC_DR_CB4 0x00000010 |
117 | #define ECC_DR_CB8 0x00000020 |
118 | #define ECC_DR_CB16 0x00000040 |
119 | #define ECC_DR_CB32 0x00000080 |
120 | #define ECC_DR_DMODE 0x00000c00 |
121 | |
122 | #define ECC_NREGS 9 |
123 | #define ECC_SIZE (ECC_NREGS * sizeof(uint32_t)) |
124 | |
125 | #define ECC_DIAG_SIZE 4 |
126 | #define ECC_DIAG_MASK (ECC_DIAG_SIZE - 1) |
127 | |
128 | #define TYPE_ECC_MEMCTL "eccmemctl" |
129 | #define ECC_MEMCTL(obj) OBJECT_CHECK(ECCState, (obj), TYPE_ECC_MEMCTL) |
130 | |
131 | typedef struct ECCState { |
132 | SysBusDevice parent_obj; |
133 | |
134 | MemoryRegion iomem, iomem_diag; |
135 | qemu_irq irq; |
136 | uint32_t regs[ECC_NREGS]; |
137 | uint8_t diag[ECC_DIAG_SIZE]; |
138 | uint32_t version; |
139 | } ECCState; |
140 | |
141 | static void ecc_mem_write(void *opaque, hwaddr addr, uint64_t val, |
142 | unsigned size) |
143 | { |
144 | ECCState *s = opaque; |
145 | |
146 | switch (addr >> 2) { |
147 | case ECC_MER: |
148 | if (s->version == ECC_MCC) |
149 | s->regs[ECC_MER] = (val & ECC_MER_MASK_0); |
150 | else if (s->version == ECC_EMC) |
151 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_1); |
152 | else if (s->version == ECC_SMC) |
153 | s->regs[ECC_MER] = s->version | (val & ECC_MER_MASK_2); |
154 | trace_ecc_mem_writel_mer(val); |
155 | break; |
156 | case ECC_MDR: |
157 | s->regs[ECC_MDR] = val & ECC_MDR_MASK; |
158 | trace_ecc_mem_writel_mdr(val); |
159 | break; |
160 | case ECC_MFSR: |
161 | s->regs[ECC_MFSR] = val; |
162 | qemu_irq_lower(s->irq); |
163 | trace_ecc_mem_writel_mfsr(val); |
164 | break; |
165 | case ECC_VCR: |
166 | s->regs[ECC_VCR] = val; |
167 | trace_ecc_mem_writel_vcr(val); |
168 | break; |
169 | case ECC_DR: |
170 | s->regs[ECC_DR] = val; |
171 | trace_ecc_mem_writel_dr(val); |
172 | break; |
173 | case ECC_ECR0: |
174 | s->regs[ECC_ECR0] = val; |
175 | trace_ecc_mem_writel_ecr0(val); |
176 | break; |
177 | case ECC_ECR1: |
178 | s->regs[ECC_ECR0] = val; |
179 | trace_ecc_mem_writel_ecr1(val); |
180 | break; |
181 | } |
182 | } |
183 | |
184 | static uint64_t ecc_mem_read(void *opaque, hwaddr addr, |
185 | unsigned size) |
186 | { |
187 | ECCState *s = opaque; |
188 | uint32_t ret = 0; |
189 | |
190 | switch (addr >> 2) { |
191 | case ECC_MER: |
192 | ret = s->regs[ECC_MER]; |
193 | trace_ecc_mem_readl_mer(ret); |
194 | break; |
195 | case ECC_MDR: |
196 | ret = s->regs[ECC_MDR]; |
197 | trace_ecc_mem_readl_mdr(ret); |
198 | break; |
199 | case ECC_MFSR: |
200 | ret = s->regs[ECC_MFSR]; |
201 | trace_ecc_mem_readl_mfsr(ret); |
202 | break; |
203 | case ECC_VCR: |
204 | ret = s->regs[ECC_VCR]; |
205 | trace_ecc_mem_readl_vcr(ret); |
206 | break; |
207 | case ECC_MFAR0: |
208 | ret = s->regs[ECC_MFAR0]; |
209 | trace_ecc_mem_readl_mfar0(ret); |
210 | break; |
211 | case ECC_MFAR1: |
212 | ret = s->regs[ECC_MFAR1]; |
213 | trace_ecc_mem_readl_mfar1(ret); |
214 | break; |
215 | case ECC_DR: |
216 | ret = s->regs[ECC_DR]; |
217 | trace_ecc_mem_readl_dr(ret); |
218 | break; |
219 | case ECC_ECR0: |
220 | ret = s->regs[ECC_ECR0]; |
221 | trace_ecc_mem_readl_ecr0(ret); |
222 | break; |
223 | case ECC_ECR1: |
224 | ret = s->regs[ECC_ECR0]; |
225 | trace_ecc_mem_readl_ecr1(ret); |
226 | break; |
227 | } |
228 | return ret; |
229 | } |
230 | |
231 | static const MemoryRegionOps ecc_mem_ops = { |
232 | .read = ecc_mem_read, |
233 | .write = ecc_mem_write, |
234 | .endianness = DEVICE_NATIVE_ENDIAN, |
235 | .valid = { |
236 | .min_access_size = 4, |
237 | .max_access_size = 4, |
238 | }, |
239 | }; |
240 | |
241 | static void ecc_diag_mem_write(void *opaque, hwaddr addr, |
242 | uint64_t val, unsigned size) |
243 | { |
244 | ECCState *s = opaque; |
245 | |
246 | trace_ecc_diag_mem_writeb(addr, val); |
247 | s->diag[addr & ECC_DIAG_MASK] = val; |
248 | } |
249 | |
250 | static uint64_t ecc_diag_mem_read(void *opaque, hwaddr addr, |
251 | unsigned size) |
252 | { |
253 | ECCState *s = opaque; |
254 | uint32_t ret = s->diag[(int)addr]; |
255 | |
256 | trace_ecc_diag_mem_readb(addr, ret); |
257 | return ret; |
258 | } |
259 | |
260 | static const MemoryRegionOps ecc_diag_mem_ops = { |
261 | .read = ecc_diag_mem_read, |
262 | .write = ecc_diag_mem_write, |
263 | .endianness = DEVICE_NATIVE_ENDIAN, |
264 | .valid = { |
265 | .min_access_size = 1, |
266 | .max_access_size = 1, |
267 | }, |
268 | }; |
269 | |
270 | static const VMStateDescription vmstate_ecc = { |
271 | .name ="ECC" , |
272 | .version_id = 3, |
273 | .minimum_version_id = 3, |
274 | .fields = (VMStateField[]) { |
275 | VMSTATE_UINT32_ARRAY(regs, ECCState, ECC_NREGS), |
276 | VMSTATE_BUFFER(diag, ECCState), |
277 | VMSTATE_UINT32(version, ECCState), |
278 | VMSTATE_END_OF_LIST() |
279 | } |
280 | }; |
281 | |
282 | static void ecc_reset(DeviceState *d) |
283 | { |
284 | ECCState *s = ECC_MEMCTL(d); |
285 | |
286 | if (s->version == ECC_MCC) { |
287 | s->regs[ECC_MER] &= ECC_MER_REU; |
288 | } else { |
289 | s->regs[ECC_MER] &= (ECC_MER_VER | ECC_MER_IMPL | ECC_MER_MRR | |
290 | ECC_MER_DCI); |
291 | } |
292 | s->regs[ECC_MDR] = 0x20; |
293 | s->regs[ECC_MFSR] = 0; |
294 | s->regs[ECC_VCR] = 0; |
295 | s->regs[ECC_MFAR0] = 0x07c00000; |
296 | s->regs[ECC_MFAR1] = 0; |
297 | s->regs[ECC_DR] = 0; |
298 | s->regs[ECC_ECR0] = 0; |
299 | s->regs[ECC_ECR1] = 0; |
300 | } |
301 | |
302 | static void ecc_init(Object *obj) |
303 | { |
304 | ECCState *s = ECC_MEMCTL(obj); |
305 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); |
306 | |
307 | sysbus_init_irq(dev, &s->irq); |
308 | |
309 | memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc" , ECC_SIZE); |
310 | sysbus_init_mmio(dev, &s->iomem); |
311 | } |
312 | |
313 | static void ecc_realize(DeviceState *dev, Error **errp) |
314 | { |
315 | ECCState *s = ECC_MEMCTL(dev); |
316 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
317 | |
318 | s->regs[0] = s->version; |
319 | |
320 | if (s->version == ECC_MCC) { // SS-600MP only |
321 | memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s, |
322 | "ecc.diag" , ECC_DIAG_SIZE); |
323 | sysbus_init_mmio(sbd, &s->iomem_diag); |
324 | } |
325 | } |
326 | |
327 | static Property ecc_properties[] = { |
328 | DEFINE_PROP_UINT32("version" , ECCState, version, -1), |
329 | DEFINE_PROP_END_OF_LIST(), |
330 | }; |
331 | |
332 | static void ecc_class_init(ObjectClass *klass, void *data) |
333 | { |
334 | DeviceClass *dc = DEVICE_CLASS(klass); |
335 | |
336 | dc->realize = ecc_realize; |
337 | dc->reset = ecc_reset; |
338 | dc->vmsd = &vmstate_ecc; |
339 | dc->props = ecc_properties; |
340 | } |
341 | |
342 | static const TypeInfo ecc_info = { |
343 | .name = TYPE_ECC_MEMCTL, |
344 | .parent = TYPE_SYS_BUS_DEVICE, |
345 | .instance_size = sizeof(ECCState), |
346 | .instance_init = ecc_init, |
347 | .class_init = ecc_class_init, |
348 | }; |
349 | |
350 | |
351 | static void ecc_register_types(void) |
352 | { |
353 | type_register_static(&ecc_info); |
354 | } |
355 | |
356 | type_init(ecc_register_types) |
357 | |