1 | /* |
2 | * QEMU model of the Milkymist High Performance Dynamic Memory Controller. |
3 | * |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | * |
19 | * |
20 | * Specification available at: |
21 | * http://milkymist.walle.cc/socdoc/hpdmc.pdf |
22 | */ |
23 | |
24 | #include "qemu/osdep.h" |
25 | #include "hw/sysbus.h" |
26 | #include "migration/vmstate.h" |
27 | #include "trace.h" |
28 | #include "qemu/error-report.h" |
29 | #include "qemu/module.h" |
30 | |
31 | enum { |
32 | R_SYSTEM = 0, |
33 | R_BYPASS, |
34 | R_TIMING, |
35 | R_IODELAY, |
36 | R_MAX |
37 | }; |
38 | |
39 | enum { |
40 | IODELAY_DQSDELAY_RDY = (1<<5), |
41 | IODELAY_PLL1_LOCKED = (1<<6), |
42 | IODELAY_PLL2_LOCKED = (1<<7), |
43 | }; |
44 | |
45 | #define TYPE_MILKYMIST_HPDMC "milkymist-hpdmc" |
46 | #define MILKYMIST_HPDMC(obj) \ |
47 | OBJECT_CHECK(MilkymistHpdmcState, (obj), TYPE_MILKYMIST_HPDMC) |
48 | |
49 | struct MilkymistHpdmcState { |
50 | SysBusDevice parent_obj; |
51 | |
52 | MemoryRegion regs_region; |
53 | |
54 | uint32_t regs[R_MAX]; |
55 | }; |
56 | typedef struct MilkymistHpdmcState MilkymistHpdmcState; |
57 | |
58 | static uint64_t hpdmc_read(void *opaque, hwaddr addr, |
59 | unsigned size) |
60 | { |
61 | MilkymistHpdmcState *s = opaque; |
62 | uint32_t r = 0; |
63 | |
64 | addr >>= 2; |
65 | switch (addr) { |
66 | case R_SYSTEM: |
67 | case R_BYPASS: |
68 | case R_TIMING: |
69 | case R_IODELAY: |
70 | r = s->regs[addr]; |
71 | break; |
72 | |
73 | default: |
74 | error_report("milkymist_hpdmc: read access to unknown register 0x" |
75 | TARGET_FMT_plx, addr << 2); |
76 | break; |
77 | } |
78 | |
79 | trace_milkymist_hpdmc_memory_read(addr << 2, r); |
80 | |
81 | return r; |
82 | } |
83 | |
84 | static void hpdmc_write(void *opaque, hwaddr addr, uint64_t value, |
85 | unsigned size) |
86 | { |
87 | MilkymistHpdmcState *s = opaque; |
88 | |
89 | trace_milkymist_hpdmc_memory_write(addr, value); |
90 | |
91 | addr >>= 2; |
92 | switch (addr) { |
93 | case R_SYSTEM: |
94 | case R_BYPASS: |
95 | case R_TIMING: |
96 | s->regs[addr] = value; |
97 | break; |
98 | case R_IODELAY: |
99 | /* ignore writes */ |
100 | break; |
101 | |
102 | default: |
103 | error_report("milkymist_hpdmc: write access to unknown register 0x" |
104 | TARGET_FMT_plx, addr << 2); |
105 | break; |
106 | } |
107 | } |
108 | |
109 | static const MemoryRegionOps hpdmc_mmio_ops = { |
110 | .read = hpdmc_read, |
111 | .write = hpdmc_write, |
112 | .valid = { |
113 | .min_access_size = 4, |
114 | .max_access_size = 4, |
115 | }, |
116 | .endianness = DEVICE_NATIVE_ENDIAN, |
117 | }; |
118 | |
119 | static void milkymist_hpdmc_reset(DeviceState *d) |
120 | { |
121 | MilkymistHpdmcState *s = MILKYMIST_HPDMC(d); |
122 | int i; |
123 | |
124 | for (i = 0; i < R_MAX; i++) { |
125 | s->regs[i] = 0; |
126 | } |
127 | |
128 | /* defaults */ |
129 | s->regs[R_IODELAY] = IODELAY_DQSDELAY_RDY | IODELAY_PLL1_LOCKED |
130 | | IODELAY_PLL2_LOCKED; |
131 | } |
132 | |
133 | static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp) |
134 | { |
135 | MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev); |
136 | |
137 | memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s, |
138 | "milkymist-hpdmc" , R_MAX * 4); |
139 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region); |
140 | } |
141 | |
142 | static const VMStateDescription vmstate_milkymist_hpdmc = { |
143 | .name = "milkymist-hpdmc" , |
144 | .version_id = 1, |
145 | .minimum_version_id = 1, |
146 | .fields = (VMStateField[]) { |
147 | VMSTATE_UINT32_ARRAY(regs, MilkymistHpdmcState, R_MAX), |
148 | VMSTATE_END_OF_LIST() |
149 | } |
150 | }; |
151 | |
152 | static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data) |
153 | { |
154 | DeviceClass *dc = DEVICE_CLASS(klass); |
155 | |
156 | dc->realize = milkymist_hpdmc_realize; |
157 | dc->reset = milkymist_hpdmc_reset; |
158 | dc->vmsd = &vmstate_milkymist_hpdmc; |
159 | } |
160 | |
161 | static const TypeInfo milkymist_hpdmc_info = { |
162 | .name = TYPE_MILKYMIST_HPDMC, |
163 | .parent = TYPE_SYS_BUS_DEVICE, |
164 | .instance_size = sizeof(MilkymistHpdmcState), |
165 | .class_init = milkymist_hpdmc_class_init, |
166 | }; |
167 | |
168 | static void milkymist_hpdmc_register_types(void) |
169 | { |
170 | type_register_static(&milkymist_hpdmc_info); |
171 | } |
172 | |
173 | type_init(milkymist_hpdmc_register_types) |
174 | |