1 | /* |
2 | * ARM MPS2 AN505 FPGAIO emulation |
3 | * |
4 | * Copyright (c) 2018 Linaro Limited |
5 | * Written by Peter Maydell |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 or |
9 | * (at your option) any later version. |
10 | */ |
11 | |
12 | /* This is a model of the "FPGA system control and I/O" block found |
13 | * in the AN505 FPGA image for the MPS2 devboard. |
14 | * It is documented in AN505: |
15 | * http://infocenter.arm.com/help/topic/com.arm.doc.dai0505b/index.html |
16 | */ |
17 | |
18 | #include "qemu/osdep.h" |
19 | #include "qemu/log.h" |
20 | #include "qemu/module.h" |
21 | #include "qapi/error.h" |
22 | #include "trace.h" |
23 | #include "hw/sysbus.h" |
24 | #include "migration/vmstate.h" |
25 | #include "hw/registerfields.h" |
26 | #include "hw/misc/mps2-fpgaio.h" |
27 | #include "hw/qdev-properties.h" |
28 | #include "qemu/timer.h" |
29 | |
30 | REG32(LED0, 0) |
31 | REG32(BUTTON, 8) |
32 | REG32(CLK1HZ, 0x10) |
33 | REG32(CLK100HZ, 0x14) |
34 | REG32(COUNTER, 0x18) |
35 | REG32(PRESCALE, 0x1c) |
36 | REG32(PSCNTR, 0x20) |
37 | REG32(MISC, 0x4c) |
38 | |
39 | static uint32_t counter_from_tickoff(int64_t now, int64_t tick_offset, int frq) |
40 | { |
41 | return muldiv64(now - tick_offset, frq, NANOSECONDS_PER_SECOND); |
42 | } |
43 | |
44 | static int64_t tickoff_from_counter(int64_t now, uint32_t count, int frq) |
45 | { |
46 | return now - muldiv64(count, NANOSECONDS_PER_SECOND, frq); |
47 | } |
48 | |
49 | static void resync_counter(MPS2FPGAIO *s) |
50 | { |
51 | /* |
52 | * Update s->counter and s->pscntr to their true current values |
53 | * by calculating how many times PSCNTR has ticked since the |
54 | * last time we did a resync. |
55 | */ |
56 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
57 | int64_t elapsed = now - s->pscntr_sync_ticks; |
58 | |
59 | /* |
60 | * Round elapsed down to a whole number of PSCNTR ticks, so we don't |
61 | * lose time if we do multiple resyncs in a single tick. |
62 | */ |
63 | uint64_t ticks = muldiv64(elapsed, s->prescale_clk, NANOSECONDS_PER_SECOND); |
64 | |
65 | /* |
66 | * Work out what PSCNTR and COUNTER have moved to. We assume that |
67 | * PSCNTR reloads from PRESCALE one tick-period after it hits zero, |
68 | * and that COUNTER increments at the same moment. |
69 | */ |
70 | if (ticks == 0) { |
71 | /* We haven't ticked since the last time we were asked */ |
72 | return; |
73 | } else if (ticks < s->pscntr) { |
74 | /* We haven't yet reached zero, just reduce the PSCNTR */ |
75 | s->pscntr -= ticks; |
76 | } else { |
77 | if (s->prescale == 0) { |
78 | /* |
79 | * If the reload value is zero then the PSCNTR will stick |
80 | * at zero once it reaches it, and so we will increment |
81 | * COUNTER every tick after that. |
82 | */ |
83 | s->counter += ticks - s->pscntr; |
84 | s->pscntr = 0; |
85 | } else { |
86 | /* |
87 | * This is the complicated bit. This ASCII art diagram gives an |
88 | * example with PRESCALE==5 PSCNTR==7: |
89 | * |
90 | * ticks 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 |
91 | * PSCNTR 7 6 5 4 3 2 1 0 5 4 3 2 1 0 5 |
92 | * cinc 1 2 |
93 | * y 0 1 2 3 4 5 6 7 8 9 10 11 12 |
94 | * x 0 1 2 3 4 5 0 1 2 3 4 5 0 |
95 | * |
96 | * where x = y % (s->prescale + 1) |
97 | * and so PSCNTR = s->prescale - x |
98 | * and COUNTER is incremented by y / (s->prescale + 1) |
99 | * |
100 | * The case where PSCNTR < PRESCALE works out the same, |
101 | * though we must be careful to calculate y as 64-bit unsigned |
102 | * for all parts of the expression. |
103 | * y < 0 is not possible because that implies ticks < s->pscntr. |
104 | */ |
105 | uint64_t y = ticks - s->pscntr + s->prescale; |
106 | s->pscntr = s->prescale - (y % (s->prescale + 1)); |
107 | s->counter += y / (s->prescale + 1); |
108 | } |
109 | } |
110 | |
111 | /* |
112 | * Only advance the sync time to the timestamp of the last PSCNTR tick, |
113 | * not all the way to 'now', so we don't lose time if we do multiple |
114 | * resyncs in a single tick. |
115 | */ |
116 | s->pscntr_sync_ticks += muldiv64(ticks, NANOSECONDS_PER_SECOND, |
117 | s->prescale_clk); |
118 | } |
119 | |
120 | static uint64_t mps2_fpgaio_read(void *opaque, hwaddr offset, unsigned size) |
121 | { |
122 | MPS2FPGAIO *s = MPS2_FPGAIO(opaque); |
123 | uint64_t r; |
124 | int64_t now; |
125 | |
126 | switch (offset) { |
127 | case A_LED0: |
128 | r = s->led0; |
129 | break; |
130 | case A_BUTTON: |
131 | /* User-pressable board buttons. We don't model that, so just return |
132 | * zeroes. |
133 | */ |
134 | r = 0; |
135 | break; |
136 | case A_PRESCALE: |
137 | r = s->prescale; |
138 | break; |
139 | case A_MISC: |
140 | r = s->misc; |
141 | break; |
142 | case A_CLK1HZ: |
143 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
144 | r = counter_from_tickoff(now, s->clk1hz_tick_offset, 1); |
145 | break; |
146 | case A_CLK100HZ: |
147 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
148 | r = counter_from_tickoff(now, s->clk100hz_tick_offset, 100); |
149 | break; |
150 | case A_COUNTER: |
151 | resync_counter(s); |
152 | r = s->counter; |
153 | break; |
154 | case A_PSCNTR: |
155 | resync_counter(s); |
156 | r = s->pscntr; |
157 | break; |
158 | default: |
159 | qemu_log_mask(LOG_GUEST_ERROR, |
160 | "MPS2 FPGAIO read: bad offset %x\n" , (int) offset); |
161 | r = 0; |
162 | break; |
163 | } |
164 | |
165 | trace_mps2_fpgaio_read(offset, r, size); |
166 | return r; |
167 | } |
168 | |
169 | static void mps2_fpgaio_write(void *opaque, hwaddr offset, uint64_t value, |
170 | unsigned size) |
171 | { |
172 | MPS2FPGAIO *s = MPS2_FPGAIO(opaque); |
173 | int64_t now; |
174 | |
175 | trace_mps2_fpgaio_write(offset, value, size); |
176 | |
177 | switch (offset) { |
178 | case A_LED0: |
179 | /* LED bits [1:0] control board LEDs. We don't currently have |
180 | * a mechanism for displaying this graphically, so use a trace event. |
181 | */ |
182 | trace_mps2_fpgaio_leds(value & 0x02 ? '*' : '.', |
183 | value & 0x01 ? '*' : '.'); |
184 | s->led0 = value & 0x3; |
185 | break; |
186 | case A_PRESCALE: |
187 | resync_counter(s); |
188 | s->prescale = value; |
189 | break; |
190 | case A_MISC: |
191 | /* These are control bits for some of the other devices on the |
192 | * board (SPI, CLCD, etc). We don't implement that yet, so just |
193 | * make the bits read as written. |
194 | */ |
195 | qemu_log_mask(LOG_UNIMP, |
196 | "MPS2 FPGAIO: MISC control bits unimplemented\n" ); |
197 | s->misc = value; |
198 | break; |
199 | case A_CLK1HZ: |
200 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
201 | s->clk1hz_tick_offset = tickoff_from_counter(now, value, 1); |
202 | break; |
203 | case A_CLK100HZ: |
204 | now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
205 | s->clk100hz_tick_offset = tickoff_from_counter(now, value, 100); |
206 | break; |
207 | case A_COUNTER: |
208 | resync_counter(s); |
209 | s->counter = value; |
210 | break; |
211 | case A_PSCNTR: |
212 | resync_counter(s); |
213 | s->pscntr = value; |
214 | break; |
215 | default: |
216 | qemu_log_mask(LOG_GUEST_ERROR, |
217 | "MPS2 FPGAIO write: bad offset 0x%x\n" , (int) offset); |
218 | break; |
219 | } |
220 | } |
221 | |
222 | static const MemoryRegionOps mps2_fpgaio_ops = { |
223 | .read = mps2_fpgaio_read, |
224 | .write = mps2_fpgaio_write, |
225 | .endianness = DEVICE_LITTLE_ENDIAN, |
226 | }; |
227 | |
228 | static void mps2_fpgaio_reset(DeviceState *dev) |
229 | { |
230 | MPS2FPGAIO *s = MPS2_FPGAIO(dev); |
231 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
232 | |
233 | trace_mps2_fpgaio_reset(); |
234 | s->led0 = 0; |
235 | s->prescale = 0; |
236 | s->misc = 0; |
237 | s->clk1hz_tick_offset = tickoff_from_counter(now, 0, 1); |
238 | s->clk100hz_tick_offset = tickoff_from_counter(now, 0, 100); |
239 | s->counter = 0; |
240 | s->pscntr = 0; |
241 | s->pscntr_sync_ticks = now; |
242 | } |
243 | |
244 | static void mps2_fpgaio_init(Object *obj) |
245 | { |
246 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
247 | MPS2FPGAIO *s = MPS2_FPGAIO(obj); |
248 | |
249 | memory_region_init_io(&s->iomem, obj, &mps2_fpgaio_ops, s, |
250 | "mps2-fpgaio" , 0x1000); |
251 | sysbus_init_mmio(sbd, &s->iomem); |
252 | } |
253 | |
254 | static bool mps2_fpgaio_counters_needed(void *opaque) |
255 | { |
256 | /* Currently vmstate.c insists all subsections have a 'needed' function */ |
257 | return true; |
258 | } |
259 | |
260 | static const VMStateDescription mps2_fpgaio_counters_vmstate = { |
261 | .name = "mps2-fpgaio/counters" , |
262 | .version_id = 2, |
263 | .minimum_version_id = 2, |
264 | .needed = mps2_fpgaio_counters_needed, |
265 | .fields = (VMStateField[]) { |
266 | VMSTATE_INT64(clk1hz_tick_offset, MPS2FPGAIO), |
267 | VMSTATE_INT64(clk100hz_tick_offset, MPS2FPGAIO), |
268 | VMSTATE_UINT32(counter, MPS2FPGAIO), |
269 | VMSTATE_UINT32(pscntr, MPS2FPGAIO), |
270 | VMSTATE_INT64(pscntr_sync_ticks, MPS2FPGAIO), |
271 | VMSTATE_END_OF_LIST() |
272 | } |
273 | }; |
274 | |
275 | static const VMStateDescription mps2_fpgaio_vmstate = { |
276 | .name = "mps2-fpgaio" , |
277 | .version_id = 1, |
278 | .minimum_version_id = 1, |
279 | .fields = (VMStateField[]) { |
280 | VMSTATE_UINT32(led0, MPS2FPGAIO), |
281 | VMSTATE_UINT32(prescale, MPS2FPGAIO), |
282 | VMSTATE_UINT32(misc, MPS2FPGAIO), |
283 | VMSTATE_END_OF_LIST() |
284 | }, |
285 | .subsections = (const VMStateDescription*[]) { |
286 | &mps2_fpgaio_counters_vmstate, |
287 | NULL |
288 | } |
289 | }; |
290 | |
291 | static Property mps2_fpgaio_properties[] = { |
292 | /* Frequency of the prescale counter */ |
293 | DEFINE_PROP_UINT32("prescale-clk" , MPS2FPGAIO, prescale_clk, 20000000), |
294 | DEFINE_PROP_END_OF_LIST(), |
295 | }; |
296 | |
297 | static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) |
298 | { |
299 | DeviceClass *dc = DEVICE_CLASS(klass); |
300 | |
301 | dc->vmsd = &mps2_fpgaio_vmstate; |
302 | dc->reset = mps2_fpgaio_reset; |
303 | dc->props = mps2_fpgaio_properties; |
304 | } |
305 | |
306 | static const TypeInfo mps2_fpgaio_info = { |
307 | .name = TYPE_MPS2_FPGAIO, |
308 | .parent = TYPE_SYS_BUS_DEVICE, |
309 | .instance_size = sizeof(MPS2FPGAIO), |
310 | .instance_init = mps2_fpgaio_init, |
311 | .class_init = mps2_fpgaio_class_init, |
312 | }; |
313 | |
314 | static void mps2_fpgaio_register_types(void) |
315 | { |
316 | type_register_static(&mps2_fpgaio_info); |
317 | } |
318 | |
319 | type_init(mps2_fpgaio_register_types); |
320 | |