1/*
2 * QEMU Cadence GEM emulation
3 *
4 * Copyright (c) 2011 Xilinx, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "qemu/osdep.h"
26#include <zlib.h> /* For crc32 */
27
28#include "hw/irq.h"
29#include "hw/net/cadence_gem.h"
30#include "hw/qdev-properties.h"
31#include "migration/vmstate.h"
32#include "qapi/error.h"
33#include "qemu/log.h"
34#include "qemu/module.h"
35#include "sysemu/dma.h"
36#include "net/checksum.h"
37
38#ifdef CADENCE_GEM_ERR_DEBUG
39#define DB_PRINT(...) do { \
40 fprintf(stderr, ": %s: ", __func__); \
41 fprintf(stderr, ## __VA_ARGS__); \
42 } while (0)
43#else
44 #define DB_PRINT(...)
45#endif
46
47#define GEM_NWCTRL (0x00000000/4) /* Network Control reg */
48#define GEM_NWCFG (0x00000004/4) /* Network Config reg */
49#define GEM_NWSTATUS (0x00000008/4) /* Network Status reg */
50#define GEM_USERIO (0x0000000C/4) /* User IO reg */
51#define GEM_DMACFG (0x00000010/4) /* DMA Control reg */
52#define GEM_TXSTATUS (0x00000014/4) /* TX Status reg */
53#define GEM_RXQBASE (0x00000018/4) /* RX Q Base address reg */
54#define GEM_TXQBASE (0x0000001C/4) /* TX Q Base address reg */
55#define GEM_RXSTATUS (0x00000020/4) /* RX Status reg */
56#define GEM_ISR (0x00000024/4) /* Interrupt Status reg */
57#define GEM_IER (0x00000028/4) /* Interrupt Enable reg */
58#define GEM_IDR (0x0000002C/4) /* Interrupt Disable reg */
59#define GEM_IMR (0x00000030/4) /* Interrupt Mask reg */
60#define GEM_PHYMNTNC (0x00000034/4) /* Phy Maintenance reg */
61#define GEM_RXPAUSE (0x00000038/4) /* RX Pause Time reg */
62#define GEM_TXPAUSE (0x0000003C/4) /* TX Pause Time reg */
63#define GEM_TXPARTIALSF (0x00000040/4) /* TX Partial Store and Forward */
64#define GEM_RXPARTIALSF (0x00000044/4) /* RX Partial Store and Forward */
65#define GEM_HASHLO (0x00000080/4) /* Hash Low address reg */
66#define GEM_HASHHI (0x00000084/4) /* Hash High address reg */
67#define GEM_SPADDR1LO (0x00000088/4) /* Specific addr 1 low reg */
68#define GEM_SPADDR1HI (0x0000008C/4) /* Specific addr 1 high reg */
69#define GEM_SPADDR2LO (0x00000090/4) /* Specific addr 2 low reg */
70#define GEM_SPADDR2HI (0x00000094/4) /* Specific addr 2 high reg */
71#define GEM_SPADDR3LO (0x00000098/4) /* Specific addr 3 low reg */
72#define GEM_SPADDR3HI (0x0000009C/4) /* Specific addr 3 high reg */
73#define GEM_SPADDR4LO (0x000000A0/4) /* Specific addr 4 low reg */
74#define GEM_SPADDR4HI (0x000000A4/4) /* Specific addr 4 high reg */
75#define GEM_TIDMATCH1 (0x000000A8/4) /* Type ID1 Match reg */
76#define GEM_TIDMATCH2 (0x000000AC/4) /* Type ID2 Match reg */
77#define GEM_TIDMATCH3 (0x000000B0/4) /* Type ID3 Match reg */
78#define GEM_TIDMATCH4 (0x000000B4/4) /* Type ID4 Match reg */
79#define GEM_WOLAN (0x000000B8/4) /* Wake on LAN reg */
80#define GEM_IPGSTRETCH (0x000000BC/4) /* IPG Stretch reg */
81#define GEM_SVLAN (0x000000C0/4) /* Stacked VLAN reg */
82#define GEM_MODID (0x000000FC/4) /* Module ID reg */
83#define GEM_OCTTXLO (0x00000100/4) /* Octects transmitted Low reg */
84#define GEM_OCTTXHI (0x00000104/4) /* Octects transmitted High reg */
85#define GEM_TXCNT (0x00000108/4) /* Error-free Frames transmitted */
86#define GEM_TXBCNT (0x0000010C/4) /* Error-free Broadcast Frames */
87#define GEM_TXMCNT (0x00000110/4) /* Error-free Multicast Frame */
88#define GEM_TXPAUSECNT (0x00000114/4) /* Pause Frames Transmitted */
89#define GEM_TX64CNT (0x00000118/4) /* Error-free 64 TX */
90#define GEM_TX65CNT (0x0000011C/4) /* Error-free 65-127 TX */
91#define GEM_TX128CNT (0x00000120/4) /* Error-free 128-255 TX */
92#define GEM_TX256CNT (0x00000124/4) /* Error-free 256-511 */
93#define GEM_TX512CNT (0x00000128/4) /* Error-free 512-1023 TX */
94#define GEM_TX1024CNT (0x0000012C/4) /* Error-free 1024-1518 TX */
95#define GEM_TX1519CNT (0x00000130/4) /* Error-free larger than 1519 TX */
96#define GEM_TXURUNCNT (0x00000134/4) /* TX under run error counter */
97#define GEM_SINGLECOLLCNT (0x00000138/4) /* Single Collision Frames */
98#define GEM_MULTCOLLCNT (0x0000013C/4) /* Multiple Collision Frames */
99#define GEM_EXCESSCOLLCNT (0x00000140/4) /* Excessive Collision Frames */
100#define GEM_LATECOLLCNT (0x00000144/4) /* Late Collision Frames */
101#define GEM_DEFERTXCNT (0x00000148/4) /* Deferred Transmission Frames */
102#define GEM_CSENSECNT (0x0000014C/4) /* Carrier Sense Error Counter */
103#define GEM_OCTRXLO (0x00000150/4) /* Octects Received register Low */
104#define GEM_OCTRXHI (0x00000154/4) /* Octects Received register High */
105#define GEM_RXCNT (0x00000158/4) /* Error-free Frames Received */
106#define GEM_RXBROADCNT (0x0000015C/4) /* Error-free Broadcast Frames RX */
107#define GEM_RXMULTICNT (0x00000160/4) /* Error-free Multicast Frames RX */
108#define GEM_RXPAUSECNT (0x00000164/4) /* Pause Frames Received Counter */
109#define GEM_RX64CNT (0x00000168/4) /* Error-free 64 byte Frames RX */
110#define GEM_RX65CNT (0x0000016C/4) /* Error-free 65-127B Frames RX */
111#define GEM_RX128CNT (0x00000170/4) /* Error-free 128-255B Frames RX */
112#define GEM_RX256CNT (0x00000174/4) /* Error-free 256-512B Frames RX */
113#define GEM_RX512CNT (0x00000178/4) /* Error-free 512-1023B Frames RX */
114#define GEM_RX1024CNT (0x0000017C/4) /* Error-free 1024-1518B Frames RX */
115#define GEM_RX1519CNT (0x00000180/4) /* Error-free 1519-max Frames RX */
116#define GEM_RXUNDERCNT (0x00000184/4) /* Undersize Frames Received */
117#define GEM_RXOVERCNT (0x00000188/4) /* Oversize Frames Received */
118#define GEM_RXJABCNT (0x0000018C/4) /* Jabbers Received Counter */
119#define GEM_RXFCSCNT (0x00000190/4) /* Frame Check seq. Error Counter */
120#define GEM_RXLENERRCNT (0x00000194/4) /* Length Field Error Counter */
121#define GEM_RXSYMERRCNT (0x00000198/4) /* Symbol Error Counter */
122#define GEM_RXALIGNERRCNT (0x0000019C/4) /* Alignment Error Counter */
123#define GEM_RXRSCERRCNT (0x000001A0/4) /* Receive Resource Error Counter */
124#define GEM_RXORUNCNT (0x000001A4/4) /* Receive Overrun Counter */
125#define GEM_RXIPCSERRCNT (0x000001A8/4) /* IP header Checksum Error Counter */
126#define GEM_RXTCPCCNT (0x000001AC/4) /* TCP Checksum Error Counter */
127#define GEM_RXUDPCCNT (0x000001B0/4) /* UDP Checksum Error Counter */
128
129#define GEM_1588S (0x000001D0/4) /* 1588 Timer Seconds */
130#define GEM_1588NS (0x000001D4/4) /* 1588 Timer Nanoseconds */
131#define GEM_1588ADJ (0x000001D8/4) /* 1588 Timer Adjust */
132#define GEM_1588INC (0x000001DC/4) /* 1588 Timer Increment */
133#define GEM_PTPETXS (0x000001E0/4) /* PTP Event Frame Transmitted (s) */
134#define GEM_PTPETXNS (0x000001E4/4) /* PTP Event Frame Transmitted (ns) */
135#define GEM_PTPERXS (0x000001E8/4) /* PTP Event Frame Received (s) */
136#define GEM_PTPERXNS (0x000001EC/4) /* PTP Event Frame Received (ns) */
137#define GEM_PTPPTXS (0x000001E0/4) /* PTP Peer Frame Transmitted (s) */
138#define GEM_PTPPTXNS (0x000001E4/4) /* PTP Peer Frame Transmitted (ns) */
139#define GEM_PTPPRXS (0x000001E8/4) /* PTP Peer Frame Received (s) */
140#define GEM_PTPPRXNS (0x000001EC/4) /* PTP Peer Frame Received (ns) */
141
142/* Design Configuration Registers */
143#define GEM_DESCONF (0x00000280/4)
144#define GEM_DESCONF2 (0x00000284/4)
145#define GEM_DESCONF3 (0x00000288/4)
146#define GEM_DESCONF4 (0x0000028C/4)
147#define GEM_DESCONF5 (0x00000290/4)
148#define GEM_DESCONF6 (0x00000294/4)
149#define GEM_DESCONF6_64B_MASK (1U << 23)
150#define GEM_DESCONF7 (0x00000298/4)
151
152#define GEM_INT_Q1_STATUS (0x00000400 / 4)
153#define GEM_INT_Q1_MASK (0x00000640 / 4)
154
155#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
156#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
157
158#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
159#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
160
161#define GEM_TBQPH (0x000004C8 / 4)
162#define GEM_RBQPH (0x000004D4 / 4)
163
164#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
165#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
166
167#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
168#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
169
170#define GEM_INT_Q1_MASK (0x00000640 / 4)
171#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
172
173#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
174
175#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
176#define GEM_ST1R_DSTC_ENABLE (1 << 28)
177#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
178#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
179#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
180#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
181#define GEM_ST1R_QUEUE_SHIFT (0)
182#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
183
184#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
185
186#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
187#define GEM_ST2R_COMPARE_A_SHIFT (13)
188#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
189#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
190#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
191#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
192 + 1)
193#define GEM_ST2R_QUEUE_SHIFT (0)
194#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
195
196#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
197#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
198
199#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
200#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
201#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
202#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
203
204/*****************************************/
205#define GEM_NWCTRL_TXSTART 0x00000200 /* Transmit Enable */
206#define GEM_NWCTRL_TXENA 0x00000008 /* Transmit Enable */
207#define GEM_NWCTRL_RXENA 0x00000004 /* Receive Enable */
208#define GEM_NWCTRL_LOCALLOOP 0x00000002 /* Local Loopback */
209
210#define GEM_NWCFG_STRIP_FCS 0x00020000 /* Strip FCS field */
211#define GEM_NWCFG_LERR_DISC 0x00010000 /* Discard RX frames with len err */
212#define GEM_NWCFG_BUFF_OFST_M 0x0000C000 /* Receive buffer offset mask */
213#define GEM_NWCFG_BUFF_OFST_S 14 /* Receive buffer offset shift */
214#define GEM_NWCFG_UCAST_HASH 0x00000080 /* accept unicast if hash match */
215#define GEM_NWCFG_MCAST_HASH 0x00000040 /* accept multicast if hash match */
216#define GEM_NWCFG_BCAST_REJ 0x00000020 /* Reject broadcast packets */
217#define GEM_NWCFG_PROMISC 0x00000010 /* Accept all packets */
218
219#define GEM_DMACFG_ADDR_64B (1U << 30)
220#define GEM_DMACFG_TX_BD_EXT (1U << 29)
221#define GEM_DMACFG_RX_BD_EXT (1U << 28)
222#define GEM_DMACFG_RBUFSZ_M 0x00FF0000 /* DMA RX Buffer Size mask */
223#define GEM_DMACFG_RBUFSZ_S 16 /* DMA RX Buffer Size shift */
224#define GEM_DMACFG_RBUFSZ_MUL 64 /* DMA RX Buffer Size multiplier */
225#define GEM_DMACFG_TXCSUM_OFFL 0x00000800 /* Transmit checksum offload */
226
227#define GEM_TXSTATUS_TXCMPL 0x00000020 /* Transmit Complete */
228#define GEM_TXSTATUS_USED 0x00000001 /* sw owned descriptor encountered */
229
230#define GEM_RXSTATUS_FRMRCVD 0x00000002 /* Frame received */
231#define GEM_RXSTATUS_NOBUF 0x00000001 /* Buffer unavailable */
232
233/* GEM_ISR GEM_IER GEM_IDR GEM_IMR */
234#define GEM_INT_TXCMPL 0x00000080 /* Transmit Complete */
235#define GEM_INT_TXUSED 0x00000008
236#define GEM_INT_RXUSED 0x00000004
237#define GEM_INT_RXCMPL 0x00000002
238
239#define GEM_PHYMNTNC_OP_R 0x20000000 /* read operation */
240#define GEM_PHYMNTNC_OP_W 0x10000000 /* write operation */
241#define GEM_PHYMNTNC_ADDR 0x0F800000 /* Address bits */
242#define GEM_PHYMNTNC_ADDR_SHFT 23
243#define GEM_PHYMNTNC_REG 0x007C0000 /* register bits */
244#define GEM_PHYMNTNC_REG_SHIFT 18
245
246/* Marvell PHY definitions */
247#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at */
248
249#define PHY_REG_CONTROL 0
250#define PHY_REG_STATUS 1
251#define PHY_REG_PHYID1 2
252#define PHY_REG_PHYID2 3
253#define PHY_REG_ANEGADV 4
254#define PHY_REG_LINKPABIL 5
255#define PHY_REG_ANEGEXP 6
256#define PHY_REG_NEXTP 7
257#define PHY_REG_LINKPNEXTP 8
258#define PHY_REG_100BTCTRL 9
259#define PHY_REG_1000BTSTAT 10
260#define PHY_REG_EXTSTAT 15
261#define PHY_REG_PHYSPCFC_CTL 16
262#define PHY_REG_PHYSPCFC_ST 17
263#define PHY_REG_INT_EN 18
264#define PHY_REG_INT_ST 19
265#define PHY_REG_EXT_PHYSPCFC_CTL 20
266#define PHY_REG_RXERR 21
267#define PHY_REG_EACD 22
268#define PHY_REG_LED 24
269#define PHY_REG_LED_OVRD 25
270#define PHY_REG_EXT_PHYSPCFC_CTL2 26
271#define PHY_REG_EXT_PHYSPCFC_ST 27
272#define PHY_REG_CABLE_DIAG 28
273
274#define PHY_REG_CONTROL_RST 0x8000
275#define PHY_REG_CONTROL_LOOP 0x4000
276#define PHY_REG_CONTROL_ANEG 0x1000
277
278#define PHY_REG_STATUS_LINK 0x0004
279#define PHY_REG_STATUS_ANEGCMPL 0x0020
280
281#define PHY_REG_INT_ST_ANEGCMPL 0x0800
282#define PHY_REG_INT_ST_LINKC 0x0400
283#define PHY_REG_INT_ST_ENERGY 0x0010
284
285/***********************************************************************/
286#define GEM_RX_REJECT (-1)
287#define GEM_RX_PROMISCUOUS_ACCEPT (-2)
288#define GEM_RX_BROADCAST_ACCEPT (-3)
289#define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
290#define GEM_RX_UNICAST_HASH_ACCEPT (-5)
291
292#define GEM_RX_SAR_ACCEPT 0
293
294/***********************************************************************/
295
296#define DESC_1_USED 0x80000000
297#define DESC_1_LENGTH 0x00001FFF
298
299#define DESC_1_TX_WRAP 0x40000000
300#define DESC_1_TX_LAST 0x00008000
301
302#define DESC_0_RX_WRAP 0x00000002
303#define DESC_0_RX_OWNERSHIP 0x00000001
304
305#define R_DESC_1_RX_SAR_SHIFT 25
306#define R_DESC_1_RX_SAR_LENGTH 2
307#define R_DESC_1_RX_SAR_MATCH (1 << 27)
308#define R_DESC_1_RX_UNICAST_HASH (1 << 29)
309#define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
310#define R_DESC_1_RX_BROADCAST (1 << 31)
311
312#define DESC_1_RX_SOF 0x00004000
313#define DESC_1_RX_EOF 0x00008000
314
315#define GEM_MODID_VALUE 0x00020118
316
317static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
318{
319 uint64_t ret = desc[0];
320
321 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
322 ret |= (uint64_t)desc[2] << 32;
323 }
324 return ret;
325}
326
327static inline unsigned tx_desc_get_used(uint32_t *desc)
328{
329 return (desc[1] & DESC_1_USED) ? 1 : 0;
330}
331
332static inline void tx_desc_set_used(uint32_t *desc)
333{
334 desc[1] |= DESC_1_USED;
335}
336
337static inline unsigned tx_desc_get_wrap(uint32_t *desc)
338{
339 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
340}
341
342static inline unsigned tx_desc_get_last(uint32_t *desc)
343{
344 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
345}
346
347static inline void tx_desc_set_last(uint32_t *desc)
348{
349 desc[1] |= DESC_1_TX_LAST;
350}
351
352static inline unsigned tx_desc_get_length(uint32_t *desc)
353{
354 return desc[1] & DESC_1_LENGTH;
355}
356
357static inline void print_gem_tx_desc(uint32_t *desc, uint8_t queue)
358{
359 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
360 DB_PRINT("bufaddr: 0x%08x\n", *desc);
361 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
362 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
363 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
364 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
365}
366
367static inline uint64_t rx_desc_get_buffer(CadenceGEMState *s, uint32_t *desc)
368{
369 uint64_t ret = desc[0] & ~0x3UL;
370
371 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
372 ret |= (uint64_t)desc[2] << 32;
373 }
374 return ret;
375}
376
377static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
378{
379 int ret = 2;
380
381 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
382 ret += 2;
383 }
384 if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
385 : GEM_DMACFG_TX_BD_EXT)) {
386 ret += 2;
387 }
388
389 assert(ret <= DESC_MAX_NUM_WORDS);
390 return ret;
391}
392
393static inline unsigned rx_desc_get_wrap(uint32_t *desc)
394{
395 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
396}
397
398static inline unsigned rx_desc_get_ownership(uint32_t *desc)
399{
400 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
401}
402
403static inline void rx_desc_set_ownership(uint32_t *desc)
404{
405 desc[0] |= DESC_0_RX_OWNERSHIP;
406}
407
408static inline void rx_desc_set_sof(uint32_t *desc)
409{
410 desc[1] |= DESC_1_RX_SOF;
411}
412
413static inline void rx_desc_set_eof(uint32_t *desc)
414{
415 desc[1] |= DESC_1_RX_EOF;
416}
417
418static inline void rx_desc_set_length(uint32_t *desc, unsigned len)
419{
420 desc[1] &= ~DESC_1_LENGTH;
421 desc[1] |= len;
422}
423
424static inline void rx_desc_set_broadcast(uint32_t *desc)
425{
426 desc[1] |= R_DESC_1_RX_BROADCAST;
427}
428
429static inline void rx_desc_set_unicast_hash(uint32_t *desc)
430{
431 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
432}
433
434static inline void rx_desc_set_multicast_hash(uint32_t *desc)
435{
436 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
437}
438
439static inline void rx_desc_set_sar(uint32_t *desc, int sar_idx)
440{
441 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
442 sar_idx);
443 desc[1] |= R_DESC_1_RX_SAR_MATCH;
444}
445
446/* The broadcast MAC address: 0xFFFFFFFFFFFF */
447static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
448
449/*
450 * gem_init_register_masks:
451 * One time initialization.
452 * Set masks to identify which register bits have magical clear properties
453 */
454static void gem_init_register_masks(CadenceGEMState *s)
455{
456 /* Mask of register bits which are read only */
457 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
458 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
459 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
460 s->regs_ro[GEM_DMACFG] = 0x8E00F000;
461 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
462 s->regs_ro[GEM_RXQBASE] = 0x00000003;
463 s->regs_ro[GEM_TXQBASE] = 0x00000003;
464 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
465 s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
466 s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
467 s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
468
469 /* Mask of register bits which are clear on read */
470 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
471 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
472
473 /* Mask of register bits which are write 1 to clear */
474 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
475 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
476 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
477
478 /* Mask of register bits which are write only */
479 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
480 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
481 s->regs_wo[GEM_IER] = 0x07FFFFFF;
482 s->regs_wo[GEM_IDR] = 0x07FFFFFF;
483}
484
485/*
486 * phy_update_link:
487 * Make the emulated PHY link state match the QEMU "interface" state.
488 */
489static void phy_update_link(CadenceGEMState *s)
490{
491 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
492
493 /* Autonegotiation status mirrors link status. */
494 if (qemu_get_queue(s->nic)->link_down) {
495 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
496 PHY_REG_STATUS_LINK);
497 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
498 } else {
499 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
500 PHY_REG_STATUS_LINK);
501 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
502 PHY_REG_INT_ST_ANEGCMPL |
503 PHY_REG_INT_ST_ENERGY);
504 }
505}
506
507static int gem_can_receive(NetClientState *nc)
508{
509 CadenceGEMState *s;
510 int i;
511
512 s = qemu_get_nic_opaque(nc);
513
514 /* Do nothing if receive is not enabled. */
515 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
516 if (s->can_rx_state != 1) {
517 s->can_rx_state = 1;
518 DB_PRINT("can't receive - no enable\n");
519 }
520 return 0;
521 }
522
523 for (i = 0; i < s->num_priority_queues; i++) {
524 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
525 break;
526 }
527 };
528
529 if (i == s->num_priority_queues) {
530 if (s->can_rx_state != 2) {
531 s->can_rx_state = 2;
532 DB_PRINT("can't receive - all the buffer descriptors are busy\n");
533 }
534 return 0;
535 }
536
537 if (s->can_rx_state != 0) {
538 s->can_rx_state = 0;
539 DB_PRINT("can receive\n");
540 }
541 return 1;
542}
543
544/*
545 * gem_update_int_status:
546 * Raise or lower interrupt based on current status.
547 */
548static void gem_update_int_status(CadenceGEMState *s)
549{
550 int i;
551
552 if (!s->regs[GEM_ISR]) {
553 /* ISR isn't set, clear all the interrupts */
554 for (i = 0; i < s->num_priority_queues; ++i) {
555 qemu_set_irq(s->irq[i], 0);
556 }
557 return;
558 }
559
560 /* If we get here we know s->regs[GEM_ISR] is set, so we don't need to
561 * check it again.
562 */
563 if (s->num_priority_queues == 1) {
564 /* No priority queues, just trigger the interrupt */
565 DB_PRINT("asserting int.\n");
566 qemu_set_irq(s->irq[0], 1);
567 return;
568 }
569
570 for (i = 0; i < s->num_priority_queues; ++i) {
571 if (s->regs[GEM_INT_Q1_STATUS + i]) {
572 DB_PRINT("asserting int. (q=%d)\n", i);
573 qemu_set_irq(s->irq[i], 1);
574 }
575 }
576}
577
578/*
579 * gem_receive_updatestats:
580 * Increment receive statistics.
581 */
582static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
583 unsigned bytes)
584{
585 uint64_t octets;
586
587 /* Total octets (bytes) received */
588 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
589 s->regs[GEM_OCTRXHI];
590 octets += bytes;
591 s->regs[GEM_OCTRXLO] = octets >> 32;
592 s->regs[GEM_OCTRXHI] = octets;
593
594 /* Error-free Frames received */
595 s->regs[GEM_RXCNT]++;
596
597 /* Error-free Broadcast Frames counter */
598 if (!memcmp(packet, broadcast_addr, 6)) {
599 s->regs[GEM_RXBROADCNT]++;
600 }
601
602 /* Error-free Multicast Frames counter */
603 if (packet[0] == 0x01) {
604 s->regs[GEM_RXMULTICNT]++;
605 }
606
607 if (bytes <= 64) {
608 s->regs[GEM_RX64CNT]++;
609 } else if (bytes <= 127) {
610 s->regs[GEM_RX65CNT]++;
611 } else if (bytes <= 255) {
612 s->regs[GEM_RX128CNT]++;
613 } else if (bytes <= 511) {
614 s->regs[GEM_RX256CNT]++;
615 } else if (bytes <= 1023) {
616 s->regs[GEM_RX512CNT]++;
617 } else if (bytes <= 1518) {
618 s->regs[GEM_RX1024CNT]++;
619 } else {
620 s->regs[GEM_RX1519CNT]++;
621 }
622}
623
624/*
625 * Get the MAC Address bit from the specified position
626 */
627static unsigned get_bit(const uint8_t *mac, unsigned bit)
628{
629 unsigned byte;
630
631 byte = mac[bit / 8];
632 byte >>= (bit & 0x7);
633 byte &= 1;
634
635 return byte;
636}
637
638/*
639 * Calculate a GEM MAC Address hash index
640 */
641static unsigned calc_mac_hash(const uint8_t *mac)
642{
643 int index_bit, mac_bit;
644 unsigned hash_index;
645
646 hash_index = 0;
647 mac_bit = 5;
648 for (index_bit = 5; index_bit >= 0; index_bit--) {
649 hash_index |= (get_bit(mac, mac_bit) ^
650 get_bit(mac, mac_bit + 6) ^
651 get_bit(mac, mac_bit + 12) ^
652 get_bit(mac, mac_bit + 18) ^
653 get_bit(mac, mac_bit + 24) ^
654 get_bit(mac, mac_bit + 30) ^
655 get_bit(mac, mac_bit + 36) ^
656 get_bit(mac, mac_bit + 42)) << index_bit;
657 mac_bit--;
658 }
659
660 return hash_index;
661}
662
663/*
664 * gem_mac_address_filter:
665 * Accept or reject this destination address?
666 * Returns:
667 * GEM_RX_REJECT: reject
668 * >= 0: Specific address accept (which matched SAR is returned)
669 * others for various other modes of accept:
670 * GEM_RM_PROMISCUOUS_ACCEPT, GEM_RX_BROADCAST_ACCEPT,
671 * GEM_RX_MULTICAST_HASH_ACCEPT or GEM_RX_UNICAST_HASH_ACCEPT
672 */
673static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
674{
675 uint8_t *gem_spaddr;
676 int i;
677
678 /* Promiscuous mode? */
679 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
680 return GEM_RX_PROMISCUOUS_ACCEPT;
681 }
682
683 if (!memcmp(packet, broadcast_addr, 6)) {
684 /* Reject broadcast packets? */
685 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
686 return GEM_RX_REJECT;
687 }
688 return GEM_RX_BROADCAST_ACCEPT;
689 }
690
691 /* Accept packets -w- hash match? */
692 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
693 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
694 unsigned hash_index;
695
696 hash_index = calc_mac_hash(packet);
697 if (hash_index < 32) {
698 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
699 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
700 GEM_RX_UNICAST_HASH_ACCEPT;
701 }
702 } else {
703 hash_index -= 32;
704 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
705 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
706 GEM_RX_UNICAST_HASH_ACCEPT;
707 }
708 }
709 }
710
711 /* Check all 4 specific addresses */
712 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
713 for (i = 3; i >= 0; i--) {
714 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
715 return GEM_RX_SAR_ACCEPT + i;
716 }
717 }
718
719 /* No address match; reject the packet */
720 return GEM_RX_REJECT;
721}
722
723/* Figure out which queue the received data should be sent to */
724static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
725 unsigned rxbufsize)
726{
727 uint32_t reg;
728 bool matched, mismatched;
729 int i, j;
730
731 for (i = 0; i < s->num_type1_screeners; i++) {
732 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
733 matched = false;
734 mismatched = false;
735
736 /* Screening is based on UDP Port */
737 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
738 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
739 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
740 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
741 matched = true;
742 } else {
743 mismatched = true;
744 }
745 }
746
747 /* Screening is based on DS/TC */
748 if (reg & GEM_ST1R_DSTC_ENABLE) {
749 uint8_t dscp = rxbuf_ptr[14 + 1];
750 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
751 GEM_ST1R_DSTC_MATCH_WIDTH)) {
752 matched = true;
753 } else {
754 mismatched = true;
755 }
756 }
757
758 if (matched && !mismatched) {
759 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
760 }
761 }
762
763 for (i = 0; i < s->num_type2_screeners; i++) {
764 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
765 matched = false;
766 mismatched = false;
767
768 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
769 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
770 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
771 GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
772
773 if (et_idx > s->num_type2_screeners) {
774 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
775 "register index: %d\n", et_idx);
776 }
777 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
778 et_idx]) {
779 matched = true;
780 } else {
781 mismatched = true;
782 }
783 }
784
785 /* Compare A, B, C */
786 for (j = 0; j < 3; j++) {
787 uint32_t cr0, cr1, mask;
788 uint16_t rx_cmp;
789 int offset;
790 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
791 GEM_ST2R_COMPARE_WIDTH);
792
793 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
794 continue;
795 }
796 if (cr_idx > s->num_type2_screeners) {
797 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
798 "register index: %d\n", cr_idx);
799 }
800
801 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
802 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
803 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
804 GEM_T2CW1_OFFSET_VALUE_WIDTH);
805
806 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
807 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
808 case 3: /* Skip UDP header */
809 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
810 "unimplemented - assuming UDP\n");
811 offset += 8;
812 /* Fallthrough */
813 case 2: /* skip the IP header */
814 offset += 20;
815 /* Fallthrough */
816 case 1: /* Count from after the ethertype */
817 offset += 14;
818 break;
819 case 0:
820 /* Offset from start of frame */
821 break;
822 }
823
824 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
825 mask = extract32(cr0, 0, 16);
826
827 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
828 matched = true;
829 } else {
830 mismatched = true;
831 }
832 }
833
834 if (matched && !mismatched) {
835 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
836 }
837 }
838
839 /* We made it here, assume it's queue 0 */
840 return 0;
841}
842
843static hwaddr gem_get_desc_addr(CadenceGEMState *s, bool tx, int q)
844{
845 hwaddr desc_addr = 0;
846
847 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) {
848 desc_addr = s->regs[tx ? GEM_TBQPH : GEM_RBQPH];
849 }
850 desc_addr <<= 32;
851 desc_addr |= tx ? s->tx_desc_addr[q] : s->rx_desc_addr[q];
852 return desc_addr;
853}
854
855static hwaddr gem_get_tx_desc_addr(CadenceGEMState *s, int q)
856{
857 return gem_get_desc_addr(s, true, q);
858}
859
860static hwaddr gem_get_rx_desc_addr(CadenceGEMState *s, int q)
861{
862 return gem_get_desc_addr(s, false, q);
863}
864
865static void gem_get_rx_desc(CadenceGEMState *s, int q)
866{
867 hwaddr desc_addr = gem_get_rx_desc_addr(s, q);
868
869 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", desc_addr);
870
871 /* read current descriptor */
872 address_space_read(&s->dma_as, desc_addr, MEMTXATTRS_UNSPECIFIED,
873 (uint8_t *)s->rx_desc[q],
874 sizeof(uint32_t) * gem_get_desc_len(s, true));
875
876 /* Descriptor owned by software ? */
877 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
878 DB_PRINT("descriptor 0x%" HWADDR_PRIx " owned by sw.\n", desc_addr);
879 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
880 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
881 /* Handle interrupt consequences */
882 gem_update_int_status(s);
883 }
884}
885
886/*
887 * gem_receive:
888 * Fit a packet handed to us by QEMU into the receive descriptor ring.
889 */
890static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
891{
892 CadenceGEMState *s;
893 unsigned rxbufsize, bytes_to_copy;
894 unsigned rxbuf_offset;
895 uint8_t rxbuf[2048];
896 uint8_t *rxbuf_ptr;
897 bool first_desc = true;
898 int maf;
899 int q = 0;
900
901 s = qemu_get_nic_opaque(nc);
902
903 /* Is this destination MAC address "for us" ? */
904 maf = gem_mac_address_filter(s, buf);
905 if (maf == GEM_RX_REJECT) {
906 return -1;
907 }
908
909 /* Discard packets with receive length error enabled ? */
910 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
911 unsigned type_len;
912
913 /* Fish the ethertype / length field out of the RX packet */
914 type_len = buf[12] << 8 | buf[13];
915 /* It is a length field, not an ethertype */
916 if (type_len < 0x600) {
917 if (size < type_len) {
918 /* discard */
919 return -1;
920 }
921 }
922 }
923
924 /*
925 * Determine configured receive buffer offset (probably 0)
926 */
927 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
928 GEM_NWCFG_BUFF_OFST_S;
929
930 /* The configure size of each receive buffer. Determines how many
931 * buffers needed to hold this packet.
932 */
933 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
934 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
935 bytes_to_copy = size;
936
937 /* Hardware allows a zero value here but warns against it. To avoid QEMU
938 * indefinite loops we enforce a minimum value here
939 */
940 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
941 rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
942 }
943
944 /* Pad to minimum length. Assume FCS field is stripped, logic
945 * below will increment it to the real minimum of 64 when
946 * not FCS stripping
947 */
948 if (size < 60) {
949 size = 60;
950 }
951
952 /* Strip of FCS field ? (usually yes) */
953 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
954 rxbuf_ptr = (void *)buf;
955 } else {
956 unsigned crc_val;
957
958 if (size > sizeof(rxbuf) - sizeof(crc_val)) {
959 size = sizeof(rxbuf) - sizeof(crc_val);
960 }
961 bytes_to_copy = size;
962 /* The application wants the FCS field, which QEMU does not provide.
963 * We must try and calculate one.
964 */
965
966 memcpy(rxbuf, buf, size);
967 memset(rxbuf + size, 0, sizeof(rxbuf) - size);
968 rxbuf_ptr = rxbuf;
969 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
970 memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
971
972 bytes_to_copy += 4;
973 size += 4;
974 }
975
976 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
977
978 /* Find which queue we are targeting */
979 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
980
981 while (bytes_to_copy) {
982 hwaddr desc_addr;
983
984 /* Do nothing if receive is not enabled. */
985 if (!gem_can_receive(nc)) {
986 return -1;
987 }
988
989 DB_PRINT("copy %d bytes to 0x%x\n", MIN(bytes_to_copy, rxbufsize),
990 rx_desc_get_buffer(s->rx_desc[q]));
991
992 /* Copy packet data to emulated DMA buffer */
993 address_space_write(&s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
994 rxbuf_offset,
995 MEMTXATTRS_UNSPECIFIED, rxbuf_ptr,
996 MIN(bytes_to_copy, rxbufsize));
997 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
998 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
999
1000 /* Update the descriptor. */
1001 if (first_desc) {
1002 rx_desc_set_sof(s->rx_desc[q]);
1003 first_desc = false;
1004 }
1005 if (bytes_to_copy == 0) {
1006 rx_desc_set_eof(s->rx_desc[q]);
1007 rx_desc_set_length(s->rx_desc[q], size);
1008 }
1009 rx_desc_set_ownership(s->rx_desc[q]);
1010
1011 switch (maf) {
1012 case GEM_RX_PROMISCUOUS_ACCEPT:
1013 break;
1014 case GEM_RX_BROADCAST_ACCEPT:
1015 rx_desc_set_broadcast(s->rx_desc[q]);
1016 break;
1017 case GEM_RX_UNICAST_HASH_ACCEPT:
1018 rx_desc_set_unicast_hash(s->rx_desc[q]);
1019 break;
1020 case GEM_RX_MULTICAST_HASH_ACCEPT:
1021 rx_desc_set_multicast_hash(s->rx_desc[q]);
1022 break;
1023 case GEM_RX_REJECT:
1024 abort();
1025 default: /* SAR */
1026 rx_desc_set_sar(s->rx_desc[q], maf);
1027 }
1028
1029 /* Descriptor write-back. */
1030 desc_addr = gem_get_rx_desc_addr(s, q);
1031 address_space_write(&s->dma_as, desc_addr,
1032 MEMTXATTRS_UNSPECIFIED,
1033 (uint8_t *)s->rx_desc[q],
1034 sizeof(uint32_t) * gem_get_desc_len(s, true));
1035
1036 /* Next descriptor */
1037 if (rx_desc_get_wrap(s->rx_desc[q])) {
1038 DB_PRINT("wrapping RX descriptor list\n");
1039 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
1040 } else {
1041 DB_PRINT("incrementing RX descriptor list\n");
1042 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
1043 }
1044
1045 gem_get_rx_desc(s, q);
1046 }
1047
1048 /* Count it */
1049 gem_receive_updatestats(s, buf, size);
1050
1051 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
1052 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
1053
1054 /* Handle interrupt consequences */
1055 gem_update_int_status(s);
1056
1057 return size;
1058}
1059
1060/*
1061 * gem_transmit_updatestats:
1062 * Increment transmit statistics.
1063 */
1064static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
1065 unsigned bytes)
1066{
1067 uint64_t octets;
1068
1069 /* Total octets (bytes) transmitted */
1070 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
1071 s->regs[GEM_OCTTXHI];
1072 octets += bytes;
1073 s->regs[GEM_OCTTXLO] = octets >> 32;
1074 s->regs[GEM_OCTTXHI] = octets;
1075
1076 /* Error-free Frames transmitted */
1077 s->regs[GEM_TXCNT]++;
1078
1079 /* Error-free Broadcast Frames counter */
1080 if (!memcmp(packet, broadcast_addr, 6)) {
1081 s->regs[GEM_TXBCNT]++;
1082 }
1083
1084 /* Error-free Multicast Frames counter */
1085 if (packet[0] == 0x01) {
1086 s->regs[GEM_TXMCNT]++;
1087 }
1088
1089 if (bytes <= 64) {
1090 s->regs[GEM_TX64CNT]++;
1091 } else if (bytes <= 127) {
1092 s->regs[GEM_TX65CNT]++;
1093 } else if (bytes <= 255) {
1094 s->regs[GEM_TX128CNT]++;
1095 } else if (bytes <= 511) {
1096 s->regs[GEM_TX256CNT]++;
1097 } else if (bytes <= 1023) {
1098 s->regs[GEM_TX512CNT]++;
1099 } else if (bytes <= 1518) {
1100 s->regs[GEM_TX1024CNT]++;
1101 } else {
1102 s->regs[GEM_TX1519CNT]++;
1103 }
1104}
1105
1106/*
1107 * gem_transmit:
1108 * Fish packets out of the descriptor ring and feed them to QEMU
1109 */
1110static void gem_transmit(CadenceGEMState *s)
1111{
1112 uint32_t desc[DESC_MAX_NUM_WORDS];
1113 hwaddr packet_desc_addr;
1114 uint8_t tx_packet[2048];
1115 uint8_t *p;
1116 unsigned total_bytes;
1117 int q = 0;
1118
1119 /* Do nothing if transmit is not enabled. */
1120 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1121 return;
1122 }
1123
1124 DB_PRINT("\n");
1125
1126 /* The packet we will hand off to QEMU.
1127 * Packets scattered across multiple descriptors are gathered to this
1128 * one contiguous buffer first.
1129 */
1130 p = tx_packet;
1131 total_bytes = 0;
1132
1133 for (q = s->num_priority_queues - 1; q >= 0; q--) {
1134 /* read current descriptor */
1135 packet_desc_addr = gem_get_tx_desc_addr(s, q);
1136
1137 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1138 address_space_read(&s->dma_as, packet_desc_addr,
1139 MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
1140 sizeof(uint32_t) * gem_get_desc_len(s, false));
1141 /* Handle all descriptors owned by hardware */
1142 while (tx_desc_get_used(desc) == 0) {
1143
1144 /* Do nothing if transmit is not enabled. */
1145 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1146 return;
1147 }
1148 print_gem_tx_desc(desc, q);
1149
1150 /* The real hardware would eat this (and possibly crash).
1151 * For QEMU let's lend a helping hand.
1152 */
1153 if ((tx_desc_get_buffer(s, desc) == 0) ||
1154 (tx_desc_get_length(desc) == 0)) {
1155 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1156 (unsigned)packet_desc_addr);
1157 break;
1158 }
1159
1160 if (tx_desc_get_length(desc) > sizeof(tx_packet) -
1161 (p - tx_packet)) {
1162 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
1163 "0x%x\n", (unsigned)packet_desc_addr,
1164 (unsigned)tx_desc_get_length(desc),
1165 sizeof(tx_packet) - (p - tx_packet));
1166 break;
1167 }
1168
1169 /* Gather this fragment of the packet from "dma memory" to our
1170 * contig buffer.
1171 */
1172 address_space_read(&s->dma_as, tx_desc_get_buffer(s, desc),
1173 MEMTXATTRS_UNSPECIFIED,
1174 p, tx_desc_get_length(desc));
1175 p += tx_desc_get_length(desc);
1176 total_bytes += tx_desc_get_length(desc);
1177
1178 /* Last descriptor for this packet; hand the whole thing off */
1179 if (tx_desc_get_last(desc)) {
1180 uint32_t desc_first[DESC_MAX_NUM_WORDS];
1181 hwaddr desc_addr = gem_get_tx_desc_addr(s, q);
1182
1183 /* Modify the 1st descriptor of this packet to be owned by
1184 * the processor.
1185 */
1186 address_space_read(&s->dma_as, desc_addr,
1187 MEMTXATTRS_UNSPECIFIED,
1188 (uint8_t *)desc_first,
1189 sizeof(desc_first));
1190 tx_desc_set_used(desc_first);
1191 address_space_write(&s->dma_as, desc_addr,
1192 MEMTXATTRS_UNSPECIFIED,
1193 (uint8_t *)desc_first,
1194 sizeof(desc_first));
1195 /* Advance the hardware current descriptor past this packet */
1196 if (tx_desc_get_wrap(desc)) {
1197 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
1198 } else {
1199 s->tx_desc_addr[q] = packet_desc_addr +
1200 4 * gem_get_desc_len(s, false);
1201 }
1202 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
1203
1204 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1205 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
1206
1207 /* Update queue interrupt status */
1208 if (s->num_priority_queues > 1) {
1209 s->regs[GEM_INT_Q1_STATUS + q] |=
1210 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
1211 }
1212
1213 /* Handle interrupt consequences */
1214 gem_update_int_status(s);
1215
1216 /* Is checksum offload enabled? */
1217 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1218 net_checksum_calculate(tx_packet, total_bytes);
1219 }
1220
1221 /* Update MAC statistics */
1222 gem_transmit_updatestats(s, tx_packet, total_bytes);
1223
1224 /* Send the packet somewhere */
1225 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1226 GEM_NWCTRL_LOCALLOOP)) {
1227 gem_receive(qemu_get_queue(s->nic), tx_packet,
1228 total_bytes);
1229 } else {
1230 qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
1231 total_bytes);
1232 }
1233
1234 /* Prepare for next packet */
1235 p = tx_packet;
1236 total_bytes = 0;
1237 }
1238
1239 /* read next descriptor */
1240 if (tx_desc_get_wrap(desc)) {
1241 tx_desc_set_last(desc);
1242 packet_desc_addr = s->regs[GEM_TXQBASE];
1243 } else {
1244 packet_desc_addr += 4 * gem_get_desc_len(s, false);
1245 }
1246 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1247 address_space_read(&s->dma_as, packet_desc_addr,
1248 MEMTXATTRS_UNSPECIFIED, (uint8_t *)desc,
1249 sizeof(uint32_t) * gem_get_desc_len(s, false));
1250 }
1251
1252 if (tx_desc_get_used(desc)) {
1253 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1254 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
1255 gem_update_int_status(s);
1256 }
1257 }
1258}
1259
1260static void gem_phy_reset(CadenceGEMState *s)
1261{
1262 memset(&s->phy_regs[0], 0, sizeof(s->phy_regs));
1263 s->phy_regs[PHY_REG_CONTROL] = 0x1140;
1264 s->phy_regs[PHY_REG_STATUS] = 0x7969;
1265 s->phy_regs[PHY_REG_PHYID1] = 0x0141;
1266 s->phy_regs[PHY_REG_PHYID2] = 0x0CC2;
1267 s->phy_regs[PHY_REG_ANEGADV] = 0x01E1;
1268 s->phy_regs[PHY_REG_LINKPABIL] = 0xCDE1;
1269 s->phy_regs[PHY_REG_ANEGEXP] = 0x000F;
1270 s->phy_regs[PHY_REG_NEXTP] = 0x2001;
1271 s->phy_regs[PHY_REG_LINKPNEXTP] = 0x40E6;
1272 s->phy_regs[PHY_REG_100BTCTRL] = 0x0300;
1273 s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00;
1274 s->phy_regs[PHY_REG_EXTSTAT] = 0x3000;
1275 s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078;
1276 s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00;
1277 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60;
1278 s->phy_regs[PHY_REG_LED] = 0x4100;
1279 s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A;
1280 s->phy_regs[PHY_REG_EXT_PHYSPCFC_ST] = 0x848B;
1281
1282 phy_update_link(s);
1283}
1284
1285static void gem_reset(DeviceState *d)
1286{
1287 int i;
1288 CadenceGEMState *s = CADENCE_GEM(d);
1289 const uint8_t *a;
1290 uint32_t queues_mask = 0;
1291
1292 DB_PRINT("\n");
1293
1294 /* Set post reset register values */
1295 memset(&s->regs[0], 0, sizeof(s->regs));
1296 s->regs[GEM_NWCFG] = 0x00080000;
1297 s->regs[GEM_NWSTATUS] = 0x00000006;
1298 s->regs[GEM_DMACFG] = 0x00020784;
1299 s->regs[GEM_IMR] = 0x07ffffff;
1300 s->regs[GEM_TXPAUSE] = 0x0000ffff;
1301 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1302 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1303 s->regs[GEM_MODID] = s->revision;
1304 s->regs[GEM_DESCONF] = 0x02500111;
1305 s->regs[GEM_DESCONF2] = 0x2ab13fff;
1306 s->regs[GEM_DESCONF5] = 0x002f2045;
1307 s->regs[GEM_DESCONF6] = GEM_DESCONF6_64B_MASK;
1308
1309 if (s->num_priority_queues > 1) {
1310 queues_mask = MAKE_64BIT_MASK(1, s->num_priority_queues - 1);
1311 s->regs[GEM_DESCONF6] |= queues_mask;
1312 }
1313
1314 /* Set MAC address */
1315 a = &s->conf.macaddr.a[0];
1316 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1317 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1318
1319 for (i = 0; i < 4; i++) {
1320 s->sar_active[i] = false;
1321 }
1322
1323 gem_phy_reset(s);
1324
1325 gem_update_int_status(s);
1326}
1327
1328static uint16_t gem_phy_read(CadenceGEMState *s, unsigned reg_num)
1329{
1330 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, s->phy_regs[reg_num]);
1331 return s->phy_regs[reg_num];
1332}
1333
1334static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
1335{
1336 DB_PRINT("reg: %d value: 0x%04x\n", reg_num, val);
1337
1338 switch (reg_num) {
1339 case PHY_REG_CONTROL:
1340 if (val & PHY_REG_CONTROL_RST) {
1341 /* Phy reset */
1342 gem_phy_reset(s);
1343 val &= ~(PHY_REG_CONTROL_RST | PHY_REG_CONTROL_LOOP);
1344 s->phy_loop = 0;
1345 }
1346 if (val & PHY_REG_CONTROL_ANEG) {
1347 /* Complete autonegotiation immediately */
1348 val &= ~PHY_REG_CONTROL_ANEG;
1349 s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
1350 }
1351 if (val & PHY_REG_CONTROL_LOOP) {
1352 DB_PRINT("PHY placed in loopback\n");
1353 s->phy_loop = 1;
1354 } else {
1355 s->phy_loop = 0;
1356 }
1357 break;
1358 }
1359 s->phy_regs[reg_num] = val;
1360}
1361
1362/*
1363 * gem_read32:
1364 * Read a GEM register.
1365 */
1366static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1367{
1368 CadenceGEMState *s;
1369 uint32_t retval;
1370 s = (CadenceGEMState *)opaque;
1371
1372 offset >>= 2;
1373 retval = s->regs[offset];
1374
1375 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1376
1377 switch (offset) {
1378 case GEM_ISR:
1379 DB_PRINT("lowering irqs on ISR read\n");
1380 /* The interrupts get updated at the end of the function. */
1381 break;
1382 case GEM_PHYMNTNC:
1383 if (retval & GEM_PHYMNTNC_OP_R) {
1384 uint32_t phy_addr, reg_num;
1385
1386 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1387 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1388 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1389 retval &= 0xFFFF0000;
1390 retval |= gem_phy_read(s, reg_num);
1391 } else {
1392 retval |= 0xFFFF; /* No device at this address */
1393 }
1394 }
1395 break;
1396 }
1397
1398 /* Squash read to clear bits */
1399 s->regs[offset] &= ~(s->regs_rtc[offset]);
1400
1401 /* Do not provide write only bits */
1402 retval &= ~(s->regs_wo[offset]);
1403
1404 DB_PRINT("0x%08x\n", retval);
1405 gem_update_int_status(s);
1406 return retval;
1407}
1408
1409/*
1410 * gem_write32:
1411 * Write a GEM register.
1412 */
1413static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1414 unsigned size)
1415{
1416 CadenceGEMState *s = (CadenceGEMState *)opaque;
1417 uint32_t readonly;
1418 int i;
1419
1420 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1421 offset >>= 2;
1422
1423 /* Squash bits which are read only in write value */
1424 val &= ~(s->regs_ro[offset]);
1425 /* Preserve (only) bits which are read only and wtc in register */
1426 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1427
1428 /* Copy register write to backing store */
1429 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1430
1431 /* do w1c */
1432 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1433
1434 /* Handle register write side effects */
1435 switch (offset) {
1436 case GEM_NWCTRL:
1437 if (val & GEM_NWCTRL_RXENA) {
1438 for (i = 0; i < s->num_priority_queues; ++i) {
1439 gem_get_rx_desc(s, i);
1440 }
1441 }
1442 if (val & GEM_NWCTRL_TXSTART) {
1443 gem_transmit(s);
1444 }
1445 if (!(val & GEM_NWCTRL_TXENA)) {
1446 /* Reset to start of Q when transmit disabled. */
1447 for (i = 0; i < s->num_priority_queues; i++) {
1448 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
1449 }
1450 }
1451 if (gem_can_receive(qemu_get_queue(s->nic))) {
1452 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1453 }
1454 break;
1455
1456 case GEM_TXSTATUS:
1457 gem_update_int_status(s);
1458 break;
1459 case GEM_RXQBASE:
1460 s->rx_desc_addr[0] = val;
1461 break;
1462 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
1463 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1464 break;
1465 case GEM_TXQBASE:
1466 s->tx_desc_addr[0] = val;
1467 break;
1468 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
1469 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1470 break;
1471 case GEM_RXSTATUS:
1472 gem_update_int_status(s);
1473 break;
1474 case GEM_IER:
1475 s->regs[GEM_IMR] &= ~val;
1476 gem_update_int_status(s);
1477 break;
1478 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1479 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1480 gem_update_int_status(s);
1481 break;
1482 case GEM_IDR:
1483 s->regs[GEM_IMR] |= val;
1484 gem_update_int_status(s);
1485 break;
1486 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1487 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1488 gem_update_int_status(s);
1489 break;
1490 case GEM_SPADDR1LO:
1491 case GEM_SPADDR2LO:
1492 case GEM_SPADDR3LO:
1493 case GEM_SPADDR4LO:
1494 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1495 break;
1496 case GEM_SPADDR1HI:
1497 case GEM_SPADDR2HI:
1498 case GEM_SPADDR3HI:
1499 case GEM_SPADDR4HI:
1500 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1501 break;
1502 case GEM_PHYMNTNC:
1503 if (val & GEM_PHYMNTNC_OP_W) {
1504 uint32_t phy_addr, reg_num;
1505
1506 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1507 if (phy_addr == BOARD_PHY_ADDRESS || phy_addr == 0) {
1508 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1509 gem_phy_write(s, reg_num, val);
1510 }
1511 }
1512 break;
1513 }
1514
1515 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1516}
1517
1518static const MemoryRegionOps gem_ops = {
1519 .read = gem_read,
1520 .write = gem_write,
1521 .endianness = DEVICE_LITTLE_ENDIAN,
1522};
1523
1524static void gem_set_link(NetClientState *nc)
1525{
1526 CadenceGEMState *s = qemu_get_nic_opaque(nc);
1527
1528 DB_PRINT("\n");
1529 phy_update_link(s);
1530 gem_update_int_status(s);
1531}
1532
1533static NetClientInfo net_gem_info = {
1534 .type = NET_CLIENT_DRIVER_NIC,
1535 .size = sizeof(NICState),
1536 .can_receive = gem_can_receive,
1537 .receive = gem_receive,
1538 .link_status_changed = gem_set_link,
1539};
1540
1541static void gem_realize(DeviceState *dev, Error **errp)
1542{
1543 CadenceGEMState *s = CADENCE_GEM(dev);
1544 int i;
1545
1546 address_space_init(&s->dma_as,
1547 s->dma_mr ? s->dma_mr : get_system_memory(), "dma");
1548
1549 if (s->num_priority_queues == 0 ||
1550 s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1551 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1552 s->num_priority_queues);
1553 return;
1554 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1555 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
1556 s->num_type1_screeners);
1557 return;
1558 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1559 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
1560 s->num_type2_screeners);
1561 return;
1562 }
1563
1564 for (i = 0; i < s->num_priority_queues; ++i) {
1565 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1566 }
1567
1568 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1569
1570 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1571 object_get_typename(OBJECT(dev)), dev->id, s);
1572}
1573
1574static void gem_init(Object *obj)
1575{
1576 CadenceGEMState *s = CADENCE_GEM(obj);
1577 DeviceState *dev = DEVICE(obj);
1578
1579 DB_PRINT("\n");
1580
1581 gem_init_register_masks(s);
1582 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1583 "enet", sizeof(s->regs));
1584
1585 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1586
1587 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1588 (Object **)&s->dma_mr,
1589 qdev_prop_allow_set_link_before_realize,
1590 OBJ_PROP_LINK_STRONG,
1591 &error_abort);
1592}
1593
1594static const VMStateDescription vmstate_cadence_gem = {
1595 .name = "cadence_gem",
1596 .version_id = 4,
1597 .minimum_version_id = 4,
1598 .fields = (VMStateField[]) {
1599 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1600 VMSTATE_UINT16_ARRAY(phy_regs, CadenceGEMState, 32),
1601 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1602 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1603 MAX_PRIORITY_QUEUES),
1604 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1605 MAX_PRIORITY_QUEUES),
1606 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1607 VMSTATE_END_OF_LIST(),
1608 }
1609};
1610
1611static Property gem_properties[] = {
1612 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1613 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1614 GEM_MODID_VALUE),
1615 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1616 num_priority_queues, 1),
1617 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1618 num_type1_screeners, 4),
1619 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1620 num_type2_screeners, 4),
1621 DEFINE_PROP_END_OF_LIST(),
1622};
1623
1624static void gem_class_init(ObjectClass *klass, void *data)
1625{
1626 DeviceClass *dc = DEVICE_CLASS(klass);
1627
1628 dc->realize = gem_realize;
1629 dc->props = gem_properties;
1630 dc->vmsd = &vmstate_cadence_gem;
1631 dc->reset = gem_reset;
1632}
1633
1634static const TypeInfo gem_info = {
1635 .name = TYPE_CADENCE_GEM,
1636 .parent = TYPE_SYS_BUS_DEVICE,
1637 .instance_size = sizeof(CadenceGEMState),
1638 .instance_init = gem_init,
1639 .class_init = gem_class_init,
1640};
1641
1642static void gem_register_types(void)
1643{
1644 type_register_static(&gem_info);
1645}
1646
1647type_init(gem_register_types)
1648