1/*
2 * SMSC LAN9118 Ethernet interface emulation
3 *
4 * Copyright (c) 2009 CodeSourcery, LLC.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GNU GPL v2
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13#include "qemu/osdep.h"
14#include "hw/sysbus.h"
15#include "migration/vmstate.h"
16#include "net/net.h"
17#include "net/eth.h"
18#include "hw/hw.h"
19#include "hw/irq.h"
20#include "hw/net/lan9118.h"
21#include "hw/ptimer.h"
22#include "hw/qdev-properties.h"
23#include "qemu/log.h"
24#include "qemu/main-loop.h"
25#include "qemu/module.h"
26/* For crc32 */
27#include <zlib.h>
28
29//#define DEBUG_LAN9118
30
31#ifdef DEBUG_LAN9118
32#define DPRINTF(fmt, ...) \
33do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
34#define BADF(fmt, ...) \
35do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
36#else
37#define DPRINTF(fmt, ...) do {} while(0)
38#define BADF(fmt, ...) \
39do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
40#endif
41
42#define CSR_ID_REV 0x50
43#define CSR_IRQ_CFG 0x54
44#define CSR_INT_STS 0x58
45#define CSR_INT_EN 0x5c
46#define CSR_BYTE_TEST 0x64
47#define CSR_FIFO_INT 0x68
48#define CSR_RX_CFG 0x6c
49#define CSR_TX_CFG 0x70
50#define CSR_HW_CFG 0x74
51#define CSR_RX_DP_CTRL 0x78
52#define CSR_RX_FIFO_INF 0x7c
53#define CSR_TX_FIFO_INF 0x80
54#define CSR_PMT_CTRL 0x84
55#define CSR_GPIO_CFG 0x88
56#define CSR_GPT_CFG 0x8c
57#define CSR_GPT_CNT 0x90
58#define CSR_WORD_SWAP 0x98
59#define CSR_FREE_RUN 0x9c
60#define CSR_RX_DROP 0xa0
61#define CSR_MAC_CSR_CMD 0xa4
62#define CSR_MAC_CSR_DATA 0xa8
63#define CSR_AFC_CFG 0xac
64#define CSR_E2P_CMD 0xb0
65#define CSR_E2P_DATA 0xb4
66
67#define E2P_CMD_MAC_ADDR_LOADED 0x100
68
69/* IRQ_CFG */
70#define IRQ_INT 0x00001000
71#define IRQ_EN 0x00000100
72#define IRQ_POL 0x00000010
73#define IRQ_TYPE 0x00000001
74
75/* INT_STS/INT_EN */
76#define SW_INT 0x80000000
77#define TXSTOP_INT 0x02000000
78#define RXSTOP_INT 0x01000000
79#define RXDFH_INT 0x00800000
80#define TX_IOC_INT 0x00200000
81#define RXD_INT 0x00100000
82#define GPT_INT 0x00080000
83#define PHY_INT 0x00040000
84#define PME_INT 0x00020000
85#define TXSO_INT 0x00010000
86#define RWT_INT 0x00008000
87#define RXE_INT 0x00004000
88#define TXE_INT 0x00002000
89#define TDFU_INT 0x00000800
90#define TDFO_INT 0x00000400
91#define TDFA_INT 0x00000200
92#define TSFF_INT 0x00000100
93#define TSFL_INT 0x00000080
94#define RXDF_INT 0x00000040
95#define RDFL_INT 0x00000020
96#define RSFF_INT 0x00000010
97#define RSFL_INT 0x00000008
98#define GPIO2_INT 0x00000004
99#define GPIO1_INT 0x00000002
100#define GPIO0_INT 0x00000001
101#define RESERVED_INT 0x7c001000
102
103#define MAC_CR 1
104#define MAC_ADDRH 2
105#define MAC_ADDRL 3
106#define MAC_HASHH 4
107#define MAC_HASHL 5
108#define MAC_MII_ACC 6
109#define MAC_MII_DATA 7
110#define MAC_FLOW 8
111#define MAC_VLAN1 9 /* TODO */
112#define MAC_VLAN2 10 /* TODO */
113#define MAC_WUFF 11 /* TODO */
114#define MAC_WUCSR 12 /* TODO */
115
116#define MAC_CR_RXALL 0x80000000
117#define MAC_CR_RCVOWN 0x00800000
118#define MAC_CR_LOOPBK 0x00200000
119#define MAC_CR_FDPX 0x00100000
120#define MAC_CR_MCPAS 0x00080000
121#define MAC_CR_PRMS 0x00040000
122#define MAC_CR_INVFILT 0x00020000
123#define MAC_CR_PASSBAD 0x00010000
124#define MAC_CR_HO 0x00008000
125#define MAC_CR_HPFILT 0x00002000
126#define MAC_CR_LCOLL 0x00001000
127#define MAC_CR_BCAST 0x00000800
128#define MAC_CR_DISRTY 0x00000400
129#define MAC_CR_PADSTR 0x00000100
130#define MAC_CR_BOLMT 0x000000c0
131#define MAC_CR_DFCHK 0x00000020
132#define MAC_CR_TXEN 0x00000008
133#define MAC_CR_RXEN 0x00000004
134#define MAC_CR_RESERVED 0x7f404213
135
136#define PHY_INT_ENERGYON 0x80
137#define PHY_INT_AUTONEG_COMPLETE 0x40
138#define PHY_INT_FAULT 0x20
139#define PHY_INT_DOWN 0x10
140#define PHY_INT_AUTONEG_LP 0x08
141#define PHY_INT_PARFAULT 0x04
142#define PHY_INT_AUTONEG_PAGE 0x02
143
144#define GPT_TIMER_EN 0x20000000
145
146enum tx_state {
147 TX_IDLE,
148 TX_B,
149 TX_DATA
150};
151
152typedef struct {
153 /* state is a tx_state but we can't put enums in VMStateDescriptions. */
154 uint32_t state;
155 uint32_t cmd_a;
156 uint32_t cmd_b;
157 int32_t buffer_size;
158 int32_t offset;
159 int32_t pad;
160 int32_t fifo_used;
161 int32_t len;
162 uint8_t data[2048];
163} LAN9118Packet;
164
165static const VMStateDescription vmstate_lan9118_packet = {
166 .name = "lan9118_packet",
167 .version_id = 1,
168 .minimum_version_id = 1,
169 .fields = (VMStateField[]) {
170 VMSTATE_UINT32(state, LAN9118Packet),
171 VMSTATE_UINT32(cmd_a, LAN9118Packet),
172 VMSTATE_UINT32(cmd_b, LAN9118Packet),
173 VMSTATE_INT32(buffer_size, LAN9118Packet),
174 VMSTATE_INT32(offset, LAN9118Packet),
175 VMSTATE_INT32(pad, LAN9118Packet),
176 VMSTATE_INT32(fifo_used, LAN9118Packet),
177 VMSTATE_INT32(len, LAN9118Packet),
178 VMSTATE_UINT8_ARRAY(data, LAN9118Packet, 2048),
179 VMSTATE_END_OF_LIST()
180 }
181};
182
183#define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118)
184
185typedef struct {
186 SysBusDevice parent_obj;
187
188 NICState *nic;
189 NICConf conf;
190 qemu_irq irq;
191 MemoryRegion mmio;
192 ptimer_state *timer;
193
194 uint32_t irq_cfg;
195 uint32_t int_sts;
196 uint32_t int_en;
197 uint32_t fifo_int;
198 uint32_t rx_cfg;
199 uint32_t tx_cfg;
200 uint32_t hw_cfg;
201 uint32_t pmt_ctrl;
202 uint32_t gpio_cfg;
203 uint32_t gpt_cfg;
204 uint32_t word_swap;
205 uint32_t free_timer_start;
206 uint32_t mac_cmd;
207 uint32_t mac_data;
208 uint32_t afc_cfg;
209 uint32_t e2p_cmd;
210 uint32_t e2p_data;
211
212 uint32_t mac_cr;
213 uint32_t mac_hashh;
214 uint32_t mac_hashl;
215 uint32_t mac_mii_acc;
216 uint32_t mac_mii_data;
217 uint32_t mac_flow;
218
219 uint32_t phy_status;
220 uint32_t phy_control;
221 uint32_t phy_advertise;
222 uint32_t phy_int;
223 uint32_t phy_int_mask;
224
225 int32_t eeprom_writable;
226 uint8_t eeprom[128];
227
228 int32_t tx_fifo_size;
229 LAN9118Packet *txp;
230 LAN9118Packet tx_packet;
231
232 int32_t tx_status_fifo_used;
233 int32_t tx_status_fifo_head;
234 uint32_t tx_status_fifo[512];
235
236 int32_t rx_status_fifo_size;
237 int32_t rx_status_fifo_used;
238 int32_t rx_status_fifo_head;
239 uint32_t rx_status_fifo[896];
240 int32_t rx_fifo_size;
241 int32_t rx_fifo_used;
242 int32_t rx_fifo_head;
243 uint32_t rx_fifo[3360];
244 int32_t rx_packet_size_head;
245 int32_t rx_packet_size_tail;
246 int32_t rx_packet_size[1024];
247
248 int32_t rxp_offset;
249 int32_t rxp_size;
250 int32_t rxp_pad;
251
252 uint32_t write_word_prev_offset;
253 uint32_t write_word_n;
254 uint16_t write_word_l;
255 uint16_t write_word_h;
256 uint32_t read_word_prev_offset;
257 uint32_t read_word_n;
258 uint32_t read_long;
259
260 uint32_t mode_16bit;
261} lan9118_state;
262
263static const VMStateDescription vmstate_lan9118 = {
264 .name = "lan9118",
265 .version_id = 2,
266 .minimum_version_id = 1,
267 .fields = (VMStateField[]) {
268 VMSTATE_PTIMER(timer, lan9118_state),
269 VMSTATE_UINT32(irq_cfg, lan9118_state),
270 VMSTATE_UINT32(int_sts, lan9118_state),
271 VMSTATE_UINT32(int_en, lan9118_state),
272 VMSTATE_UINT32(fifo_int, lan9118_state),
273 VMSTATE_UINT32(rx_cfg, lan9118_state),
274 VMSTATE_UINT32(tx_cfg, lan9118_state),
275 VMSTATE_UINT32(hw_cfg, lan9118_state),
276 VMSTATE_UINT32(pmt_ctrl, lan9118_state),
277 VMSTATE_UINT32(gpio_cfg, lan9118_state),
278 VMSTATE_UINT32(gpt_cfg, lan9118_state),
279 VMSTATE_UINT32(word_swap, lan9118_state),
280 VMSTATE_UINT32(free_timer_start, lan9118_state),
281 VMSTATE_UINT32(mac_cmd, lan9118_state),
282 VMSTATE_UINT32(mac_data, lan9118_state),
283 VMSTATE_UINT32(afc_cfg, lan9118_state),
284 VMSTATE_UINT32(e2p_cmd, lan9118_state),
285 VMSTATE_UINT32(e2p_data, lan9118_state),
286 VMSTATE_UINT32(mac_cr, lan9118_state),
287 VMSTATE_UINT32(mac_hashh, lan9118_state),
288 VMSTATE_UINT32(mac_hashl, lan9118_state),
289 VMSTATE_UINT32(mac_mii_acc, lan9118_state),
290 VMSTATE_UINT32(mac_mii_data, lan9118_state),
291 VMSTATE_UINT32(mac_flow, lan9118_state),
292 VMSTATE_UINT32(phy_status, lan9118_state),
293 VMSTATE_UINT32(phy_control, lan9118_state),
294 VMSTATE_UINT32(phy_advertise, lan9118_state),
295 VMSTATE_UINT32(phy_int, lan9118_state),
296 VMSTATE_UINT32(phy_int_mask, lan9118_state),
297 VMSTATE_INT32(eeprom_writable, lan9118_state),
298 VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
299 VMSTATE_INT32(tx_fifo_size, lan9118_state),
300 /* txp always points at tx_packet so need not be saved */
301 VMSTATE_STRUCT(tx_packet, lan9118_state, 0,
302 vmstate_lan9118_packet, LAN9118Packet),
303 VMSTATE_INT32(tx_status_fifo_used, lan9118_state),
304 VMSTATE_INT32(tx_status_fifo_head, lan9118_state),
305 VMSTATE_UINT32_ARRAY(tx_status_fifo, lan9118_state, 512),
306 VMSTATE_INT32(rx_status_fifo_size, lan9118_state),
307 VMSTATE_INT32(rx_status_fifo_used, lan9118_state),
308 VMSTATE_INT32(rx_status_fifo_head, lan9118_state),
309 VMSTATE_UINT32_ARRAY(rx_status_fifo, lan9118_state, 896),
310 VMSTATE_INT32(rx_fifo_size, lan9118_state),
311 VMSTATE_INT32(rx_fifo_used, lan9118_state),
312 VMSTATE_INT32(rx_fifo_head, lan9118_state),
313 VMSTATE_UINT32_ARRAY(rx_fifo, lan9118_state, 3360),
314 VMSTATE_INT32(rx_packet_size_head, lan9118_state),
315 VMSTATE_INT32(rx_packet_size_tail, lan9118_state),
316 VMSTATE_INT32_ARRAY(rx_packet_size, lan9118_state, 1024),
317 VMSTATE_INT32(rxp_offset, lan9118_state),
318 VMSTATE_INT32(rxp_size, lan9118_state),
319 VMSTATE_INT32(rxp_pad, lan9118_state),
320 VMSTATE_UINT32_V(write_word_prev_offset, lan9118_state, 2),
321 VMSTATE_UINT32_V(write_word_n, lan9118_state, 2),
322 VMSTATE_UINT16_V(write_word_l, lan9118_state, 2),
323 VMSTATE_UINT16_V(write_word_h, lan9118_state, 2),
324 VMSTATE_UINT32_V(read_word_prev_offset, lan9118_state, 2),
325 VMSTATE_UINT32_V(read_word_n, lan9118_state, 2),
326 VMSTATE_UINT32_V(read_long, lan9118_state, 2),
327 VMSTATE_UINT32_V(mode_16bit, lan9118_state, 2),
328 VMSTATE_END_OF_LIST()
329 }
330};
331
332static void lan9118_update(lan9118_state *s)
333{
334 int level;
335
336 /* TODO: Implement FIFO level IRQs. */
337 level = (s->int_sts & s->int_en) != 0;
338 if (level) {
339 s->irq_cfg |= IRQ_INT;
340 } else {
341 s->irq_cfg &= ~IRQ_INT;
342 }
343 if ((s->irq_cfg & IRQ_EN) == 0) {
344 level = 0;
345 }
346 if ((s->irq_cfg & (IRQ_TYPE | IRQ_POL)) != (IRQ_TYPE | IRQ_POL)) {
347 /* Interrupt is active low unless we're configured as
348 * active-high polarity, push-pull type.
349 */
350 level = !level;
351 }
352 qemu_set_irq(s->irq, level);
353}
354
355static void lan9118_mac_changed(lan9118_state *s)
356{
357 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
358}
359
360static void lan9118_reload_eeprom(lan9118_state *s)
361{
362 int i;
363 if (s->eeprom[0] != 0xa5) {
364 s->e2p_cmd &= ~E2P_CMD_MAC_ADDR_LOADED;
365 DPRINTF("MACADDR load failed\n");
366 return;
367 }
368 for (i = 0; i < 6; i++) {
369 s->conf.macaddr.a[i] = s->eeprom[i + 1];
370 }
371 s->e2p_cmd |= E2P_CMD_MAC_ADDR_LOADED;
372 DPRINTF("MACADDR loaded from eeprom\n");
373 lan9118_mac_changed(s);
374}
375
376static void phy_update_irq(lan9118_state *s)
377{
378 if (s->phy_int & s->phy_int_mask) {
379 s->int_sts |= PHY_INT;
380 } else {
381 s->int_sts &= ~PHY_INT;
382 }
383 lan9118_update(s);
384}
385
386static void phy_update_link(lan9118_state *s)
387{
388 /* Autonegotiation status mirrors link status. */
389 if (qemu_get_queue(s->nic)->link_down) {
390 s->phy_status &= ~0x0024;
391 s->phy_int |= PHY_INT_DOWN;
392 } else {
393 s->phy_status |= 0x0024;
394 s->phy_int |= PHY_INT_ENERGYON;
395 s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
396 }
397 phy_update_irq(s);
398}
399
400static void lan9118_set_link(NetClientState *nc)
401{
402 phy_update_link(qemu_get_nic_opaque(nc));
403}
404
405static void phy_reset(lan9118_state *s)
406{
407 s->phy_status = 0x7809;
408 s->phy_control = 0x3000;
409 s->phy_advertise = 0x01e1;
410 s->phy_int_mask = 0;
411 s->phy_int = 0;
412 phy_update_link(s);
413}
414
415static void lan9118_reset(DeviceState *d)
416{
417 lan9118_state *s = LAN9118(d);
418
419 s->irq_cfg &= (IRQ_TYPE | IRQ_POL);
420 s->int_sts = 0;
421 s->int_en = 0;
422 s->fifo_int = 0x48000000;
423 s->rx_cfg = 0;
424 s->tx_cfg = 0;
425 s->hw_cfg = s->mode_16bit ? 0x00050000 : 0x00050004;
426 s->pmt_ctrl &= 0x45;
427 s->gpio_cfg = 0;
428 s->txp->fifo_used = 0;
429 s->txp->state = TX_IDLE;
430 s->txp->cmd_a = 0xffffffffu;
431 s->txp->cmd_b = 0xffffffffu;
432 s->txp->len = 0;
433 s->txp->fifo_used = 0;
434 s->tx_fifo_size = 4608;
435 s->tx_status_fifo_used = 0;
436 s->rx_status_fifo_size = 704;
437 s->rx_fifo_size = 2640;
438 s->rx_fifo_used = 0;
439 s->rx_status_fifo_size = 176;
440 s->rx_status_fifo_used = 0;
441 s->rxp_offset = 0;
442 s->rxp_size = 0;
443 s->rxp_pad = 0;
444 s->rx_packet_size_tail = s->rx_packet_size_head;
445 s->rx_packet_size[s->rx_packet_size_head] = 0;
446 s->mac_cmd = 0;
447 s->mac_data = 0;
448 s->afc_cfg = 0;
449 s->e2p_cmd = 0;
450 s->e2p_data = 0;
451 s->free_timer_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40;
452
453 ptimer_stop(s->timer);
454 ptimer_set_count(s->timer, 0xffff);
455 s->gpt_cfg = 0xffff;
456
457 s->mac_cr = MAC_CR_PRMS;
458 s->mac_hashh = 0;
459 s->mac_hashl = 0;
460 s->mac_mii_acc = 0;
461 s->mac_mii_data = 0;
462 s->mac_flow = 0;
463
464 s->read_word_n = 0;
465 s->write_word_n = 0;
466
467 phy_reset(s);
468
469 s->eeprom_writable = 0;
470 lan9118_reload_eeprom(s);
471}
472
473static void rx_fifo_push(lan9118_state *s, uint32_t val)
474{
475 int fifo_pos;
476 fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
477 if (fifo_pos >= s->rx_fifo_size)
478 fifo_pos -= s->rx_fifo_size;
479 s->rx_fifo[fifo_pos] = val;
480 s->rx_fifo_used++;
481}
482
483/* Return nonzero if the packet is accepted by the filter. */
484static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
485{
486 int multicast;
487 uint32_t hash;
488
489 if (s->mac_cr & MAC_CR_PRMS) {
490 return 1;
491 }
492 if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
493 addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
494 return (s->mac_cr & MAC_CR_BCAST) == 0;
495 }
496
497 multicast = addr[0] & 1;
498 if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
499 return 1;
500 }
501 if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
502 : (s->mac_cr & MAC_CR_HO) == 0) {
503 /* Exact matching. */
504 hash = memcmp(addr, s->conf.macaddr.a, 6);
505 if (s->mac_cr & MAC_CR_INVFILT) {
506 return hash != 0;
507 } else {
508 return hash == 0;
509 }
510 } else {
511 /* Hash matching */
512 hash = net_crc32(addr, ETH_ALEN) >> 26;
513 if (hash & 0x20) {
514 return (s->mac_hashh >> (hash & 0x1f)) & 1;
515 } else {
516 return (s->mac_hashl >> (hash & 0x1f)) & 1;
517 }
518 }
519}
520
521static ssize_t lan9118_receive(NetClientState *nc, const uint8_t *buf,
522 size_t size)
523{
524 lan9118_state *s = qemu_get_nic_opaque(nc);
525 int fifo_len;
526 int offset;
527 int src_pos;
528 int n;
529 int filter;
530 uint32_t val;
531 uint32_t crc;
532 uint32_t status;
533
534 if ((s->mac_cr & MAC_CR_RXEN) == 0) {
535 return -1;
536 }
537
538 if (size >= 2048 || size < 14) {
539 return -1;
540 }
541
542 /* TODO: Implement FIFO overflow notification. */
543 if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
544 return -1;
545 }
546
547 filter = lan9118_filter(s, buf);
548 if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
549 return size;
550 }
551
552 offset = (s->rx_cfg >> 8) & 0x1f;
553 n = offset & 3;
554 fifo_len = (size + n + 3) >> 2;
555 /* Add a word for the CRC. */
556 fifo_len++;
557 if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
558 return -1;
559 }
560
561 DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
562 (int)size, fifo_len, filter ? "pass" : "fail");
563 val = 0;
564 crc = bswap32(crc32(~0, buf, size));
565 for (src_pos = 0; src_pos < size; src_pos++) {
566 val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
567 n++;
568 if (n == 4) {
569 n = 0;
570 rx_fifo_push(s, val);
571 val = 0;
572 }
573 }
574 if (n) {
575 val >>= ((4 - n) * 8);
576 val |= crc << (n * 8);
577 rx_fifo_push(s, val);
578 val = crc >> ((4 - n) * 8);
579 rx_fifo_push(s, val);
580 } else {
581 rx_fifo_push(s, crc);
582 }
583 n = s->rx_status_fifo_head + s->rx_status_fifo_used;
584 if (n >= s->rx_status_fifo_size) {
585 n -= s->rx_status_fifo_size;
586 }
587 s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
588 s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
589 s->rx_status_fifo_used++;
590
591 status = (size + 4) << 16;
592 if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
593 buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
594 status |= 0x00002000;
595 } else if (buf[0] & 1) {
596 status |= 0x00000400;
597 }
598 if (!filter) {
599 status |= 0x40000000;
600 }
601 s->rx_status_fifo[n] = status;
602
603 if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
604 s->int_sts |= RSFL_INT;
605 }
606 lan9118_update(s);
607
608 return size;
609}
610
611static uint32_t rx_fifo_pop(lan9118_state *s)
612{
613 int n;
614 uint32_t val;
615
616 if (s->rxp_size == 0 && s->rxp_pad == 0) {
617 s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
618 s->rx_packet_size[s->rx_packet_size_head] = 0;
619 if (s->rxp_size != 0) {
620 s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
621 s->rxp_offset = (s->rx_cfg >> 10) & 7;
622 n = s->rxp_offset + s->rxp_size;
623 switch (s->rx_cfg >> 30) {
624 case 1:
625 n = (-n) & 3;
626 break;
627 case 2:
628 n = (-n) & 7;
629 break;
630 default:
631 n = 0;
632 break;
633 }
634 s->rxp_pad = n;
635 DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
636 s->rxp_size, s->rxp_offset, s->rxp_pad);
637 }
638 }
639 if (s->rxp_offset > 0) {
640 s->rxp_offset--;
641 val = 0;
642 } else if (s->rxp_size > 0) {
643 s->rxp_size--;
644 val = s->rx_fifo[s->rx_fifo_head++];
645 if (s->rx_fifo_head >= s->rx_fifo_size) {
646 s->rx_fifo_head -= s->rx_fifo_size;
647 }
648 s->rx_fifo_used--;
649 } else if (s->rxp_pad > 0) {
650 s->rxp_pad--;
651 val = 0;
652 } else {
653 DPRINTF("RX underflow\n");
654 s->int_sts |= RXE_INT;
655 val = 0;
656 }
657 lan9118_update(s);
658 return val;
659}
660
661static void do_tx_packet(lan9118_state *s)
662{
663 int n;
664 uint32_t status;
665
666 /* FIXME: Honor TX disable, and allow queueing of packets. */
667 if (s->phy_control & 0x4000) {
668 /* This assumes the receive routine doesn't touch the VLANClient. */
669 lan9118_receive(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
670 } else {
671 qemu_send_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
672 }
673 s->txp->fifo_used = 0;
674
675 if (s->tx_status_fifo_used == 512) {
676 /* Status FIFO full */
677 return;
678 }
679 /* Add entry to status FIFO. */
680 status = s->txp->cmd_b & 0xffff0000u;
681 DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
682 n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
683 s->tx_status_fifo[n] = status;
684 s->tx_status_fifo_used++;
685 if (s->tx_status_fifo_used == 512) {
686 s->int_sts |= TSFF_INT;
687 /* TODO: Stop transmission. */
688 }
689}
690
691static uint32_t rx_status_fifo_pop(lan9118_state *s)
692{
693 uint32_t val;
694
695 val = s->rx_status_fifo[s->rx_status_fifo_head];
696 if (s->rx_status_fifo_used != 0) {
697 s->rx_status_fifo_used--;
698 s->rx_status_fifo_head++;
699 if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
700 s->rx_status_fifo_head -= s->rx_status_fifo_size;
701 }
702 /* ??? What value should be returned when the FIFO is empty? */
703 DPRINTF("RX status pop 0x%08x\n", val);
704 }
705 return val;
706}
707
708static uint32_t tx_status_fifo_pop(lan9118_state *s)
709{
710 uint32_t val;
711
712 val = s->tx_status_fifo[s->tx_status_fifo_head];
713 if (s->tx_status_fifo_used != 0) {
714 s->tx_status_fifo_used--;
715 s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
716 /* ??? What value should be returned when the FIFO is empty? */
717 }
718 return val;
719}
720
721static void tx_fifo_push(lan9118_state *s, uint32_t val)
722{
723 int n;
724
725 if (s->txp->fifo_used == s->tx_fifo_size) {
726 s->int_sts |= TDFO_INT;
727 return;
728 }
729 switch (s->txp->state) {
730 case TX_IDLE:
731 s->txp->cmd_a = val & 0x831f37ff;
732 s->txp->fifo_used++;
733 s->txp->state = TX_B;
734 s->txp->buffer_size = extract32(s->txp->cmd_a, 0, 11);
735 s->txp->offset = extract32(s->txp->cmd_a, 16, 5);
736 break;
737 case TX_B:
738 if (s->txp->cmd_a & 0x2000) {
739 /* First segment */
740 s->txp->cmd_b = val;
741 s->txp->fifo_used++;
742 /* End alignment does not include command words. */
743 n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
744 switch ((n >> 24) & 3) {
745 case 1:
746 n = (-n) & 3;
747 break;
748 case 2:
749 n = (-n) & 7;
750 break;
751 default:
752 n = 0;
753 }
754 s->txp->pad = n;
755 s->txp->len = 0;
756 }
757 DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
758 s->txp->buffer_size, s->txp->offset, s->txp->pad,
759 s->txp->cmd_a);
760 s->txp->state = TX_DATA;
761 break;
762 case TX_DATA:
763 if (s->txp->offset >= 4) {
764 s->txp->offset -= 4;
765 break;
766 }
767 if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
768 s->txp->pad--;
769 } else {
770 n = MIN(4, s->txp->buffer_size + s->txp->offset);
771 while (s->txp->offset) {
772 val >>= 8;
773 n--;
774 s->txp->offset--;
775 }
776 /* Documentation is somewhat unclear on the ordering of bytes
777 in FIFO words. Empirical results show it to be little-endian.
778 */
779 /* TODO: FIFO overflow checking. */
780 while (n--) {
781 s->txp->data[s->txp->len] = val & 0xff;
782 s->txp->len++;
783 val >>= 8;
784 s->txp->buffer_size--;
785 }
786 s->txp->fifo_used++;
787 }
788 if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
789 if (s->txp->cmd_a & 0x1000) {
790 do_tx_packet(s);
791 }
792 if (s->txp->cmd_a & 0x80000000) {
793 s->int_sts |= TX_IOC_INT;
794 }
795 s->txp->state = TX_IDLE;
796 }
797 break;
798 }
799}
800
801static uint32_t do_phy_read(lan9118_state *s, int reg)
802{
803 uint32_t val;
804
805 switch (reg) {
806 case 0: /* Basic Control */
807 return s->phy_control;
808 case 1: /* Basic Status */
809 return s->phy_status;
810 case 2: /* ID1 */
811 return 0x0007;
812 case 3: /* ID2 */
813 return 0xc0d1;
814 case 4: /* Auto-neg advertisement */
815 return s->phy_advertise;
816 case 5: /* Auto-neg Link Partner Ability */
817 return 0x0f71;
818 case 6: /* Auto-neg Expansion */
819 return 1;
820 /* TODO 17, 18, 27, 29, 30, 31 */
821 case 29: /* Interrupt source. */
822 val = s->phy_int;
823 s->phy_int = 0;
824 phy_update_irq(s);
825 return val;
826 case 30: /* Interrupt mask */
827 return s->phy_int_mask;
828 default:
829 BADF("PHY read reg %d\n", reg);
830 return 0;
831 }
832}
833
834static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
835{
836 switch (reg) {
837 case 0: /* Basic Control */
838 if (val & 0x8000) {
839 phy_reset(s);
840 break;
841 }
842 s->phy_control = val & 0x7980;
843 /* Complete autonegotiation immediately. */
844 if (val & 0x1000) {
845 s->phy_status |= 0x0020;
846 }
847 break;
848 case 4: /* Auto-neg advertisement */
849 s->phy_advertise = (val & 0x2d7f) | 0x80;
850 break;
851 /* TODO 17, 18, 27, 31 */
852 case 30: /* Interrupt mask */
853 s->phy_int_mask = val & 0xff;
854 phy_update_irq(s);
855 break;
856 default:
857 BADF("PHY write reg %d = 0x%04x\n", reg, val);
858 }
859}
860
861static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
862{
863 switch (reg) {
864 case MAC_CR:
865 if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
866 s->int_sts |= RXSTOP_INT;
867 }
868 s->mac_cr = val & ~MAC_CR_RESERVED;
869 DPRINTF("MAC_CR: %08x\n", val);
870 break;
871 case MAC_ADDRH:
872 s->conf.macaddr.a[4] = val & 0xff;
873 s->conf.macaddr.a[5] = (val >> 8) & 0xff;
874 lan9118_mac_changed(s);
875 break;
876 case MAC_ADDRL:
877 s->conf.macaddr.a[0] = val & 0xff;
878 s->conf.macaddr.a[1] = (val >> 8) & 0xff;
879 s->conf.macaddr.a[2] = (val >> 16) & 0xff;
880 s->conf.macaddr.a[3] = (val >> 24) & 0xff;
881 lan9118_mac_changed(s);
882 break;
883 case MAC_HASHH:
884 s->mac_hashh = val;
885 break;
886 case MAC_HASHL:
887 s->mac_hashl = val;
888 break;
889 case MAC_MII_ACC:
890 s->mac_mii_acc = val & 0xffc2;
891 if (val & 2) {
892 DPRINTF("PHY write %d = 0x%04x\n",
893 (val >> 6) & 0x1f, s->mac_mii_data);
894 do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
895 } else {
896 s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
897 DPRINTF("PHY read %d = 0x%04x\n",
898 (val >> 6) & 0x1f, s->mac_mii_data);
899 }
900 break;
901 case MAC_MII_DATA:
902 s->mac_mii_data = val & 0xffff;
903 break;
904 case MAC_FLOW:
905 s->mac_flow = val & 0xffff0000;
906 break;
907 case MAC_VLAN1:
908 /* Writing to this register changes a condition for
909 * FrameTooLong bit in rx_status. Since we do not set
910 * FrameTooLong anyway, just ignore write to this.
911 */
912 break;
913 default:
914 qemu_log_mask(LOG_GUEST_ERROR,
915 "lan9118: Unimplemented MAC register write: %d = 0x%x\n",
916 s->mac_cmd & 0xf, val);
917 }
918}
919
920static uint32_t do_mac_read(lan9118_state *s, int reg)
921{
922 switch (reg) {
923 case MAC_CR:
924 return s->mac_cr;
925 case MAC_ADDRH:
926 return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
927 case MAC_ADDRL:
928 return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
929 | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
930 case MAC_HASHH:
931 return s->mac_hashh;
932 break;
933 case MAC_HASHL:
934 return s->mac_hashl;
935 break;
936 case MAC_MII_ACC:
937 return s->mac_mii_acc;
938 case MAC_MII_DATA:
939 return s->mac_mii_data;
940 case MAC_FLOW:
941 return s->mac_flow;
942 default:
943 qemu_log_mask(LOG_GUEST_ERROR,
944 "lan9118: Unimplemented MAC register read: %d\n",
945 s->mac_cmd & 0xf);
946 return 0;
947 }
948}
949
950static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
951{
952 s->e2p_cmd = (s->e2p_cmd & E2P_CMD_MAC_ADDR_LOADED) | (cmd << 28) | addr;
953 switch (cmd) {
954 case 0:
955 s->e2p_data = s->eeprom[addr];
956 DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
957 break;
958 case 1:
959 s->eeprom_writable = 0;
960 DPRINTF("EEPROM Write Disable\n");
961 break;
962 case 2: /* EWEN */
963 s->eeprom_writable = 1;
964 DPRINTF("EEPROM Write Enable\n");
965 break;
966 case 3: /* WRITE */
967 if (s->eeprom_writable) {
968 s->eeprom[addr] &= s->e2p_data;
969 DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
970 } else {
971 DPRINTF("EEPROM Write %d (ignored)\n", addr);
972 }
973 break;
974 case 4: /* WRAL */
975 if (s->eeprom_writable) {
976 for (addr = 0; addr < 128; addr++) {
977 s->eeprom[addr] &= s->e2p_data;
978 }
979 DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
980 } else {
981 DPRINTF("EEPROM Write All (ignored)\n");
982 }
983 break;
984 case 5: /* ERASE */
985 if (s->eeprom_writable) {
986 s->eeprom[addr] = 0xff;
987 DPRINTF("EEPROM Erase %d\n", addr);
988 } else {
989 DPRINTF("EEPROM Erase %d (ignored)\n", addr);
990 }
991 break;
992 case 6: /* ERAL */
993 if (s->eeprom_writable) {
994 memset(s->eeprom, 0xff, 128);
995 DPRINTF("EEPROM Erase All\n");
996 } else {
997 DPRINTF("EEPROM Erase All (ignored)\n");
998 }
999 break;
1000 case 7: /* RELOAD */
1001 lan9118_reload_eeprom(s);
1002 break;
1003 }
1004}
1005
1006static void lan9118_tick(void *opaque)
1007{
1008 lan9118_state *s = (lan9118_state *)opaque;
1009 if (s->int_en & GPT_INT) {
1010 s->int_sts |= GPT_INT;
1011 }
1012 lan9118_update(s);
1013}
1014
1015static void lan9118_writel(void *opaque, hwaddr offset,
1016 uint64_t val, unsigned size)
1017{
1018 lan9118_state *s = (lan9118_state *)opaque;
1019 offset &= 0xff;
1020
1021 //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
1022 if (offset >= 0x20 && offset < 0x40) {
1023 /* TX FIFO */
1024 tx_fifo_push(s, val);
1025 return;
1026 }
1027 switch (offset) {
1028 case CSR_IRQ_CFG:
1029 /* TODO: Implement interrupt deassertion intervals. */
1030 val &= (IRQ_EN | IRQ_POL | IRQ_TYPE);
1031 s->irq_cfg = (s->irq_cfg & IRQ_INT) | val;
1032 break;
1033 case CSR_INT_STS:
1034 s->int_sts &= ~val;
1035 break;
1036 case CSR_INT_EN:
1037 s->int_en = val & ~RESERVED_INT;
1038 s->int_sts |= val & SW_INT;
1039 break;
1040 case CSR_FIFO_INT:
1041 DPRINTF("FIFO INT levels %08x\n", val);
1042 s->fifo_int = val;
1043 break;
1044 case CSR_RX_CFG:
1045 if (val & 0x8000) {
1046 /* RX_DUMP */
1047 s->rx_fifo_used = 0;
1048 s->rx_status_fifo_used = 0;
1049 s->rx_packet_size_tail = s->rx_packet_size_head;
1050 s->rx_packet_size[s->rx_packet_size_head] = 0;
1051 }
1052 s->rx_cfg = val & 0xcfff1ff0;
1053 break;
1054 case CSR_TX_CFG:
1055 if (val & 0x8000) {
1056 s->tx_status_fifo_used = 0;
1057 }
1058 if (val & 0x4000) {
1059 s->txp->state = TX_IDLE;
1060 s->txp->fifo_used = 0;
1061 s->txp->cmd_a = 0xffffffff;
1062 }
1063 s->tx_cfg = val & 6;
1064 break;
1065 case CSR_HW_CFG:
1066 if (val & 1) {
1067 /* SRST */
1068 lan9118_reset(DEVICE(s));
1069 } else {
1070 s->hw_cfg = (val & 0x003f300) | (s->hw_cfg & 0x4);
1071 }
1072 break;
1073 case CSR_RX_DP_CTRL:
1074 if (val & 0x80000000) {
1075 /* Skip forward to next packet. */
1076 s->rxp_pad = 0;
1077 s->rxp_offset = 0;
1078 if (s->rxp_size == 0) {
1079 /* Pop a word to start the next packet. */
1080 rx_fifo_pop(s);
1081 s->rxp_pad = 0;
1082 s->rxp_offset = 0;
1083 }
1084 s->rx_fifo_head += s->rxp_size;
1085 if (s->rx_fifo_head >= s->rx_fifo_size) {
1086 s->rx_fifo_head -= s->rx_fifo_size;
1087 }
1088 }
1089 break;
1090 case CSR_PMT_CTRL:
1091 if (val & 0x400) {
1092 phy_reset(s);
1093 }
1094 s->pmt_ctrl &= ~0x34e;
1095 s->pmt_ctrl |= (val & 0x34e);
1096 break;
1097 case CSR_GPIO_CFG:
1098 /* Probably just enabling LEDs. */
1099 s->gpio_cfg = val & 0x7777071f;
1100 break;
1101 case CSR_GPT_CFG:
1102 if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
1103 if (val & GPT_TIMER_EN) {
1104 ptimer_set_count(s->timer, val & 0xffff);
1105 ptimer_run(s->timer, 0);
1106 } else {
1107 ptimer_stop(s->timer);
1108 ptimer_set_count(s->timer, 0xffff);
1109 }
1110 }
1111 s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
1112 break;
1113 case CSR_WORD_SWAP:
1114 /* Ignored because we're in 32-bit mode. */
1115 s->word_swap = val;
1116 break;
1117 case CSR_MAC_CSR_CMD:
1118 s->mac_cmd = val & 0x4000000f;
1119 if (val & 0x80000000) {
1120 if (val & 0x40000000) {
1121 s->mac_data = do_mac_read(s, val & 0xf);
1122 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
1123 } else {
1124 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
1125 do_mac_write(s, val & 0xf, s->mac_data);
1126 }
1127 }
1128 break;
1129 case CSR_MAC_CSR_DATA:
1130 s->mac_data = val;
1131 break;
1132 case CSR_AFC_CFG:
1133 s->afc_cfg = val & 0x00ffffff;
1134 break;
1135 case CSR_E2P_CMD:
1136 lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0x7f);
1137 break;
1138 case CSR_E2P_DATA:
1139 s->e2p_data = val & 0xff;
1140 break;
1141
1142 default:
1143 qemu_log_mask(LOG_GUEST_ERROR, "lan9118_write: Bad reg 0x%x = %x\n",
1144 (int)offset, (int)val);
1145 break;
1146 }
1147 lan9118_update(s);
1148}
1149
1150static void lan9118_writew(void *opaque, hwaddr offset,
1151 uint32_t val)
1152{
1153 lan9118_state *s = (lan9118_state *)opaque;
1154 offset &= 0xff;
1155
1156 if (s->write_word_prev_offset != (offset & ~0x3)) {
1157 /* New offset, reset word counter */
1158 s->write_word_n = 0;
1159 s->write_word_prev_offset = offset & ~0x3;
1160 }
1161
1162 if (offset & 0x2) {
1163 s->write_word_h = val;
1164 } else {
1165 s->write_word_l = val;
1166 }
1167
1168 //DPRINTF("Writew reg 0x%02x = 0x%08x\n", (int)offset, val);
1169 s->write_word_n++;
1170 if (s->write_word_n == 2) {
1171 s->write_word_n = 0;
1172 lan9118_writel(s, offset & ~3, s->write_word_l +
1173 (s->write_word_h << 16), 4);
1174 }
1175}
1176
1177static void lan9118_16bit_mode_write(void *opaque, hwaddr offset,
1178 uint64_t val, unsigned size)
1179{
1180 switch (size) {
1181 case 2:
1182 lan9118_writew(opaque, offset, (uint32_t)val);
1183 return;
1184 case 4:
1185 lan9118_writel(opaque, offset, val, size);
1186 return;
1187 }
1188
1189 hw_error("lan9118_write: Bad size 0x%x\n", size);
1190}
1191
1192static uint64_t lan9118_readl(void *opaque, hwaddr offset,
1193 unsigned size)
1194{
1195 lan9118_state *s = (lan9118_state *)opaque;
1196
1197 //DPRINTF("Read reg 0x%02x\n", (int)offset);
1198 if (offset < 0x20) {
1199 /* RX FIFO */
1200 return rx_fifo_pop(s);
1201 }
1202 switch (offset) {
1203 case 0x40:
1204 return rx_status_fifo_pop(s);
1205 case 0x44:
1206 return s->rx_status_fifo[s->tx_status_fifo_head];
1207 case 0x48:
1208 return tx_status_fifo_pop(s);
1209 case 0x4c:
1210 return s->tx_status_fifo[s->tx_status_fifo_head];
1211 case CSR_ID_REV:
1212 return 0x01180001;
1213 case CSR_IRQ_CFG:
1214 return s->irq_cfg;
1215 case CSR_INT_STS:
1216 return s->int_sts;
1217 case CSR_INT_EN:
1218 return s->int_en;
1219 case CSR_BYTE_TEST:
1220 return 0x87654321;
1221 case CSR_FIFO_INT:
1222 return s->fifo_int;
1223 case CSR_RX_CFG:
1224 return s->rx_cfg;
1225 case CSR_TX_CFG:
1226 return s->tx_cfg;
1227 case CSR_HW_CFG:
1228 return s->hw_cfg;
1229 case CSR_RX_DP_CTRL:
1230 return 0;
1231 case CSR_RX_FIFO_INF:
1232 return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1233 case CSR_TX_FIFO_INF:
1234 return (s->tx_status_fifo_used << 16)
1235 | (s->tx_fifo_size - s->txp->fifo_used);
1236 case CSR_PMT_CTRL:
1237 return s->pmt_ctrl;
1238 case CSR_GPIO_CFG:
1239 return s->gpio_cfg;
1240 case CSR_GPT_CFG:
1241 return s->gpt_cfg;
1242 case CSR_GPT_CNT:
1243 return ptimer_get_count(s->timer);
1244 case CSR_WORD_SWAP:
1245 return s->word_swap;
1246 case CSR_FREE_RUN:
1247 return (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 40) - s->free_timer_start;
1248 case CSR_RX_DROP:
1249 /* TODO: Implement dropped frames counter. */
1250 return 0;
1251 case CSR_MAC_CSR_CMD:
1252 return s->mac_cmd;
1253 case CSR_MAC_CSR_DATA:
1254 return s->mac_data;
1255 case CSR_AFC_CFG:
1256 return s->afc_cfg;
1257 case CSR_E2P_CMD:
1258 return s->e2p_cmd;
1259 case CSR_E2P_DATA:
1260 return s->e2p_data;
1261 }
1262 qemu_log_mask(LOG_GUEST_ERROR, "lan9118_read: Bad reg 0x%x\n", (int)offset);
1263 return 0;
1264}
1265
1266static uint32_t lan9118_readw(void *opaque, hwaddr offset)
1267{
1268 lan9118_state *s = (lan9118_state *)opaque;
1269 uint32_t val;
1270
1271 if (s->read_word_prev_offset != (offset & ~0x3)) {
1272 /* New offset, reset word counter */
1273 s->read_word_n = 0;
1274 s->read_word_prev_offset = offset & ~0x3;
1275 }
1276
1277 s->read_word_n++;
1278 if (s->read_word_n == 1) {
1279 s->read_long = lan9118_readl(s, offset & ~3, 4);
1280 } else {
1281 s->read_word_n = 0;
1282 }
1283
1284 if (offset & 2) {
1285 val = s->read_long >> 16;
1286 } else {
1287 val = s->read_long & 0xFFFF;
1288 }
1289
1290 //DPRINTF("Readw reg 0x%02x, val 0x%x\n", (int)offset, val);
1291 return val;
1292}
1293
1294static uint64_t lan9118_16bit_mode_read(void *opaque, hwaddr offset,
1295 unsigned size)
1296{
1297 switch (size) {
1298 case 2:
1299 return lan9118_readw(opaque, offset);
1300 case 4:
1301 return lan9118_readl(opaque, offset, size);
1302 }
1303
1304 hw_error("lan9118_read: Bad size 0x%x\n", size);
1305 return 0;
1306}
1307
1308static const MemoryRegionOps lan9118_mem_ops = {
1309 .read = lan9118_readl,
1310 .write = lan9118_writel,
1311 .endianness = DEVICE_NATIVE_ENDIAN,
1312};
1313
1314static const MemoryRegionOps lan9118_16bit_mem_ops = {
1315 .read = lan9118_16bit_mode_read,
1316 .write = lan9118_16bit_mode_write,
1317 .endianness = DEVICE_NATIVE_ENDIAN,
1318};
1319
1320static NetClientInfo net_lan9118_info = {
1321 .type = NET_CLIENT_DRIVER_NIC,
1322 .size = sizeof(NICState),
1323 .receive = lan9118_receive,
1324 .link_status_changed = lan9118_set_link,
1325};
1326
1327static void lan9118_realize(DeviceState *dev, Error **errp)
1328{
1329 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
1330 lan9118_state *s = LAN9118(dev);
1331 QEMUBH *bh;
1332 int i;
1333 const MemoryRegionOps *mem_ops =
1334 s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
1335
1336 memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
1337 "lan9118-mmio", 0x100);
1338 sysbus_init_mmio(sbd, &s->mmio);
1339 sysbus_init_irq(sbd, &s->irq);
1340 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1341
1342 s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1343 object_get_typename(OBJECT(dev)), dev->id, s);
1344 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
1345 s->eeprom[0] = 0xa5;
1346 for (i = 0; i < 6; i++) {
1347 s->eeprom[i + 1] = s->conf.macaddr.a[i];
1348 }
1349 s->pmt_ctrl = 1;
1350 s->txp = &s->tx_packet;
1351
1352 bh = qemu_bh_new(lan9118_tick, s);
1353 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT);
1354 ptimer_set_freq(s->timer, 10000);
1355 ptimer_set_limit(s->timer, 0xffff, 1);
1356}
1357
1358static Property lan9118_properties[] = {
1359 DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1360 DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0),
1361 DEFINE_PROP_END_OF_LIST(),
1362};
1363
1364static void lan9118_class_init(ObjectClass *klass, void *data)
1365{
1366 DeviceClass *dc = DEVICE_CLASS(klass);
1367
1368 dc->reset = lan9118_reset;
1369 dc->props = lan9118_properties;
1370 dc->vmsd = &vmstate_lan9118;
1371 dc->realize = lan9118_realize;
1372}
1373
1374static const TypeInfo lan9118_info = {
1375 .name = TYPE_LAN9118,
1376 .parent = TYPE_SYS_BUS_DEVICE,
1377 .instance_size = sizeof(lan9118_state),
1378 .class_init = lan9118_class_init,
1379};
1380
1381static void lan9118_register_types(void)
1382{
1383 type_register_static(&lan9118_info);
1384}
1385
1386/* Legacy helper function. Should go away when machine config files are
1387 implemented. */
1388void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1389{
1390 DeviceState *dev;
1391 SysBusDevice *s;
1392
1393 qemu_check_nic_model(nd, "lan9118");
1394 dev = qdev_create(NULL, TYPE_LAN9118);
1395 qdev_set_nic_properties(dev, nd);
1396 qdev_init_nofail(dev);
1397 s = SYS_BUS_DEVICE(dev);
1398 sysbus_mmio_map(s, 0, base);
1399 sysbus_connect_irq(s, 0, irq);
1400}
1401
1402type_init(lan9118_register_types)
1403