1 | /* |
2 | * ColdFire Fast Ethernet Controller emulation. |
3 | * |
4 | * Copyright (c) 2007 CodeSourcery. |
5 | * |
6 | * This code is licensed under the GPL |
7 | */ |
8 | |
9 | #include "qemu/osdep.h" |
10 | #include "hw/hw.h" |
11 | #include "hw/irq.h" |
12 | #include "net/net.h" |
13 | #include "qemu/module.h" |
14 | #include "hw/m68k/mcf.h" |
15 | #include "hw/m68k/mcf_fec.h" |
16 | #include "hw/net/mii.h" |
17 | #include "hw/qdev-properties.h" |
18 | #include "hw/sysbus.h" |
19 | /* For crc32 */ |
20 | #include <zlib.h> |
21 | |
22 | //#define DEBUG_FEC 1 |
23 | |
24 | #ifdef DEBUG_FEC |
25 | #define DPRINTF(fmt, ...) \ |
26 | do { printf("mcf_fec: " fmt , ## __VA_ARGS__); } while (0) |
27 | #else |
28 | #define DPRINTF(fmt, ...) do {} while(0) |
29 | #endif |
30 | |
31 | #define FEC_MAX_DESC 1024 |
32 | #define FEC_MAX_FRAME_SIZE 2032 |
33 | #define FEC_MIB_SIZE 64 |
34 | |
35 | typedef struct { |
36 | SysBusDevice parent_obj; |
37 | |
38 | MemoryRegion iomem; |
39 | qemu_irq irq[FEC_NUM_IRQ]; |
40 | NICState *nic; |
41 | NICConf conf; |
42 | uint32_t irq_state; |
43 | uint32_t eir; |
44 | uint32_t eimr; |
45 | int rx_enabled; |
46 | uint32_t rx_descriptor; |
47 | uint32_t tx_descriptor; |
48 | uint32_t ecr; |
49 | uint32_t mmfr; |
50 | uint32_t mscr; |
51 | uint32_t rcr; |
52 | uint32_t tcr; |
53 | uint32_t tfwr; |
54 | uint32_t rfsr; |
55 | uint32_t erdsr; |
56 | uint32_t etdsr; |
57 | uint32_t emrbr; |
58 | uint32_t mib[FEC_MIB_SIZE]; |
59 | } mcf_fec_state; |
60 | |
61 | #define FEC_INT_HB 0x80000000 |
62 | #define FEC_INT_BABR 0x40000000 |
63 | #define FEC_INT_BABT 0x20000000 |
64 | #define FEC_INT_GRA 0x10000000 |
65 | #define FEC_INT_TXF 0x08000000 |
66 | #define FEC_INT_TXB 0x04000000 |
67 | #define FEC_INT_RXF 0x02000000 |
68 | #define FEC_INT_RXB 0x01000000 |
69 | #define FEC_INT_MII 0x00800000 |
70 | #define FEC_INT_EB 0x00400000 |
71 | #define FEC_INT_LC 0x00200000 |
72 | #define FEC_INT_RL 0x00100000 |
73 | #define FEC_INT_UN 0x00080000 |
74 | |
75 | #define FEC_EN 2 |
76 | #define FEC_RESET 1 |
77 | |
78 | /* Map interrupt flags onto IRQ lines. */ |
79 | static const uint32_t mcf_fec_irq_map[FEC_NUM_IRQ] = { |
80 | FEC_INT_TXF, |
81 | FEC_INT_TXB, |
82 | FEC_INT_UN, |
83 | FEC_INT_RL, |
84 | FEC_INT_RXF, |
85 | FEC_INT_RXB, |
86 | FEC_INT_MII, |
87 | FEC_INT_LC, |
88 | FEC_INT_HB, |
89 | FEC_INT_GRA, |
90 | FEC_INT_EB, |
91 | FEC_INT_BABT, |
92 | FEC_INT_BABR |
93 | }; |
94 | |
95 | /* Buffer Descriptor. */ |
96 | typedef struct { |
97 | uint16_t flags; |
98 | uint16_t length; |
99 | uint32_t data; |
100 | } mcf_fec_bd; |
101 | |
102 | #define FEC_BD_R 0x8000 |
103 | #define FEC_BD_E 0x8000 |
104 | #define FEC_BD_O1 0x4000 |
105 | #define FEC_BD_W 0x2000 |
106 | #define FEC_BD_O2 0x1000 |
107 | #define FEC_BD_L 0x0800 |
108 | #define FEC_BD_TC 0x0400 |
109 | #define FEC_BD_ABC 0x0200 |
110 | #define FEC_BD_M 0x0100 |
111 | #define FEC_BD_BC 0x0080 |
112 | #define FEC_BD_MC 0x0040 |
113 | #define FEC_BD_LG 0x0020 |
114 | #define FEC_BD_NO 0x0010 |
115 | #define FEC_BD_CR 0x0004 |
116 | #define FEC_BD_OV 0x0002 |
117 | #define FEC_BD_TR 0x0001 |
118 | |
119 | #define MIB_RMON_T_DROP 0 |
120 | #define MIB_RMON_T_PACKETS 1 |
121 | #define MIB_RMON_T_BC_PKT 2 |
122 | #define MIB_RMON_T_MC_PKT 3 |
123 | #define MIB_RMON_T_CRC_ALIGN 4 |
124 | #define MIB_RMON_T_UNDERSIZE 5 |
125 | #define MIB_RMON_T_OVERSIZE 6 |
126 | #define MIB_RMON_T_FRAG 7 |
127 | #define MIB_RMON_T_JAB 8 |
128 | #define MIB_RMON_T_COL 9 |
129 | #define MIB_RMON_T_P64 10 |
130 | #define MIB_RMON_T_P65TO127 11 |
131 | #define MIB_RMON_T_P128TO255 12 |
132 | #define MIB_RMON_T_P256TO511 13 |
133 | #define MIB_RMON_T_P512TO1023 14 |
134 | #define MIB_RMON_T_P1024TO2047 15 |
135 | #define MIB_RMON_T_P_GTE2048 16 |
136 | #define MIB_RMON_T_OCTETS 17 |
137 | #define MIB_IEEE_T_DROP 18 |
138 | #define MIB_IEEE_T_FRAME_OK 19 |
139 | #define MIB_IEEE_T_1COL 20 |
140 | #define MIB_IEEE_T_MCOL 21 |
141 | #define MIB_IEEE_T_DEF 22 |
142 | #define MIB_IEEE_T_LCOL 23 |
143 | #define MIB_IEEE_T_EXCOL 24 |
144 | #define MIB_IEEE_T_MACERR 25 |
145 | #define MIB_IEEE_T_CSERR 26 |
146 | #define MIB_IEEE_T_SQE 27 |
147 | #define MIB_IEEE_T_FDXFC 28 |
148 | #define MIB_IEEE_T_OCTETS_OK 29 |
149 | |
150 | #define MIB_RMON_R_DROP 32 |
151 | #define MIB_RMON_R_PACKETS 33 |
152 | #define MIB_RMON_R_BC_PKT 34 |
153 | #define MIB_RMON_R_MC_PKT 35 |
154 | #define MIB_RMON_R_CRC_ALIGN 36 |
155 | #define MIB_RMON_R_UNDERSIZE 37 |
156 | #define MIB_RMON_R_OVERSIZE 38 |
157 | #define MIB_RMON_R_FRAG 39 |
158 | #define MIB_RMON_R_JAB 40 |
159 | #define MIB_RMON_R_RESVD_0 41 |
160 | #define MIB_RMON_R_P64 42 |
161 | #define MIB_RMON_R_P65TO127 43 |
162 | #define MIB_RMON_R_P128TO255 44 |
163 | #define MIB_RMON_R_P256TO511 45 |
164 | #define MIB_RMON_R_P512TO1023 46 |
165 | #define MIB_RMON_R_P1024TO2047 47 |
166 | #define MIB_RMON_R_P_GTE2048 48 |
167 | #define MIB_RMON_R_OCTETS 49 |
168 | #define MIB_IEEE_R_DROP 50 |
169 | #define MIB_IEEE_R_FRAME_OK 51 |
170 | #define MIB_IEEE_R_CRC 52 |
171 | #define MIB_IEEE_R_ALIGN 53 |
172 | #define MIB_IEEE_R_MACERR 54 |
173 | #define MIB_IEEE_R_FDXFC 55 |
174 | #define MIB_IEEE_R_OCTETS_OK 56 |
175 | |
176 | static void mcf_fec_read_bd(mcf_fec_bd *bd, uint32_t addr) |
177 | { |
178 | cpu_physical_memory_read(addr, bd, sizeof(*bd)); |
179 | be16_to_cpus(&bd->flags); |
180 | be16_to_cpus(&bd->length); |
181 | be32_to_cpus(&bd->data); |
182 | } |
183 | |
184 | static void mcf_fec_write_bd(mcf_fec_bd *bd, uint32_t addr) |
185 | { |
186 | mcf_fec_bd tmp; |
187 | tmp.flags = cpu_to_be16(bd->flags); |
188 | tmp.length = cpu_to_be16(bd->length); |
189 | tmp.data = cpu_to_be32(bd->data); |
190 | cpu_physical_memory_write(addr, &tmp, sizeof(tmp)); |
191 | } |
192 | |
193 | static void mcf_fec_update(mcf_fec_state *s) |
194 | { |
195 | uint32_t active; |
196 | uint32_t changed; |
197 | uint32_t mask; |
198 | int i; |
199 | |
200 | active = s->eir & s->eimr; |
201 | changed = active ^s->irq_state; |
202 | for (i = 0; i < FEC_NUM_IRQ; i++) { |
203 | mask = mcf_fec_irq_map[i]; |
204 | if (changed & mask) { |
205 | DPRINTF("IRQ %d = %d\n" , i, (active & mask) != 0); |
206 | qemu_set_irq(s->irq[i], (active & mask) != 0); |
207 | } |
208 | } |
209 | s->irq_state = active; |
210 | } |
211 | |
212 | static void mcf_fec_tx_stats(mcf_fec_state *s, int size) |
213 | { |
214 | s->mib[MIB_RMON_T_PACKETS]++; |
215 | s->mib[MIB_RMON_T_OCTETS] += size; |
216 | if (size < 64) { |
217 | s->mib[MIB_RMON_T_FRAG]++; |
218 | } else if (size == 64) { |
219 | s->mib[MIB_RMON_T_P64]++; |
220 | } else if (size < 128) { |
221 | s->mib[MIB_RMON_T_P65TO127]++; |
222 | } else if (size < 256) { |
223 | s->mib[MIB_RMON_T_P128TO255]++; |
224 | } else if (size < 512) { |
225 | s->mib[MIB_RMON_T_P256TO511]++; |
226 | } else if (size < 1024) { |
227 | s->mib[MIB_RMON_T_P512TO1023]++; |
228 | } else if (size < 2048) { |
229 | s->mib[MIB_RMON_T_P1024TO2047]++; |
230 | } else { |
231 | s->mib[MIB_RMON_T_P_GTE2048]++; |
232 | } |
233 | s->mib[MIB_IEEE_T_FRAME_OK]++; |
234 | s->mib[MIB_IEEE_T_OCTETS_OK] += size; |
235 | } |
236 | |
237 | static void mcf_fec_do_tx(mcf_fec_state *s) |
238 | { |
239 | uint32_t addr; |
240 | mcf_fec_bd bd; |
241 | int frame_size; |
242 | int len, descnt = 0; |
243 | uint8_t frame[FEC_MAX_FRAME_SIZE]; |
244 | uint8_t *ptr; |
245 | |
246 | DPRINTF("do_tx\n" ); |
247 | ptr = frame; |
248 | frame_size = 0; |
249 | addr = s->tx_descriptor; |
250 | while (descnt++ < FEC_MAX_DESC) { |
251 | mcf_fec_read_bd(&bd, addr); |
252 | DPRINTF("tx_bd %x flags %04x len %d data %08x\n" , |
253 | addr, bd.flags, bd.length, bd.data); |
254 | if ((bd.flags & FEC_BD_R) == 0) { |
255 | /* Run out of descriptors to transmit. */ |
256 | break; |
257 | } |
258 | len = bd.length; |
259 | if (frame_size + len > FEC_MAX_FRAME_SIZE) { |
260 | len = FEC_MAX_FRAME_SIZE - frame_size; |
261 | s->eir |= FEC_INT_BABT; |
262 | } |
263 | cpu_physical_memory_read(bd.data, ptr, len); |
264 | ptr += len; |
265 | frame_size += len; |
266 | if (bd.flags & FEC_BD_L) { |
267 | /* Last buffer in frame. */ |
268 | DPRINTF("Sending packet\n" ); |
269 | qemu_send_packet(qemu_get_queue(s->nic), frame, frame_size); |
270 | mcf_fec_tx_stats(s, frame_size); |
271 | ptr = frame; |
272 | frame_size = 0; |
273 | s->eir |= FEC_INT_TXF; |
274 | } |
275 | s->eir |= FEC_INT_TXB; |
276 | bd.flags &= ~FEC_BD_R; |
277 | /* Write back the modified descriptor. */ |
278 | mcf_fec_write_bd(&bd, addr); |
279 | /* Advance to the next descriptor. */ |
280 | if ((bd.flags & FEC_BD_W) != 0) { |
281 | addr = s->etdsr; |
282 | } else { |
283 | addr += 8; |
284 | } |
285 | } |
286 | s->tx_descriptor = addr; |
287 | } |
288 | |
289 | static void mcf_fec_enable_rx(mcf_fec_state *s) |
290 | { |
291 | NetClientState *nc = qemu_get_queue(s->nic); |
292 | mcf_fec_bd bd; |
293 | |
294 | mcf_fec_read_bd(&bd, s->rx_descriptor); |
295 | s->rx_enabled = ((bd.flags & FEC_BD_E) != 0); |
296 | if (s->rx_enabled) { |
297 | qemu_flush_queued_packets(nc); |
298 | } |
299 | } |
300 | |
301 | static void mcf_fec_reset(DeviceState *dev) |
302 | { |
303 | mcf_fec_state *s = MCF_FEC_NET(dev); |
304 | |
305 | s->eir = 0; |
306 | s->eimr = 0; |
307 | s->rx_enabled = 0; |
308 | s->ecr = 0; |
309 | s->mscr = 0; |
310 | s->rcr = 0x05ee0001; |
311 | s->tcr = 0; |
312 | s->tfwr = 0; |
313 | s->rfsr = 0x500; |
314 | } |
315 | |
316 | #define MMFR_WRITE_OP (1 << 28) |
317 | #define MMFR_READ_OP (2 << 28) |
318 | #define MMFR_PHYADDR(v) (((v) >> 23) & 0x1f) |
319 | #define MMFR_REGNUM(v) (((v) >> 18) & 0x1f) |
320 | |
321 | static uint64_t mcf_fec_read_mdio(mcf_fec_state *s) |
322 | { |
323 | uint64_t v; |
324 | |
325 | if (s->mmfr & MMFR_WRITE_OP) |
326 | return s->mmfr; |
327 | if (MMFR_PHYADDR(s->mmfr) != 1) |
328 | return s->mmfr |= 0xffff; |
329 | |
330 | switch (MMFR_REGNUM(s->mmfr)) { |
331 | case MII_BMCR: |
332 | v = MII_BMCR_SPEED | MII_BMCR_AUTOEN | MII_BMCR_FD; |
333 | break; |
334 | case MII_BMSR: |
335 | v = MII_BMSR_100TX_FD | MII_BMSR_100TX_HD | MII_BMSR_10T_FD | |
336 | MII_BMSR_10T_HD | MII_BMSR_MFPS | MII_BMSR_AN_COMP | |
337 | MII_BMSR_AUTONEG | MII_BMSR_LINK_ST; |
338 | break; |
339 | case MII_PHYID1: |
340 | v = DP83848_PHYID1; |
341 | break; |
342 | case MII_PHYID2: |
343 | v = DP83848_PHYID2; |
344 | break; |
345 | case MII_ANAR: |
346 | v = MII_ANAR_TXFD | MII_ANAR_TX | MII_ANAR_10FD | |
347 | MII_ANAR_10 | MII_ANAR_CSMACD; |
348 | break; |
349 | case MII_ANLPAR: |
350 | v = MII_ANLPAR_ACK | MII_ANLPAR_TXFD | MII_ANLPAR_TX | |
351 | MII_ANLPAR_10FD | MII_ANLPAR_10 | MII_ANLPAR_CSMACD; |
352 | break; |
353 | default: |
354 | v = 0xffff; |
355 | break; |
356 | } |
357 | s->mmfr = (s->mmfr & ~0xffff) | v; |
358 | return s->mmfr; |
359 | } |
360 | |
361 | static uint64_t mcf_fec_read(void *opaque, hwaddr addr, |
362 | unsigned size) |
363 | { |
364 | mcf_fec_state *s = (mcf_fec_state *)opaque; |
365 | switch (addr & 0x3ff) { |
366 | case 0x004: return s->eir; |
367 | case 0x008: return s->eimr; |
368 | case 0x010: return s->rx_enabled ? (1 << 24) : 0; /* RDAR */ |
369 | case 0x014: return 0; /* TDAR */ |
370 | case 0x024: return s->ecr; |
371 | case 0x040: return mcf_fec_read_mdio(s); |
372 | case 0x044: return s->mscr; |
373 | case 0x064: return 0; /* MIBC */ |
374 | case 0x084: return s->rcr; |
375 | case 0x0c4: return s->tcr; |
376 | case 0x0e4: /* PALR */ |
377 | return (s->conf.macaddr.a[0] << 24) | (s->conf.macaddr.a[1] << 16) |
378 | | (s->conf.macaddr.a[2] << 8) | s->conf.macaddr.a[3]; |
379 | break; |
380 | case 0x0e8: /* PAUR */ |
381 | return (s->conf.macaddr.a[4] << 24) | (s->conf.macaddr.a[5] << 16) | 0x8808; |
382 | case 0x0ec: return 0x10000; /* OPD */ |
383 | case 0x118: return 0; |
384 | case 0x11c: return 0; |
385 | case 0x120: return 0; |
386 | case 0x124: return 0; |
387 | case 0x144: return s->tfwr; |
388 | case 0x14c: return 0x600; |
389 | case 0x150: return s->rfsr; |
390 | case 0x180: return s->erdsr; |
391 | case 0x184: return s->etdsr; |
392 | case 0x188: return s->emrbr; |
393 | case 0x200 ... 0x2e0: return s->mib[(addr & 0x1ff) / 4]; |
394 | default: |
395 | hw_error("mcf_fec_read: Bad address 0x%x\n" , (int)addr); |
396 | return 0; |
397 | } |
398 | } |
399 | |
400 | static void mcf_fec_write(void *opaque, hwaddr addr, |
401 | uint64_t value, unsigned size) |
402 | { |
403 | mcf_fec_state *s = (mcf_fec_state *)opaque; |
404 | switch (addr & 0x3ff) { |
405 | case 0x004: |
406 | s->eir &= ~value; |
407 | break; |
408 | case 0x008: |
409 | s->eimr = value; |
410 | break; |
411 | case 0x010: /* RDAR */ |
412 | if ((s->ecr & FEC_EN) && !s->rx_enabled) { |
413 | DPRINTF("RX enable\n" ); |
414 | mcf_fec_enable_rx(s); |
415 | } |
416 | break; |
417 | case 0x014: /* TDAR */ |
418 | if (s->ecr & FEC_EN) { |
419 | mcf_fec_do_tx(s); |
420 | } |
421 | break; |
422 | case 0x024: |
423 | s->ecr = value; |
424 | if (value & FEC_RESET) { |
425 | DPRINTF("Reset\n" ); |
426 | mcf_fec_reset(opaque); |
427 | } |
428 | if ((s->ecr & FEC_EN) == 0) { |
429 | s->rx_enabled = 0; |
430 | } |
431 | break; |
432 | case 0x040: |
433 | s->mmfr = value; |
434 | s->eir |= FEC_INT_MII; |
435 | break; |
436 | case 0x044: |
437 | s->mscr = value & 0xfe; |
438 | break; |
439 | case 0x064: |
440 | /* TODO: Implement MIB. */ |
441 | break; |
442 | case 0x084: |
443 | s->rcr = value & 0x07ff003f; |
444 | /* TODO: Implement LOOP mode. */ |
445 | break; |
446 | case 0x0c4: /* TCR */ |
447 | /* We transmit immediately, so raise GRA immediately. */ |
448 | s->tcr = value; |
449 | if (value & 1) |
450 | s->eir |= FEC_INT_GRA; |
451 | break; |
452 | case 0x0e4: /* PALR */ |
453 | s->conf.macaddr.a[0] = value >> 24; |
454 | s->conf.macaddr.a[1] = value >> 16; |
455 | s->conf.macaddr.a[2] = value >> 8; |
456 | s->conf.macaddr.a[3] = value; |
457 | break; |
458 | case 0x0e8: /* PAUR */ |
459 | s->conf.macaddr.a[4] = value >> 24; |
460 | s->conf.macaddr.a[5] = value >> 16; |
461 | break; |
462 | case 0x0ec: |
463 | /* OPD */ |
464 | break; |
465 | case 0x118: |
466 | case 0x11c: |
467 | case 0x120: |
468 | case 0x124: |
469 | /* TODO: implement MAC hash filtering. */ |
470 | break; |
471 | case 0x144: |
472 | s->tfwr = value & 3; |
473 | break; |
474 | case 0x14c: |
475 | /* FRBR writes ignored. */ |
476 | break; |
477 | case 0x150: |
478 | s->rfsr = (value & 0x3fc) | 0x400; |
479 | break; |
480 | case 0x180: |
481 | s->erdsr = value & ~3; |
482 | s->rx_descriptor = s->erdsr; |
483 | break; |
484 | case 0x184: |
485 | s->etdsr = value & ~3; |
486 | s->tx_descriptor = s->etdsr; |
487 | break; |
488 | case 0x188: |
489 | s->emrbr = value > 0 ? value & 0x7F0 : 0x7F0; |
490 | break; |
491 | case 0x200 ... 0x2e0: |
492 | s->mib[(addr & 0x1ff) / 4] = value; |
493 | break; |
494 | default: |
495 | hw_error("mcf_fec_write Bad address 0x%x\n" , (int)addr); |
496 | } |
497 | mcf_fec_update(s); |
498 | } |
499 | |
500 | static void mcf_fec_rx_stats(mcf_fec_state *s, int size) |
501 | { |
502 | s->mib[MIB_RMON_R_PACKETS]++; |
503 | s->mib[MIB_RMON_R_OCTETS] += size; |
504 | if (size < 64) { |
505 | s->mib[MIB_RMON_R_FRAG]++; |
506 | } else if (size == 64) { |
507 | s->mib[MIB_RMON_R_P64]++; |
508 | } else if (size < 128) { |
509 | s->mib[MIB_RMON_R_P65TO127]++; |
510 | } else if (size < 256) { |
511 | s->mib[MIB_RMON_R_P128TO255]++; |
512 | } else if (size < 512) { |
513 | s->mib[MIB_RMON_R_P256TO511]++; |
514 | } else if (size < 1024) { |
515 | s->mib[MIB_RMON_R_P512TO1023]++; |
516 | } else if (size < 2048) { |
517 | s->mib[MIB_RMON_R_P1024TO2047]++; |
518 | } else { |
519 | s->mib[MIB_RMON_R_P_GTE2048]++; |
520 | } |
521 | s->mib[MIB_IEEE_R_FRAME_OK]++; |
522 | s->mib[MIB_IEEE_R_OCTETS_OK] += size; |
523 | } |
524 | |
525 | static int mcf_fec_have_receive_space(mcf_fec_state *s, size_t want) |
526 | { |
527 | mcf_fec_bd bd; |
528 | uint32_t addr; |
529 | |
530 | /* Walk descriptor list to determine if we have enough buffer */ |
531 | addr = s->rx_descriptor; |
532 | while (want > 0) { |
533 | mcf_fec_read_bd(&bd, addr); |
534 | if ((bd.flags & FEC_BD_E) == 0) { |
535 | return 0; |
536 | } |
537 | if (want < s->emrbr) { |
538 | return 1; |
539 | } |
540 | want -= s->emrbr; |
541 | /* Advance to the next descriptor. */ |
542 | if ((bd.flags & FEC_BD_W) != 0) { |
543 | addr = s->erdsr; |
544 | } else { |
545 | addr += 8; |
546 | } |
547 | } |
548 | return 0; |
549 | } |
550 | |
551 | static ssize_t mcf_fec_receive(NetClientState *nc, const uint8_t *buf, size_t size) |
552 | { |
553 | mcf_fec_state *s = qemu_get_nic_opaque(nc); |
554 | mcf_fec_bd bd; |
555 | uint32_t flags = 0; |
556 | uint32_t addr; |
557 | uint32_t crc; |
558 | uint32_t buf_addr; |
559 | uint8_t *crc_ptr; |
560 | unsigned int buf_len; |
561 | size_t retsize; |
562 | |
563 | DPRINTF("do_rx len %d\n" , size); |
564 | if (!s->rx_enabled) { |
565 | return -1; |
566 | } |
567 | /* 4 bytes for the CRC. */ |
568 | size += 4; |
569 | crc = cpu_to_be32(crc32(~0, buf, size)); |
570 | crc_ptr = (uint8_t *)&crc; |
571 | /* Huge frames are truncted. */ |
572 | if (size > FEC_MAX_FRAME_SIZE) { |
573 | size = FEC_MAX_FRAME_SIZE; |
574 | flags |= FEC_BD_TR | FEC_BD_LG; |
575 | } |
576 | /* Frames larger than the user limit just set error flags. */ |
577 | if (size > (s->rcr >> 16)) { |
578 | flags |= FEC_BD_LG; |
579 | } |
580 | /* Check if we have enough space in current descriptors */ |
581 | if (!mcf_fec_have_receive_space(s, size)) { |
582 | return 0; |
583 | } |
584 | addr = s->rx_descriptor; |
585 | retsize = size; |
586 | while (size > 0) { |
587 | mcf_fec_read_bd(&bd, addr); |
588 | buf_len = (size <= s->emrbr) ? size: s->emrbr; |
589 | bd.length = buf_len; |
590 | size -= buf_len; |
591 | DPRINTF("rx_bd %x length %d\n" , addr, bd.length); |
592 | /* The last 4 bytes are the CRC. */ |
593 | if (size < 4) |
594 | buf_len += size - 4; |
595 | buf_addr = bd.data; |
596 | cpu_physical_memory_write(buf_addr, buf, buf_len); |
597 | buf += buf_len; |
598 | if (size < 4) { |
599 | cpu_physical_memory_write(buf_addr + buf_len, crc_ptr, 4 - size); |
600 | crc_ptr += 4 - size; |
601 | } |
602 | bd.flags &= ~FEC_BD_E; |
603 | if (size == 0) { |
604 | /* Last buffer in frame. */ |
605 | bd.flags |= flags | FEC_BD_L; |
606 | DPRINTF("rx frame flags %04x\n" , bd.flags); |
607 | s->eir |= FEC_INT_RXF; |
608 | } else { |
609 | s->eir |= FEC_INT_RXB; |
610 | } |
611 | mcf_fec_write_bd(&bd, addr); |
612 | /* Advance to the next descriptor. */ |
613 | if ((bd.flags & FEC_BD_W) != 0) { |
614 | addr = s->erdsr; |
615 | } else { |
616 | addr += 8; |
617 | } |
618 | } |
619 | s->rx_descriptor = addr; |
620 | mcf_fec_rx_stats(s, retsize); |
621 | mcf_fec_enable_rx(s); |
622 | mcf_fec_update(s); |
623 | return retsize; |
624 | } |
625 | |
626 | static const MemoryRegionOps mcf_fec_ops = { |
627 | .read = mcf_fec_read, |
628 | .write = mcf_fec_write, |
629 | .endianness = DEVICE_NATIVE_ENDIAN, |
630 | }; |
631 | |
632 | static NetClientInfo net_mcf_fec_info = { |
633 | .type = NET_CLIENT_DRIVER_NIC, |
634 | .size = sizeof(NICState), |
635 | .receive = mcf_fec_receive, |
636 | }; |
637 | |
638 | static void mcf_fec_realize(DeviceState *dev, Error **errp) |
639 | { |
640 | mcf_fec_state *s = MCF_FEC_NET(dev); |
641 | |
642 | s->nic = qemu_new_nic(&net_mcf_fec_info, &s->conf, |
643 | object_get_typename(OBJECT(dev)), dev->id, s); |
644 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
645 | } |
646 | |
647 | static void mcf_fec_instance_init(Object *obj) |
648 | { |
649 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
650 | mcf_fec_state *s = MCF_FEC_NET(obj); |
651 | int i; |
652 | |
653 | memory_region_init_io(&s->iomem, obj, &mcf_fec_ops, s, "fec" , 0x400); |
654 | sysbus_init_mmio(sbd, &s->iomem); |
655 | for (i = 0; i < FEC_NUM_IRQ; i++) { |
656 | sysbus_init_irq(sbd, &s->irq[i]); |
657 | } |
658 | } |
659 | |
660 | static Property mcf_fec_properties[] = { |
661 | DEFINE_NIC_PROPERTIES(mcf_fec_state, conf), |
662 | DEFINE_PROP_END_OF_LIST(), |
663 | }; |
664 | |
665 | static void mcf_fec_class_init(ObjectClass *oc, void *data) |
666 | { |
667 | DeviceClass *dc = DEVICE_CLASS(oc); |
668 | |
669 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
670 | dc->realize = mcf_fec_realize; |
671 | dc->desc = "MCF Fast Ethernet Controller network device" ; |
672 | dc->reset = mcf_fec_reset; |
673 | dc->props = mcf_fec_properties; |
674 | } |
675 | |
676 | static const TypeInfo mcf_fec_info = { |
677 | .name = TYPE_MCF_FEC_NET, |
678 | .parent = TYPE_SYS_BUS_DEVICE, |
679 | .instance_size = sizeof(mcf_fec_state), |
680 | .instance_init = mcf_fec_instance_init, |
681 | .class_init = mcf_fec_class_init, |
682 | }; |
683 | |
684 | static void mcf_fec_register_types(void) |
685 | { |
686 | type_register_static(&mcf_fec_info); |
687 | } |
688 | |
689 | type_init(mcf_fec_register_types) |
690 | |