1 | /* |
2 | * QEMU model of the Milkymist minimac2 block. |
3 | * |
4 | * Copyright (c) 2011 Michael Walle <michael@walle.cc> |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | * |
19 | * |
20 | * Specification available at: |
21 | * not available yet |
22 | * |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qapi/error.h" |
27 | #include "cpu.h" /* FIXME: why does this use TARGET_PAGE_ALIGN? */ |
28 | #include "hw/irq.h" |
29 | #include "hw/qdev-properties.h" |
30 | #include "hw/sysbus.h" |
31 | #include "migration/vmstate.h" |
32 | #include "trace.h" |
33 | #include "net/net.h" |
34 | #include "qemu/log.h" |
35 | #include "qemu/module.h" |
36 | #include "qemu/error-report.h" |
37 | |
38 | #include <zlib.h> |
39 | |
40 | enum { |
41 | R_SETUP = 0, |
42 | R_MDIO, |
43 | R_STATE0, |
44 | R_COUNT0, |
45 | R_STATE1, |
46 | R_COUNT1, |
47 | R_TXCOUNT, |
48 | R_MAX |
49 | }; |
50 | |
51 | enum { |
52 | SETUP_PHY_RST = (1<<0), |
53 | }; |
54 | |
55 | enum { |
56 | MDIO_DO = (1<<0), |
57 | MDIO_DI = (1<<1), |
58 | MDIO_OE = (1<<2), |
59 | MDIO_CLK = (1<<3), |
60 | }; |
61 | |
62 | enum { |
63 | STATE_EMPTY = 0, |
64 | STATE_LOADED = 1, |
65 | STATE_PENDING = 2, |
66 | }; |
67 | |
68 | enum { |
69 | MDIO_OP_WRITE = 1, |
70 | MDIO_OP_READ = 2, |
71 | }; |
72 | |
73 | enum mdio_state { |
74 | MDIO_STATE_IDLE, |
75 | MDIO_STATE_READING, |
76 | MDIO_STATE_WRITING, |
77 | }; |
78 | |
79 | enum { |
80 | R_PHY_ID1 = 2, |
81 | R_PHY_ID2 = 3, |
82 | R_PHY_MAX = 32 |
83 | }; |
84 | |
85 | #define MINIMAC2_MTU 1530 |
86 | #define MINIMAC2_BUFFER_SIZE 2048 |
87 | |
88 | struct MilkymistMinimac2MdioState { |
89 | int last_clk; |
90 | int count; |
91 | uint32_t data; |
92 | uint16_t data_out; |
93 | int state; |
94 | |
95 | uint8_t phy_addr; |
96 | uint8_t reg_addr; |
97 | }; |
98 | typedef struct MilkymistMinimac2MdioState MilkymistMinimac2MdioState; |
99 | |
100 | #define TYPE_MILKYMIST_MINIMAC2 "milkymist-minimac2" |
101 | #define MILKYMIST_MINIMAC2(obj) \ |
102 | OBJECT_CHECK(MilkymistMinimac2State, (obj), TYPE_MILKYMIST_MINIMAC2) |
103 | |
104 | struct MilkymistMinimac2State { |
105 | SysBusDevice parent_obj; |
106 | |
107 | NICState *nic; |
108 | NICConf conf; |
109 | char *phy_model; |
110 | MemoryRegion buffers; |
111 | MemoryRegion regs_region; |
112 | |
113 | qemu_irq rx_irq; |
114 | qemu_irq tx_irq; |
115 | |
116 | uint32_t regs[R_MAX]; |
117 | |
118 | MilkymistMinimac2MdioState mdio; |
119 | |
120 | uint16_t phy_regs[R_PHY_MAX]; |
121 | |
122 | uint8_t *rx0_buf; |
123 | uint8_t *rx1_buf; |
124 | uint8_t *tx_buf; |
125 | }; |
126 | typedef struct MilkymistMinimac2State MilkymistMinimac2State; |
127 | |
128 | static const uint8_t preamble_sfd[] = { |
129 | 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0xd5 |
130 | }; |
131 | |
132 | static void minimac2_mdio_write_reg(MilkymistMinimac2State *s, |
133 | uint8_t phy_addr, uint8_t reg_addr, uint16_t value) |
134 | { |
135 | trace_milkymist_minimac2_mdio_write(phy_addr, reg_addr, value); |
136 | |
137 | /* nop */ |
138 | } |
139 | |
140 | static uint16_t minimac2_mdio_read_reg(MilkymistMinimac2State *s, |
141 | uint8_t phy_addr, uint8_t reg_addr) |
142 | { |
143 | uint16_t r = s->phy_regs[reg_addr]; |
144 | |
145 | trace_milkymist_minimac2_mdio_read(phy_addr, reg_addr, r); |
146 | |
147 | return r; |
148 | } |
149 | |
150 | static void minimac2_update_mdio(MilkymistMinimac2State *s) |
151 | { |
152 | MilkymistMinimac2MdioState *m = &s->mdio; |
153 | |
154 | /* detect rising clk edge */ |
155 | if (m->last_clk == 0 && (s->regs[R_MDIO] & MDIO_CLK)) { |
156 | /* shift data in */ |
157 | int bit = ((s->regs[R_MDIO] & MDIO_DO) |
158 | && (s->regs[R_MDIO] & MDIO_OE)) ? 1 : 0; |
159 | m->data = (m->data << 1) | bit; |
160 | |
161 | /* check for sync */ |
162 | if (m->data == 0xffffffff) { |
163 | m->count = 32; |
164 | } |
165 | |
166 | if (m->count == 16) { |
167 | uint8_t start = (m->data >> 14) & 0x3; |
168 | uint8_t op = (m->data >> 12) & 0x3; |
169 | uint8_t ta = (m->data) & 0x3; |
170 | |
171 | if (start == 1 && op == MDIO_OP_WRITE && ta == 2) { |
172 | m->state = MDIO_STATE_WRITING; |
173 | } else if (start == 1 && op == MDIO_OP_READ && (ta & 1) == 0) { |
174 | m->state = MDIO_STATE_READING; |
175 | } else { |
176 | m->state = MDIO_STATE_IDLE; |
177 | } |
178 | |
179 | if (m->state != MDIO_STATE_IDLE) { |
180 | m->phy_addr = (m->data >> 7) & 0x1f; |
181 | m->reg_addr = (m->data >> 2) & 0x1f; |
182 | } |
183 | |
184 | if (m->state == MDIO_STATE_READING) { |
185 | m->data_out = minimac2_mdio_read_reg(s, m->phy_addr, |
186 | m->reg_addr); |
187 | } |
188 | } |
189 | |
190 | if (m->count < 16 && m->state == MDIO_STATE_READING) { |
191 | int bit = (m->data_out & 0x8000) ? 1 : 0; |
192 | m->data_out <<= 1; |
193 | |
194 | if (bit) { |
195 | s->regs[R_MDIO] |= MDIO_DI; |
196 | } else { |
197 | s->regs[R_MDIO] &= ~MDIO_DI; |
198 | } |
199 | } |
200 | |
201 | if (m->count == 0 && m->state) { |
202 | if (m->state == MDIO_STATE_WRITING) { |
203 | uint16_t data = m->data & 0xffff; |
204 | minimac2_mdio_write_reg(s, m->phy_addr, m->reg_addr, data); |
205 | } |
206 | m->state = MDIO_STATE_IDLE; |
207 | } |
208 | m->count--; |
209 | } |
210 | |
211 | m->last_clk = (s->regs[R_MDIO] & MDIO_CLK) ? 1 : 0; |
212 | } |
213 | |
214 | static size_t assemble_frame(uint8_t *buf, size_t size, |
215 | const uint8_t *payload, size_t payload_size) |
216 | { |
217 | uint32_t crc; |
218 | |
219 | if (size < payload_size + 12) { |
220 | qemu_log_mask(LOG_GUEST_ERROR, "milkymist_minimac2: frame too big " |
221 | "(%zd bytes)\n" , payload_size); |
222 | return 0; |
223 | } |
224 | |
225 | /* prepend preamble and sfd */ |
226 | memcpy(buf, preamble_sfd, 8); |
227 | |
228 | /* now copy the payload */ |
229 | memcpy(buf + 8, payload, payload_size); |
230 | |
231 | /* pad frame if needed */ |
232 | if (payload_size < 60) { |
233 | memset(buf + payload_size + 8, 0, 60 - payload_size); |
234 | payload_size = 60; |
235 | } |
236 | |
237 | /* append fcs */ |
238 | crc = cpu_to_le32(crc32(0, buf + 8, payload_size)); |
239 | memcpy(buf + payload_size + 8, &crc, 4); |
240 | |
241 | return payload_size + 12; |
242 | } |
243 | |
244 | static void minimac2_tx(MilkymistMinimac2State *s) |
245 | { |
246 | uint32_t txcount = s->regs[R_TXCOUNT]; |
247 | uint8_t *buf = s->tx_buf; |
248 | |
249 | if (txcount < 64) { |
250 | error_report("milkymist_minimac2: ethernet frame too small (%u < %u)" , |
251 | txcount, 64); |
252 | goto err; |
253 | } |
254 | |
255 | if (txcount > MINIMAC2_MTU) { |
256 | error_report("milkymist_minimac2: MTU exceeded (%u > %u)" , |
257 | txcount, MINIMAC2_MTU); |
258 | goto err; |
259 | } |
260 | |
261 | if (memcmp(buf, preamble_sfd, 8) != 0) { |
262 | error_report("milkymist_minimac2: frame doesn't contain the preamble " |
263 | "and/or the SFD (%02x %02x %02x %02x %02x %02x %02x %02x)" , |
264 | buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6], buf[7]); |
265 | goto err; |
266 | } |
267 | |
268 | trace_milkymist_minimac2_tx_frame(txcount - 12); |
269 | |
270 | /* send packet, skipping preamble and sfd */ |
271 | qemu_send_packet_raw(qemu_get_queue(s->nic), buf + 8, txcount - 12); |
272 | |
273 | s->regs[R_TXCOUNT] = 0; |
274 | |
275 | err: |
276 | trace_milkymist_minimac2_pulse_irq_tx(); |
277 | qemu_irq_pulse(s->tx_irq); |
278 | } |
279 | |
280 | static void update_rx_interrupt(MilkymistMinimac2State *s) |
281 | { |
282 | if (s->regs[R_STATE0] == STATE_PENDING |
283 | || s->regs[R_STATE1] == STATE_PENDING) { |
284 | trace_milkymist_minimac2_raise_irq_rx(); |
285 | qemu_irq_raise(s->rx_irq); |
286 | } else { |
287 | trace_milkymist_minimac2_lower_irq_rx(); |
288 | qemu_irq_lower(s->rx_irq); |
289 | } |
290 | } |
291 | |
292 | static ssize_t minimac2_rx(NetClientState *nc, const uint8_t *buf, size_t size) |
293 | { |
294 | MilkymistMinimac2State *s = qemu_get_nic_opaque(nc); |
295 | |
296 | uint32_t r_count; |
297 | uint32_t r_state; |
298 | uint8_t *rx_buf; |
299 | |
300 | size_t frame_size; |
301 | |
302 | trace_milkymist_minimac2_rx_frame(buf, size); |
303 | |
304 | /* choose appropriate slot */ |
305 | if (s->regs[R_STATE0] == STATE_LOADED) { |
306 | r_count = R_COUNT0; |
307 | r_state = R_STATE0; |
308 | rx_buf = s->rx0_buf; |
309 | } else if (s->regs[R_STATE1] == STATE_LOADED) { |
310 | r_count = R_COUNT1; |
311 | r_state = R_STATE1; |
312 | rx_buf = s->rx1_buf; |
313 | } else { |
314 | return 0; |
315 | } |
316 | |
317 | /* assemble frame */ |
318 | frame_size = assemble_frame(rx_buf, MINIMAC2_BUFFER_SIZE, buf, size); |
319 | |
320 | if (frame_size == 0) { |
321 | return size; |
322 | } |
323 | |
324 | trace_milkymist_minimac2_rx_transfer(rx_buf, frame_size); |
325 | |
326 | /* update slot */ |
327 | s->regs[r_count] = frame_size; |
328 | s->regs[r_state] = STATE_PENDING; |
329 | |
330 | update_rx_interrupt(s); |
331 | |
332 | return size; |
333 | } |
334 | |
335 | static uint64_t |
336 | minimac2_read(void *opaque, hwaddr addr, unsigned size) |
337 | { |
338 | MilkymistMinimac2State *s = opaque; |
339 | uint32_t r = 0; |
340 | |
341 | addr >>= 2; |
342 | switch (addr) { |
343 | case R_SETUP: |
344 | case R_MDIO: |
345 | case R_STATE0: |
346 | case R_COUNT0: |
347 | case R_STATE1: |
348 | case R_COUNT1: |
349 | case R_TXCOUNT: |
350 | r = s->regs[addr]; |
351 | break; |
352 | |
353 | default: |
354 | qemu_log_mask(LOG_GUEST_ERROR, |
355 | "milkymist_minimac2_rd%d: 0x%" HWADDR_PRIx "\n" , |
356 | size, addr << 2); |
357 | break; |
358 | } |
359 | |
360 | trace_milkymist_minimac2_memory_read(addr << 2, r); |
361 | |
362 | return r; |
363 | } |
364 | |
365 | static int minimac2_can_rx(MilkymistMinimac2State *s) |
366 | { |
367 | if (s->regs[R_STATE0] == STATE_LOADED) { |
368 | return 1; |
369 | } |
370 | if (s->regs[R_STATE1] == STATE_LOADED) { |
371 | return 1; |
372 | } |
373 | |
374 | return 0; |
375 | } |
376 | |
377 | static void |
378 | minimac2_write(void *opaque, hwaddr addr, uint64_t value, |
379 | unsigned size) |
380 | { |
381 | MilkymistMinimac2State *s = opaque; |
382 | |
383 | trace_milkymist_minimac2_memory_write(addr, value); |
384 | |
385 | addr >>= 2; |
386 | switch (addr) { |
387 | case R_MDIO: |
388 | { |
389 | /* MDIO_DI is read only */ |
390 | int mdio_di = (s->regs[R_MDIO] & MDIO_DI); |
391 | s->regs[R_MDIO] = value; |
392 | if (mdio_di) { |
393 | s->regs[R_MDIO] |= mdio_di; |
394 | } else { |
395 | s->regs[R_MDIO] &= ~mdio_di; |
396 | } |
397 | |
398 | minimac2_update_mdio(s); |
399 | } break; |
400 | case R_TXCOUNT: |
401 | s->regs[addr] = value; |
402 | if (value > 0) { |
403 | minimac2_tx(s); |
404 | } |
405 | break; |
406 | case R_STATE0: |
407 | case R_STATE1: |
408 | s->regs[addr] = value; |
409 | update_rx_interrupt(s); |
410 | if (minimac2_can_rx(s)) { |
411 | qemu_flush_queued_packets(qemu_get_queue(s->nic)); |
412 | } |
413 | break; |
414 | case R_SETUP: |
415 | case R_COUNT0: |
416 | case R_COUNT1: |
417 | s->regs[addr] = value; |
418 | break; |
419 | |
420 | default: |
421 | qemu_log_mask(LOG_GUEST_ERROR, |
422 | "milkymist_minimac2_wr%d: 0x%" HWADDR_PRIx |
423 | " = 0x%" PRIx64 "\n" , |
424 | size, addr << 2, value); |
425 | break; |
426 | } |
427 | } |
428 | |
429 | static const MemoryRegionOps minimac2_ops = { |
430 | .read = minimac2_read, |
431 | .write = minimac2_write, |
432 | .valid = { |
433 | .min_access_size = 4, |
434 | .max_access_size = 4, |
435 | }, |
436 | .endianness = DEVICE_NATIVE_ENDIAN, |
437 | }; |
438 | |
439 | static void milkymist_minimac2_reset(DeviceState *d) |
440 | { |
441 | MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(d); |
442 | int i; |
443 | |
444 | for (i = 0; i < R_MAX; i++) { |
445 | s->regs[i] = 0; |
446 | } |
447 | for (i = 0; i < R_PHY_MAX; i++) { |
448 | s->phy_regs[i] = 0; |
449 | } |
450 | |
451 | /* defaults */ |
452 | s->phy_regs[R_PHY_ID1] = 0x0022; /* Micrel KSZ8001L */ |
453 | s->phy_regs[R_PHY_ID2] = 0x161a; |
454 | } |
455 | |
456 | static NetClientInfo net_milkymist_minimac2_info = { |
457 | .type = NET_CLIENT_DRIVER_NIC, |
458 | .size = sizeof(NICState), |
459 | .receive = minimac2_rx, |
460 | }; |
461 | |
462 | static void milkymist_minimac2_realize(DeviceState *dev, Error **errp) |
463 | { |
464 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
465 | MilkymistMinimac2State *s = MILKYMIST_MINIMAC2(dev); |
466 | size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE); |
467 | |
468 | sysbus_init_irq(sbd, &s->rx_irq); |
469 | sysbus_init_irq(sbd, &s->tx_irq); |
470 | |
471 | memory_region_init_io(&s->regs_region, OBJECT(dev), &minimac2_ops, s, |
472 | "milkymist-minimac2" , R_MAX * 4); |
473 | sysbus_init_mmio(sbd, &s->regs_region); |
474 | |
475 | /* register buffers memory */ |
476 | memory_region_init_ram_nomigrate(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers" , |
477 | buffers_size, &error_fatal); |
478 | vmstate_register_ram_global(&s->buffers); |
479 | s->rx0_buf = memory_region_get_ram_ptr(&s->buffers); |
480 | s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE; |
481 | s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE; |
482 | |
483 | sysbus_init_mmio(sbd, &s->buffers); |
484 | |
485 | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
486 | s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf, |
487 | object_get_typename(OBJECT(dev)), dev->id, s); |
488 | qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); |
489 | } |
490 | |
491 | static const VMStateDescription vmstate_milkymist_minimac2_mdio = { |
492 | .name = "milkymist-minimac2-mdio" , |
493 | .version_id = 1, |
494 | .minimum_version_id = 1, |
495 | .fields = (VMStateField[]) { |
496 | VMSTATE_INT32(last_clk, MilkymistMinimac2MdioState), |
497 | VMSTATE_INT32(count, MilkymistMinimac2MdioState), |
498 | VMSTATE_UINT32(data, MilkymistMinimac2MdioState), |
499 | VMSTATE_UINT16(data_out, MilkymistMinimac2MdioState), |
500 | VMSTATE_INT32(state, MilkymistMinimac2MdioState), |
501 | VMSTATE_UINT8(phy_addr, MilkymistMinimac2MdioState), |
502 | VMSTATE_UINT8(reg_addr, MilkymistMinimac2MdioState), |
503 | VMSTATE_END_OF_LIST() |
504 | } |
505 | }; |
506 | |
507 | static const VMStateDescription vmstate_milkymist_minimac2 = { |
508 | .name = "milkymist-minimac2" , |
509 | .version_id = 1, |
510 | .minimum_version_id = 1, |
511 | .fields = (VMStateField[]) { |
512 | VMSTATE_UINT32_ARRAY(regs, MilkymistMinimac2State, R_MAX), |
513 | VMSTATE_UINT16_ARRAY(phy_regs, MilkymistMinimac2State, R_PHY_MAX), |
514 | VMSTATE_STRUCT(mdio, MilkymistMinimac2State, 0, |
515 | vmstate_milkymist_minimac2_mdio, MilkymistMinimac2MdioState), |
516 | VMSTATE_END_OF_LIST() |
517 | } |
518 | }; |
519 | |
520 | static Property milkymist_minimac2_properties[] = { |
521 | DEFINE_NIC_PROPERTIES(MilkymistMinimac2State, conf), |
522 | DEFINE_PROP_STRING("phy_model" , MilkymistMinimac2State, phy_model), |
523 | DEFINE_PROP_END_OF_LIST(), |
524 | }; |
525 | |
526 | static void milkymist_minimac2_class_init(ObjectClass *klass, void *data) |
527 | { |
528 | DeviceClass *dc = DEVICE_CLASS(klass); |
529 | |
530 | dc->realize = milkymist_minimac2_realize; |
531 | dc->reset = milkymist_minimac2_reset; |
532 | dc->vmsd = &vmstate_milkymist_minimac2; |
533 | dc->props = milkymist_minimac2_properties; |
534 | } |
535 | |
536 | static const TypeInfo milkymist_minimac2_info = { |
537 | .name = TYPE_MILKYMIST_MINIMAC2, |
538 | .parent = TYPE_SYS_BUS_DEVICE, |
539 | .instance_size = sizeof(MilkymistMinimac2State), |
540 | .class_init = milkymist_minimac2_class_init, |
541 | }; |
542 | |
543 | static void milkymist_minimac2_register_types(void) |
544 | { |
545 | type_register_static(&milkymist_minimac2_info); |
546 | } |
547 | |
548 | type_init(milkymist_minimac2_register_types) |
549 | |