1/*
2 * QEMU model of XGMAC Ethernet.
3 *
4 * derived from the Xilinx AXI-Ethernet by Edgar E. Iglesias.
5 *
6 * Copyright (c) 2011 Calxeda, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27#include "qemu/osdep.h"
28#include "hw/irq.h"
29#include "hw/qdev-properties.h"
30#include "hw/sysbus.h"
31#include "migration/vmstate.h"
32#include "qemu/log.h"
33#include "qemu/module.h"
34#include "net/net.h"
35
36#ifdef DEBUG_XGMAC
37#define DEBUGF_BRK(message, args...) do { \
38 fprintf(stderr, (message), ## args); \
39 } while (0)
40#else
41#define DEBUGF_BRK(message, args...) do { } while (0)
42#endif
43
44#define XGMAC_CONTROL 0x00000000 /* MAC Configuration */
45#define XGMAC_FRAME_FILTER 0x00000001 /* MAC Frame Filter */
46#define XGMAC_FLOW_CTRL 0x00000006 /* MAC Flow Control */
47#define XGMAC_VLAN_TAG 0x00000007 /* VLAN Tags */
48#define XGMAC_VERSION 0x00000008 /* Version */
49/* VLAN tag for insertion or replacement into tx frames */
50#define XGMAC_VLAN_INCL 0x00000009
51#define XGMAC_LPI_CTRL 0x0000000a /* LPI Control and Status */
52#define XGMAC_LPI_TIMER 0x0000000b /* LPI Timers Control */
53#define XGMAC_TX_PACE 0x0000000c /* Transmit Pace and Stretch */
54#define XGMAC_VLAN_HASH 0x0000000d /* VLAN Hash Table */
55#define XGMAC_DEBUG 0x0000000e /* Debug */
56#define XGMAC_INT_STATUS 0x0000000f /* Interrupt and Control */
57/* HASH table registers */
58#define XGMAC_HASH(n) ((0x00000300/4) + (n))
59#define XGMAC_NUM_HASH 16
60/* Operation Mode */
61#define XGMAC_OPMODE (0x00000400/4)
62/* Remote Wake-Up Frame Filter */
63#define XGMAC_REMOTE_WAKE (0x00000700/4)
64/* PMT Control and Status */
65#define XGMAC_PMT (0x00000704/4)
66
67#define XGMAC_ADDR_HIGH(reg) (0x00000010+((reg) * 2))
68#define XGMAC_ADDR_LOW(reg) (0x00000011+((reg) * 2))
69
70#define DMA_BUS_MODE 0x000003c0 /* Bus Mode */
71#define DMA_XMT_POLL_DEMAND 0x000003c1 /* Transmit Poll Demand */
72#define DMA_RCV_POLL_DEMAND 0x000003c2 /* Received Poll Demand */
73#define DMA_RCV_BASE_ADDR 0x000003c3 /* Receive List Base */
74#define DMA_TX_BASE_ADDR 0x000003c4 /* Transmit List Base */
75#define DMA_STATUS 0x000003c5 /* Status Register */
76#define DMA_CONTROL 0x000003c6 /* Ctrl (Operational Mode) */
77#define DMA_INTR_ENA 0x000003c7 /* Interrupt Enable */
78#define DMA_MISSED_FRAME_CTR 0x000003c8 /* Missed Frame Counter */
79/* Receive Interrupt Watchdog Timer */
80#define DMA_RI_WATCHDOG_TIMER 0x000003c9
81#define DMA_AXI_BUS 0x000003ca /* AXI Bus Mode */
82#define DMA_AXI_STATUS 0x000003cb /* AXI Status */
83#define DMA_CUR_TX_DESC_ADDR 0x000003d2 /* Current Host Tx Descriptor */
84#define DMA_CUR_RX_DESC_ADDR 0x000003d3 /* Current Host Rx Descriptor */
85#define DMA_CUR_TX_BUF_ADDR 0x000003d4 /* Current Host Tx Buffer */
86#define DMA_CUR_RX_BUF_ADDR 0x000003d5 /* Current Host Rx Buffer */
87#define DMA_HW_FEATURE 0x000003d6 /* Enabled Hardware Features */
88
89/* DMA Status register defines */
90#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
91#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
92#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
93#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
94#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
95#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
96#define DMA_STATUS_TS_SHIFT 20
97#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
98#define DMA_STATUS_RS_SHIFT 17
99#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
100#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
101#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
102#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
103#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
104#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
105#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
106#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
107#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
108#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
109#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
110#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
111#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
112#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
113#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
114
115/* DMA Control register defines */
116#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
117#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
118#define DMA_CONTROL_DFF 0x01000000 /* Disable flush of rx frames */
119
120struct desc {
121 uint32_t ctl_stat;
122 uint16_t buffer1_size;
123 uint16_t buffer2_size;
124 uint32_t buffer1_addr;
125 uint32_t buffer2_addr;
126 uint32_t ext_stat;
127 uint32_t res[3];
128};
129
130#define R_MAX 0x400
131
132typedef struct RxTxStats {
133 uint64_t rx_bytes;
134 uint64_t tx_bytes;
135
136 uint64_t rx;
137 uint64_t rx_bcast;
138 uint64_t rx_mcast;
139} RxTxStats;
140
141#define TYPE_XGMAC "xgmac"
142#define XGMAC(obj) OBJECT_CHECK(XgmacState, (obj), TYPE_XGMAC)
143
144typedef struct XgmacState {
145 SysBusDevice parent_obj;
146
147 MemoryRegion iomem;
148 qemu_irq sbd_irq;
149 qemu_irq pmt_irq;
150 qemu_irq mci_irq;
151 NICState *nic;
152 NICConf conf;
153
154 struct RxTxStats stats;
155 uint32_t regs[R_MAX];
156} XgmacState;
157
158static const VMStateDescription vmstate_rxtx_stats = {
159 .name = "xgmac_stats",
160 .version_id = 1,
161 .minimum_version_id = 1,
162 .fields = (VMStateField[]) {
163 VMSTATE_UINT64(rx_bytes, RxTxStats),
164 VMSTATE_UINT64(tx_bytes, RxTxStats),
165 VMSTATE_UINT64(rx, RxTxStats),
166 VMSTATE_UINT64(rx_bcast, RxTxStats),
167 VMSTATE_UINT64(rx_mcast, RxTxStats),
168 VMSTATE_END_OF_LIST()
169 }
170};
171
172static const VMStateDescription vmstate_xgmac = {
173 .name = "xgmac",
174 .version_id = 1,
175 .minimum_version_id = 1,
176 .fields = (VMStateField[]) {
177 VMSTATE_STRUCT(stats, XgmacState, 0, vmstate_rxtx_stats, RxTxStats),
178 VMSTATE_UINT32_ARRAY(regs, XgmacState, R_MAX),
179 VMSTATE_END_OF_LIST()
180 }
181};
182
183static void xgmac_read_desc(XgmacState *s, struct desc *d, int rx)
184{
185 uint32_t addr = rx ? s->regs[DMA_CUR_RX_DESC_ADDR] :
186 s->regs[DMA_CUR_TX_DESC_ADDR];
187 cpu_physical_memory_read(addr, d, sizeof(*d));
188}
189
190static void xgmac_write_desc(XgmacState *s, struct desc *d, int rx)
191{
192 int reg = rx ? DMA_CUR_RX_DESC_ADDR : DMA_CUR_TX_DESC_ADDR;
193 uint32_t addr = s->regs[reg];
194
195 if (!rx && (d->ctl_stat & 0x00200000)) {
196 s->regs[reg] = s->regs[DMA_TX_BASE_ADDR];
197 } else if (rx && (d->buffer1_size & 0x8000)) {
198 s->regs[reg] = s->regs[DMA_RCV_BASE_ADDR];
199 } else {
200 s->regs[reg] += sizeof(*d);
201 }
202 cpu_physical_memory_write(addr, d, sizeof(*d));
203}
204
205static void xgmac_enet_send(XgmacState *s)
206{
207 struct desc bd;
208 int frame_size;
209 int len;
210 uint8_t frame[8192];
211 uint8_t *ptr;
212
213 ptr = frame;
214 frame_size = 0;
215 while (1) {
216 xgmac_read_desc(s, &bd, 0);
217 if ((bd.ctl_stat & 0x80000000) == 0) {
218 /* Run out of descriptors to transmit. */
219 break;
220 }
221 len = (bd.buffer1_size & 0xfff) + (bd.buffer2_size & 0xfff);
222
223 if ((bd.buffer1_size & 0xfff) > 2048) {
224 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
225 "xgmac buffer 1 len on send > 2048 (0x%x)\n",
226 __func__, bd.buffer1_size & 0xfff);
227 }
228 if ((bd.buffer2_size & 0xfff) != 0) {
229 DEBUGF_BRK("qemu:%s:ERROR...ERROR...ERROR... -- "
230 "xgmac buffer 2 len on send != 0 (0x%x)\n",
231 __func__, bd.buffer2_size & 0xfff);
232 }
233 if (len >= sizeof(frame)) {
234 DEBUGF_BRK("qemu:%s: buffer overflow %d read into %zu "
235 "buffer\n" , __func__, len, sizeof(frame));
236 DEBUGF_BRK("qemu:%s: buffer1.size=%d; buffer2.size=%d\n",
237 __func__, bd.buffer1_size, bd.buffer2_size);
238 }
239
240 cpu_physical_memory_read(bd.buffer1_addr, ptr, len);
241 ptr += len;
242 frame_size += len;
243 if (bd.ctl_stat & 0x20000000) {
244 /* Last buffer in frame. */
245 qemu_send_packet(qemu_get_queue(s->nic), frame, len);
246 ptr = frame;
247 frame_size = 0;
248 s->regs[DMA_STATUS] |= DMA_STATUS_TI | DMA_STATUS_NIS;
249 }
250 bd.ctl_stat &= ~0x80000000;
251 /* Write back the modified descriptor. */
252 xgmac_write_desc(s, &bd, 0);
253 }
254}
255
256static void enet_update_irq(XgmacState *s)
257{
258 int stat = s->regs[DMA_STATUS] & s->regs[DMA_INTR_ENA];
259 qemu_set_irq(s->sbd_irq, !!stat);
260}
261
262static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
263{
264 XgmacState *s = opaque;
265 uint64_t r = 0;
266 addr >>= 2;
267
268 switch (addr) {
269 case XGMAC_VERSION:
270 r = 0x1012;
271 break;
272 default:
273 if (addr < ARRAY_SIZE(s->regs)) {
274 r = s->regs[addr];
275 }
276 break;
277 }
278 return r;
279}
280
281static void enet_write(void *opaque, hwaddr addr,
282 uint64_t value, unsigned size)
283{
284 XgmacState *s = opaque;
285
286 addr >>= 2;
287 switch (addr) {
288 case DMA_BUS_MODE:
289 s->regs[DMA_BUS_MODE] = value & ~0x1;
290 break;
291 case DMA_XMT_POLL_DEMAND:
292 xgmac_enet_send(s);
293 break;
294 case DMA_STATUS:
295 s->regs[DMA_STATUS] = s->regs[DMA_STATUS] & ~value;
296 break;
297 case DMA_RCV_BASE_ADDR:
298 s->regs[DMA_RCV_BASE_ADDR] = s->regs[DMA_CUR_RX_DESC_ADDR] = value;
299 break;
300 case DMA_TX_BASE_ADDR:
301 s->regs[DMA_TX_BASE_ADDR] = s->regs[DMA_CUR_TX_DESC_ADDR] = value;
302 break;
303 default:
304 if (addr < ARRAY_SIZE(s->regs)) {
305 s->regs[addr] = value;
306 }
307 break;
308 }
309 enet_update_irq(s);
310}
311
312static const MemoryRegionOps enet_mem_ops = {
313 .read = enet_read,
314 .write = enet_write,
315 .endianness = DEVICE_LITTLE_ENDIAN,
316};
317
318static int eth_can_rx(XgmacState *s)
319{
320 /* RX enabled? */
321 return s->regs[DMA_CONTROL] & DMA_CONTROL_SR;
322}
323
324static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
325{
326 XgmacState *s = qemu_get_nic_opaque(nc);
327 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
328 0xff, 0xff, 0xff};
329 int unicast, broadcast, multicast;
330 struct desc bd;
331 ssize_t ret;
332
333 if (!eth_can_rx(s)) {
334 return -1;
335 }
336 unicast = ~buf[0] & 0x1;
337 broadcast = memcmp(buf, sa_bcast, 6) == 0;
338 multicast = !unicast && !broadcast;
339 if (size < 12) {
340 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
341 ret = -1;
342 goto out;
343 }
344
345 xgmac_read_desc(s, &bd, 1);
346 if ((bd.ctl_stat & 0x80000000) == 0) {
347 s->regs[DMA_STATUS] |= DMA_STATUS_RU | DMA_STATUS_AIS;
348 ret = size;
349 goto out;
350 }
351
352 cpu_physical_memory_write(bd.buffer1_addr, buf, size);
353
354 /* Add in the 4 bytes for crc (the real hw returns length incl crc) */
355 size += 4;
356 bd.ctl_stat = (size << 16) | 0x300;
357 xgmac_write_desc(s, &bd, 1);
358
359 s->stats.rx_bytes += size;
360 s->stats.rx++;
361 if (multicast) {
362 s->stats.rx_mcast++;
363 } else if (broadcast) {
364 s->stats.rx_bcast++;
365 }
366
367 s->regs[DMA_STATUS] |= DMA_STATUS_RI | DMA_STATUS_NIS;
368 ret = size;
369
370out:
371 enet_update_irq(s);
372 return ret;
373}
374
375static NetClientInfo net_xgmac_enet_info = {
376 .type = NET_CLIENT_DRIVER_NIC,
377 .size = sizeof(NICState),
378 .receive = eth_rx,
379};
380
381static void xgmac_enet_realize(DeviceState *dev, Error **errp)
382{
383 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
384 XgmacState *s = XGMAC(dev);
385
386 memory_region_init_io(&s->iomem, OBJECT(s), &enet_mem_ops, s,
387 "xgmac", 0x1000);
388 sysbus_init_mmio(sbd, &s->iomem);
389 sysbus_init_irq(sbd, &s->sbd_irq);
390 sysbus_init_irq(sbd, &s->pmt_irq);
391 sysbus_init_irq(sbd, &s->mci_irq);
392
393 qemu_macaddr_default_if_unset(&s->conf.macaddr);
394 s->nic = qemu_new_nic(&net_xgmac_enet_info, &s->conf,
395 object_get_typename(OBJECT(dev)), dev->id, s);
396 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
397
398 s->regs[XGMAC_ADDR_HIGH(0)] = (s->conf.macaddr.a[5] << 8) |
399 s->conf.macaddr.a[4];
400 s->regs[XGMAC_ADDR_LOW(0)] = (s->conf.macaddr.a[3] << 24) |
401 (s->conf.macaddr.a[2] << 16) |
402 (s->conf.macaddr.a[1] << 8) |
403 s->conf.macaddr.a[0];
404}
405
406static Property xgmac_properties[] = {
407 DEFINE_NIC_PROPERTIES(XgmacState, conf),
408 DEFINE_PROP_END_OF_LIST(),
409};
410
411static void xgmac_enet_class_init(ObjectClass *klass, void *data)
412{
413 DeviceClass *dc = DEVICE_CLASS(klass);
414
415 dc->realize = xgmac_enet_realize;
416 dc->vmsd = &vmstate_xgmac;
417 dc->props = xgmac_properties;
418}
419
420static const TypeInfo xgmac_enet_info = {
421 .name = TYPE_XGMAC,
422 .parent = TYPE_SYS_BUS_DEVICE,
423 .instance_size = sizeof(XgmacState),
424 .class_init = xgmac_enet_class_init,
425};
426
427static void xgmac_enet_register_types(void)
428{
429 type_register_static(&xgmac_enet_info);
430}
431
432type_init(xgmac_enet_register_types)
433