1/*
2 * xio3130_upstream.c
3 * TI X3130 pci express upstream port switch
4 *
5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
20 */
21
22#include "qemu/osdep.h"
23#include "hw/pci/pci_ids.h"
24#include "hw/pci/msi.h"
25#include "hw/pci/pcie.h"
26#include "hw/pci/pcie_port.h"
27#include "migration/vmstate.h"
28#include "qemu/module.h"
29
30#define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */
31#define XIO3130_REVISION 0x2
32#define XIO3130_MSI_OFFSET 0x70
33#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
34#define XIO3130_MSI_NR_VECTOR 1
35#define XIO3130_SSVID_OFFSET 0x80
36#define XIO3130_SSVID_SVID 0
37#define XIO3130_SSVID_SSID 0
38#define XIO3130_EXP_OFFSET 0x90
39#define XIO3130_AER_OFFSET 0x100
40
41static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
42 uint32_t val, int len)
43{
44 pci_bridge_write_config(d, address, val, len);
45 pcie_cap_flr_write_config(d, address, val, len);
46 pcie_aer_write_config(d, address, val, len);
47}
48
49static void xio3130_upstream_reset(DeviceState *qdev)
50{
51 PCIDevice *d = PCI_DEVICE(qdev);
52
53 pci_bridge_reset(qdev);
54 pcie_cap_deverr_reset(d);
55}
56
57static void xio3130_upstream_realize(PCIDevice *d, Error **errp)
58{
59 PCIEPort *p = PCIE_PORT(d);
60 int rc;
61
62 pci_bridge_initfn(d, TYPE_PCIE_BUS);
63 pcie_port_init_reg(d);
64
65 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
66 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
67 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
68 errp);
69 if (rc < 0) {
70 assert(rc == -ENOTSUP);
71 goto err_bridge;
72 }
73
74 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
75 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
76 errp);
77 if (rc < 0) {
78 goto err_bridge;
79 }
80
81 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
82 p->port, errp);
83 if (rc < 0) {
84 goto err_msi;
85 }
86 pcie_cap_flr_init(d);
87 pcie_cap_deverr_init(d);
88
89 rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
90 PCI_ERR_SIZEOF, errp);
91 if (rc < 0) {
92 goto err;
93 }
94
95 return;
96
97err:
98 pcie_cap_exit(d);
99err_msi:
100 msi_uninit(d);
101err_bridge:
102 pci_bridge_exitfn(d);
103}
104
105static void xio3130_upstream_exitfn(PCIDevice *d)
106{
107 pcie_aer_exit(d);
108 pcie_cap_exit(d);
109 msi_uninit(d);
110 pci_bridge_exitfn(d);
111}
112
113static const VMStateDescription vmstate_xio3130_upstream = {
114 .name = "xio3130-express-upstream-port",
115 .priority = MIG_PRI_PCI_BUS,
116 .version_id = 1,
117 .minimum_version_id = 1,
118 .fields = (VMStateField[]) {
119 VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort),
120 VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0,
121 vmstate_pcie_aer_log, PCIEAERLog),
122 VMSTATE_END_OF_LIST()
123 }
124};
125
126static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
127{
128 DeviceClass *dc = DEVICE_CLASS(klass);
129 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
130
131 k->is_bridge = true;
132 k->config_write = xio3130_upstream_write_config;
133 k->realize = xio3130_upstream_realize;
134 k->exit = xio3130_upstream_exitfn;
135 k->vendor_id = PCI_VENDOR_ID_TI;
136 k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
137 k->revision = XIO3130_REVISION;
138 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
139 dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
140 dc->reset = xio3130_upstream_reset;
141 dc->vmsd = &vmstate_xio3130_upstream;
142}
143
144static const TypeInfo xio3130_upstream_info = {
145 .name = "x3130-upstream",
146 .parent = TYPE_PCIE_PORT,
147 .class_init = xio3130_upstream_class_init,
148 .interfaces = (InterfaceInfo[]) {
149 { INTERFACE_PCIE_DEVICE },
150 { }
151 },
152};
153
154static void xio3130_upstream_register_types(void)
155{
156 type_register_static(&xio3130_upstream_info);
157}
158
159type_init(xio3130_upstream_register_types)
160