1 | /* |
2 | * QEMU RS/6000 memory controller |
3 | * |
4 | * Copyright (c) 2017 Hervé Poussineau |
5 | * |
6 | * This program is free software: you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License as published by |
8 | * the Free Software Foundation, either version 2 of the License, or |
9 | * (at your option) version 3 or any later version. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License |
17 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #include "qemu/osdep.h" |
21 | #include "qemu/units.h" |
22 | #include "hw/isa/isa.h" |
23 | #include "hw/qdev-properties.h" |
24 | #include "migration/vmstate.h" |
25 | #include "exec/address-spaces.h" |
26 | #include "hw/boards.h" |
27 | #include "qapi/error.h" |
28 | #include "trace.h" |
29 | |
30 | #define TYPE_RS6000MC "rs6000-mc" |
31 | #define RS6000MC_DEVICE(obj) \ |
32 | OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC) |
33 | |
34 | typedef struct RS6000MCState { |
35 | ISADevice parent_obj; |
36 | /* see US patent 5,684,979 for details (expired 2001-11-04) */ |
37 | uint32_t ram_size; |
38 | bool autoconfigure; |
39 | MemoryRegion simm[6]; |
40 | unsigned int simm_size[6]; |
41 | uint32_t end_address[8]; |
42 | uint8_t port0820_index; |
43 | PortioList portio; |
44 | } RS6000MCState; |
45 | |
46 | /* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */ |
47 | |
48 | static uint32_t rs6000mc_port0803_read(void *opaque, uint32_t addr) |
49 | { |
50 | RS6000MCState *s = opaque; |
51 | uint32_t val = 0; |
52 | int socket; |
53 | |
54 | /* (1 << socket) indicates 32 MB SIMM at given socket */ |
55 | for (socket = 0; socket < 6; socket++) { |
56 | if (s->simm_size[socket] == 32) { |
57 | val |= (1 << socket); |
58 | } |
59 | } |
60 | |
61 | trace_rs6000mc_id_read(addr, val); |
62 | return val; |
63 | } |
64 | |
65 | /* PORT 0804 -- SIMM Presence Register (Read Only) */ |
66 | |
67 | static uint32_t rs6000mc_port0804_read(void *opaque, uint32_t addr) |
68 | { |
69 | RS6000MCState *s = opaque; |
70 | uint32_t val = 0xff; |
71 | int socket; |
72 | |
73 | /* (1 << socket) indicates SIMM absence at given socket */ |
74 | for (socket = 0; socket < 6; socket++) { |
75 | if (s->simm_size[socket]) { |
76 | val &= ~(1 << socket); |
77 | } |
78 | } |
79 | s->port0820_index = 0; |
80 | |
81 | trace_rs6000mc_presence_read(addr, val); |
82 | return val; |
83 | } |
84 | |
85 | /* Memory Controller Size Programming Register */ |
86 | |
87 | static uint32_t rs6000mc_port0820_read(void *opaque, uint32_t addr) |
88 | { |
89 | RS6000MCState *s = opaque; |
90 | uint32_t val = s->end_address[s->port0820_index] & 0x1f; |
91 | s->port0820_index = (s->port0820_index + 1) & 7; |
92 | trace_rs6000mc_size_read(addr, val); |
93 | return val; |
94 | } |
95 | |
96 | static void rs6000mc_port0820_write(void *opaque, uint32_t addr, uint32_t val) |
97 | { |
98 | RS6000MCState *s = opaque; |
99 | uint8_t socket = val >> 5; |
100 | uint32_t end_address = val & 0x1f; |
101 | |
102 | trace_rs6000mc_size_write(addr, val); |
103 | s->end_address[socket] = end_address; |
104 | if (socket > 0 && socket < 7) { |
105 | if (s->simm_size[socket - 1]) { |
106 | uint32_t size; |
107 | uint32_t start_address = 0; |
108 | if (socket > 1) { |
109 | start_address = s->end_address[socket - 1]; |
110 | } |
111 | |
112 | size = end_address - start_address; |
113 | memory_region_set_enabled(&s->simm[socket - 1], size != 0); |
114 | memory_region_set_address(&s->simm[socket - 1], |
115 | start_address * 8 * MiB); |
116 | } |
117 | } |
118 | } |
119 | |
120 | /* Read Memory Parity Error */ |
121 | |
122 | enum { |
123 | PORT0841_NO_ERROR_DETECTED = 0x01, |
124 | }; |
125 | |
126 | static uint32_t rs6000mc_port0841_read(void *opaque, uint32_t addr) |
127 | { |
128 | uint32_t val = PORT0841_NO_ERROR_DETECTED; |
129 | trace_rs6000mc_parity_read(addr, val); |
130 | return val; |
131 | } |
132 | |
133 | static const MemoryRegionPortio rs6000mc_port_list[] = { |
134 | { 0x803, 1, 1, .read = rs6000mc_port0803_read }, |
135 | { 0x804, 1, 1, .read = rs6000mc_port0804_read }, |
136 | { 0x820, 1, 1, .read = rs6000mc_port0820_read, |
137 | .write = rs6000mc_port0820_write, }, |
138 | { 0x841, 1, 1, .read = rs6000mc_port0841_read }, |
139 | PORTIO_END_OF_LIST() |
140 | }; |
141 | |
142 | static void rs6000mc_realize(DeviceState *dev, Error **errp) |
143 | { |
144 | RS6000MCState *s = RS6000MC_DEVICE(dev); |
145 | int socket = 0; |
146 | unsigned int ram_size = s->ram_size / MiB; |
147 | |
148 | while (socket < 6) { |
149 | if (ram_size >= 64) { |
150 | s->simm_size[socket] = 32; |
151 | s->simm_size[socket + 1] = 32; |
152 | ram_size -= 64; |
153 | } else if (ram_size >= 16) { |
154 | s->simm_size[socket] = 8; |
155 | s->simm_size[socket + 1] = 8; |
156 | ram_size -= 16; |
157 | } else { |
158 | /* Not enough memory */ |
159 | break; |
160 | } |
161 | socket += 2; |
162 | } |
163 | |
164 | for (socket = 0; socket < 6; socket++) { |
165 | if (s->simm_size[socket]) { |
166 | char name[] = "simm.?" ; |
167 | name[5] = socket + '0'; |
168 | memory_region_allocate_system_memory(&s->simm[socket], OBJECT(dev), |
169 | name, |
170 | s->simm_size[socket] * MiB); |
171 | memory_region_add_subregion_overlap(get_system_memory(), 0, |
172 | &s->simm[socket], socket); |
173 | } |
174 | } |
175 | if (ram_size) { |
176 | /* unable to push all requested RAM in SIMMs */ |
177 | error_setg(errp, "RAM size incompatible with this board. " |
178 | "Try again with something else, like %" PRId64 " MB" , |
179 | s->ram_size / MiB - ram_size); |
180 | return; |
181 | } |
182 | |
183 | if (s->autoconfigure) { |
184 | uint32_t start_address = 0; |
185 | for (socket = 0; socket < 6; socket++) { |
186 | if (s->simm_size[socket]) { |
187 | memory_region_set_enabled(&s->simm[socket], true); |
188 | memory_region_set_address(&s->simm[socket], start_address); |
189 | start_address += memory_region_size(&s->simm[socket]); |
190 | } |
191 | } |
192 | } |
193 | |
194 | isa_register_portio_list(ISA_DEVICE(dev), &s->portio, 0x0, |
195 | rs6000mc_port_list, s, "rs6000mc" ); |
196 | } |
197 | |
198 | static const VMStateDescription vmstate_rs6000mc = { |
199 | .name = "rs6000-mc" , |
200 | .version_id = 1, |
201 | .minimum_version_id = 1, |
202 | .fields = (VMStateField[]) { |
203 | VMSTATE_UINT8(port0820_index, RS6000MCState), |
204 | VMSTATE_END_OF_LIST() |
205 | }, |
206 | }; |
207 | |
208 | static Property rs6000mc_properties[] = { |
209 | DEFINE_PROP_UINT32("ram-size" , RS6000MCState, ram_size, 0), |
210 | DEFINE_PROP_BOOL("auto-configure" , RS6000MCState, autoconfigure, true), |
211 | DEFINE_PROP_END_OF_LIST() |
212 | }; |
213 | |
214 | static void rs6000mc_class_initfn(ObjectClass *klass, void *data) |
215 | { |
216 | DeviceClass *dc = DEVICE_CLASS(klass); |
217 | |
218 | dc->realize = rs6000mc_realize; |
219 | dc->vmsd = &vmstate_rs6000mc; |
220 | dc->props = rs6000mc_properties; |
221 | } |
222 | |
223 | static const TypeInfo rs6000mc_info = { |
224 | .name = TYPE_RS6000MC, |
225 | .parent = TYPE_ISA_DEVICE, |
226 | .instance_size = sizeof(RS6000MCState), |
227 | .class_init = rs6000mc_class_initfn, |
228 | }; |
229 | |
230 | static void rs6000mc_types(void) |
231 | { |
232 | type_register_static(&rs6000mc_info); |
233 | } |
234 | |
235 | type_init(rs6000mc_types) |
236 | |