1/*
2 * QEMU RISCV Hart Array
3 *
4 * Copyright (c) 2017 SiFive, Inc.
5 *
6 * Holds the state of a heterogenous array of RISC-V harts
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "qemu/module.h"
24#include "sysemu/reset.h"
25#include "hw/sysbus.h"
26#include "target/riscv/cpu.h"
27#include "hw/qdev-properties.h"
28#include "hw/riscv/riscv_hart.h"
29
30static Property riscv_harts_props[] = {
31 DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
32 DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type),
33 DEFINE_PROP_END_OF_LIST(),
34};
35
36static void riscv_harts_cpu_reset(void *opaque)
37{
38 RISCVCPU *cpu = opaque;
39 cpu_reset(CPU(cpu));
40}
41
42static void riscv_harts_realize(DeviceState *dev, Error **errp)
43{
44 RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
45 Error *err = NULL;
46 int n;
47
48 s->harts = g_new0(RISCVCPU, s->num_harts);
49
50 for (n = 0; n < s->num_harts; n++) {
51 object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n],
52 sizeof(RISCVCPU), s->cpu_type,
53 &error_abort, NULL);
54 s->harts[n].env.mhartid = n;
55 qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
56 object_property_set_bool(OBJECT(&s->harts[n]), true,
57 "realized", &err);
58 if (err) {
59 error_propagate(errp, err);
60 return;
61 }
62 }
63}
64
65static void riscv_harts_class_init(ObjectClass *klass, void *data)
66{
67 DeviceClass *dc = DEVICE_CLASS(klass);
68
69 dc->props = riscv_harts_props;
70 dc->realize = riscv_harts_realize;
71}
72
73static const TypeInfo riscv_harts_info = {
74 .name = TYPE_RISCV_HART_ARRAY,
75 .parent = TYPE_SYS_BUS_DEVICE,
76 .instance_size = sizeof(RISCVHartArrayState),
77 .class_init = riscv_harts_class_init,
78};
79
80static void riscv_harts_register_types(void)
81{
82 type_register_static(&riscv_harts_info);
83}
84
85type_init(riscv_harts_register_types)
86