1/*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20#ifndef RISCV_CPU_H
21#define RISCV_CPU_H
22
23#include "hw/core/cpu.h"
24#include "exec/cpu-defs.h"
25#include "fpu/softfloat-types.h"
26
27#define TCG_GUEST_DEFAULT_MO 0
28
29#define TYPE_RISCV_CPU "riscv-cpu"
30
31#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
32#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
33#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
34
35#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
36#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
37#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
38#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
39#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
40#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
41#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
42/* Deprecated */
43#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
44#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
45#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
46#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
47#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
48#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
49
50#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
51#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
52
53#if defined(TARGET_RISCV32)
54#define RVXLEN RV32
55#elif defined(TARGET_RISCV64)
56#define RVXLEN RV64
57#endif
58
59#define RV(x) ((target_ulong)1 << (x - 'A'))
60
61#define RVI RV('I')
62#define RVE RV('E') /* E and I are mutually exclusive */
63#define RVM RV('M')
64#define RVA RV('A')
65#define RVF RV('F')
66#define RVD RV('D')
67#define RVC RV('C')
68#define RVS RV('S')
69#define RVU RV('U')
70
71/* S extension denotes that Supervisor mode exists, however it is possible
72 to have a core that support S mode but does not have an MMU and there
73 is currently no bit in misa to indicate whether an MMU exists or not
74 so a cpu features bitfield is required, likewise for optional PMP support */
75enum {
76 RISCV_FEATURE_MMU,
77 RISCV_FEATURE_PMP,
78 RISCV_FEATURE_MISA
79};
80
81#define PRIV_VERSION_1_09_1 0x00010901
82#define PRIV_VERSION_1_10_0 0x00011000
83#define PRIV_VERSION_1_11_0 0x00011100
84
85#define TRANSLATE_PMP_FAIL 2
86#define TRANSLATE_FAIL 1
87#define TRANSLATE_SUCCESS 0
88#define MMU_USER_IDX 3
89
90#define MAX_RISCV_PMPS (16)
91
92typedef struct CPURISCVState CPURISCVState;
93
94#include "pmp.h"
95
96struct CPURISCVState {
97 target_ulong gpr[32];
98 uint64_t fpr[32]; /* assume both F and D extensions */
99 target_ulong pc;
100 target_ulong load_res;
101 target_ulong load_val;
102
103 target_ulong frm;
104
105 target_ulong badaddr;
106
107 target_ulong priv_ver;
108 target_ulong misa;
109 target_ulong misa_mask;
110
111 uint32_t features;
112
113#ifdef CONFIG_USER_ONLY
114 uint32_t elf_flags;
115#endif
116
117#ifndef CONFIG_USER_ONLY
118 target_ulong priv;
119 target_ulong resetvec;
120
121 target_ulong mhartid;
122 target_ulong mstatus;
123
124 /*
125 * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously
126 * by I/O threads. It should be read with atomic_read. It should be updated
127 * using riscv_cpu_update_mip with the iothread mutex held. The iothread
128 * mutex must be held because mip must be consistent with the CPU inturrept
129 * state. riscv_cpu_update_mip calls cpu_interrupt or cpu_reset_interrupt
130 * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
131 * mip is 32-bits to allow atomic_read on 32-bit hosts.
132 */
133 uint32_t mip;
134 uint32_t miclaim;
135
136 target_ulong mie;
137 target_ulong mideleg;
138
139 target_ulong sptbr; /* until: priv-1.9.1 */
140 target_ulong satp; /* since: priv-1.10.0 */
141 target_ulong sbadaddr;
142 target_ulong mbadaddr;
143 target_ulong medeleg;
144
145 target_ulong stvec;
146 target_ulong sepc;
147 target_ulong scause;
148
149 target_ulong mtvec;
150 target_ulong mepc;
151 target_ulong mcause;
152 target_ulong mtval; /* since: priv-1.10.0 */
153
154 target_ulong scounteren;
155 target_ulong mcounteren;
156
157 target_ulong sscratch;
158 target_ulong mscratch;
159
160 /* temporary htif regs */
161 uint64_t mfromhost;
162 uint64_t mtohost;
163 uint64_t timecmp;
164
165 /* physical memory protection */
166 pmp_table_t pmp_state;
167
168 /* True if in debugger mode. */
169 bool debugger;
170#endif
171
172 float_status fp_status;
173
174 /* Fields from here on are preserved across CPU reset. */
175 QEMUTimer *timer; /* Internal timer */
176};
177
178#define RISCV_CPU_CLASS(klass) \
179 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
180#define RISCV_CPU(obj) \
181 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
182#define RISCV_CPU_GET_CLASS(obj) \
183 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
184
185/**
186 * RISCVCPUClass:
187 * @parent_realize: The parent class' realize handler.
188 * @parent_reset: The parent class' reset handler.
189 *
190 * A RISCV CPU model.
191 */
192typedef struct RISCVCPUClass {
193 /*< private >*/
194 CPUClass parent_class;
195 /*< public >*/
196 DeviceRealize parent_realize;
197 void (*parent_reset)(CPUState *cpu);
198} RISCVCPUClass;
199
200/**
201 * RISCVCPU:
202 * @env: #CPURISCVState
203 *
204 * A RISCV CPU.
205 */
206typedef struct RISCVCPU {
207 /*< private >*/
208 CPUState parent_obj;
209 /*< public >*/
210 CPUNegativeOffsetState neg;
211 CPURISCVState env;
212
213 /* Configuration Settings */
214 struct {
215 bool ext_i;
216 bool ext_e;
217 bool ext_g;
218 bool ext_m;
219 bool ext_a;
220 bool ext_f;
221 bool ext_d;
222 bool ext_c;
223 bool ext_s;
224 bool ext_u;
225 bool ext_counters;
226 bool ext_ifencei;
227 bool ext_icsr;
228
229 char *priv_spec;
230 char *user_spec;
231 bool mmu;
232 bool pmp;
233 } cfg;
234} RISCVCPU;
235
236static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
237{
238 return (env->misa & ext) != 0;
239}
240
241static inline bool riscv_feature(CPURISCVState *env, int feature)
242{
243 return env->features & (1ULL << feature);
244}
245
246#include "cpu_user.h"
247#include "cpu_bits.h"
248
249extern const char * const riscv_int_regnames[];
250extern const char * const riscv_fpr_regnames[];
251extern const char * const riscv_excp_names[];
252extern const char * const riscv_intr_names[];
253
254void riscv_cpu_do_interrupt(CPUState *cpu);
255int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
256int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
257bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
258int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
259hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
260void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
261 MMUAccessType access_type, int mmu_idx,
262 uintptr_t retaddr);
263bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
264 MMUAccessType access_type, int mmu_idx,
265 bool probe, uintptr_t retaddr);
266void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
267 bool is_exec, int unused, unsigned size);
268char *riscv_isa_string(RISCVCPU *cpu);
269void riscv_cpu_list(void);
270
271#define cpu_signal_handler riscv_cpu_signal_handler
272#define cpu_list riscv_cpu_list
273#define cpu_mmu_index riscv_cpu_mmu_index
274
275#ifndef CONFIG_USER_ONLY
276int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
277uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
278#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
279#endif
280void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
281
282void riscv_translate_init(void);
283int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
284void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
285 uint32_t exception, uintptr_t pc);
286
287target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
288void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
289
290#define TB_FLAGS_MMU_MASK 3
291#define TB_FLAGS_MSTATUS_FS MSTATUS_FS
292
293static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
294 target_ulong *cs_base, uint32_t *flags)
295{
296 *pc = env->pc;
297 *cs_base = 0;
298#ifdef CONFIG_USER_ONLY
299 *flags = TB_FLAGS_MSTATUS_FS;
300#else
301 *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS);
302#endif
303}
304
305int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
306 target_ulong new_value, target_ulong write_mask);
307int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
308 target_ulong new_value, target_ulong write_mask);
309
310static inline void riscv_csr_write(CPURISCVState *env, int csrno,
311 target_ulong val)
312{
313 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
314}
315
316static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
317{
318 target_ulong val = 0;
319 riscv_csrrw(env, csrno, &val, 0, 0);
320 return val;
321}
322
323typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
324typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
325 target_ulong *ret_value);
326typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
327 target_ulong new_value);
328typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
329 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
330
331typedef struct {
332 riscv_csr_predicate_fn predicate;
333 riscv_csr_read_fn read;
334 riscv_csr_write_fn write;
335 riscv_csr_op_fn op;
336} riscv_csr_operations;
337
338void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
339void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
340
341void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
342
343typedef CPURISCVState CPUArchState;
344typedef RISCVCPU ArchCPU;
345
346#include "exec/cpu-all.h"
347
348#endif /* RISCV_CPU_H */
349