1 | /* |
2 | * sifive System-on-Chip general purpose input/output register definition |
3 | * |
4 | * Copyright 2019 AdaCore |
5 | * |
6 | * Base on nrf51_gpio.c: |
7 | * |
8 | * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> |
9 | * |
10 | * This code is licensed under the GPL version 2 or later. See |
11 | * the COPYING file in the top-level directory. |
12 | */ |
13 | |
14 | #include "qemu/osdep.h" |
15 | #include "qemu/log.h" |
16 | #include "hw/irq.h" |
17 | #include "hw/riscv/sifive_gpio.h" |
18 | #include "migration/vmstate.h" |
19 | #include "trace.h" |
20 | |
21 | static void update_output_irq(SIFIVEGPIOState *s) |
22 | { |
23 | |
24 | uint32_t pending; |
25 | uint32_t pin; |
26 | |
27 | pending = s->high_ip & s->high_ie; |
28 | pending |= s->low_ip & s->low_ie; |
29 | pending |= s->rise_ip & s->rise_ie; |
30 | pending |= s->fall_ip & s->fall_ie; |
31 | |
32 | for (int i = 0; i < SIFIVE_GPIO_PINS; i++) { |
33 | pin = 1 << i; |
34 | qemu_set_irq(s->irq[i], (pending & pin) != 0); |
35 | trace_sifive_gpio_update_output_irq(i, (pending & pin) != 0); |
36 | } |
37 | } |
38 | |
39 | static void update_state(SIFIVEGPIOState *s) |
40 | { |
41 | size_t i; |
42 | bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en, |
43 | rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival; |
44 | |
45 | for (i = 0; i < SIFIVE_GPIO_PINS; i++) { |
46 | |
47 | prev_ival = extract32(s->value, i, 1); |
48 | in = extract32(s->in, i, 1); |
49 | in_mask = extract32(s->in_mask, i, 1); |
50 | port = extract32(s->port, i, 1); |
51 | out_xor = extract32(s->out_xor, i, 1); |
52 | pull = extract32(s->pue, i, 1); |
53 | output_en = extract32(s->output_en, i, 1); |
54 | input_en = extract32(s->input_en, i, 1); |
55 | rise_ip = extract32(s->rise_ip, i, 1); |
56 | fall_ip = extract32(s->fall_ip, i, 1); |
57 | low_ip = extract32(s->low_ip, i, 1); |
58 | high_ip = extract32(s->high_ip, i, 1); |
59 | |
60 | /* Output value (IOF not supported) */ |
61 | oval = output_en && (port ^ out_xor); |
62 | |
63 | /* Pin both driven externally and internally */ |
64 | if (output_en && in_mask) { |
65 | qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n" , i); |
66 | } |
67 | |
68 | if (in_mask) { |
69 | /* The pin is driven by external device */ |
70 | actual_value = in; |
71 | } else if (output_en) { |
72 | /* The pin is driven by internal circuit */ |
73 | actual_value = oval; |
74 | } else { |
75 | /* Floating? Apply pull-up resistor */ |
76 | actual_value = pull; |
77 | } |
78 | |
79 | qemu_set_irq(s->output[i], actual_value); |
80 | |
81 | /* Input value */ |
82 | ival = input_en && actual_value; |
83 | |
84 | /* Interrupts */ |
85 | high_ip = high_ip || ival; |
86 | s->high_ip = deposit32(s->high_ip, i, 1, high_ip); |
87 | |
88 | low_ip = low_ip || !ival; |
89 | s->low_ip = deposit32(s->low_ip, i, 1, low_ip); |
90 | |
91 | rise_ip = rise_ip || (ival && !prev_ival); |
92 | s->rise_ip = deposit32(s->rise_ip, i, 1, rise_ip); |
93 | |
94 | fall_ip = fall_ip || (!ival && prev_ival); |
95 | s->fall_ip = deposit32(s->fall_ip, i, 1, fall_ip); |
96 | |
97 | /* Update value */ |
98 | s->value = deposit32(s->value, i, 1, ival); |
99 | } |
100 | update_output_irq(s); |
101 | } |
102 | |
103 | static uint64_t sifive_gpio_read(void *opaque, hwaddr offset, unsigned int size) |
104 | { |
105 | SIFIVEGPIOState *s = SIFIVE_GPIO(opaque); |
106 | uint64_t r = 0; |
107 | |
108 | switch (offset) { |
109 | case SIFIVE_GPIO_REG_VALUE: |
110 | r = s->value; |
111 | break; |
112 | |
113 | case SIFIVE_GPIO_REG_INPUT_EN: |
114 | r = s->input_en; |
115 | break; |
116 | |
117 | case SIFIVE_GPIO_REG_OUTPUT_EN: |
118 | r = s->output_en; |
119 | break; |
120 | |
121 | case SIFIVE_GPIO_REG_PORT: |
122 | r = s->port; |
123 | break; |
124 | |
125 | case SIFIVE_GPIO_REG_PUE: |
126 | r = s->pue; |
127 | break; |
128 | |
129 | case SIFIVE_GPIO_REG_DS: |
130 | r = s->ds; |
131 | break; |
132 | |
133 | case SIFIVE_GPIO_REG_RISE_IE: |
134 | r = s->rise_ie; |
135 | break; |
136 | |
137 | case SIFIVE_GPIO_REG_RISE_IP: |
138 | r = s->rise_ip; |
139 | break; |
140 | |
141 | case SIFIVE_GPIO_REG_FALL_IE: |
142 | r = s->fall_ie; |
143 | break; |
144 | |
145 | case SIFIVE_GPIO_REG_FALL_IP: |
146 | r = s->fall_ip; |
147 | break; |
148 | |
149 | case SIFIVE_GPIO_REG_HIGH_IE: |
150 | r = s->high_ie; |
151 | break; |
152 | |
153 | case SIFIVE_GPIO_REG_HIGH_IP: |
154 | r = s->high_ip; |
155 | break; |
156 | |
157 | case SIFIVE_GPIO_REG_LOW_IE: |
158 | r = s->low_ie; |
159 | break; |
160 | |
161 | case SIFIVE_GPIO_REG_LOW_IP: |
162 | r = s->low_ip; |
163 | break; |
164 | |
165 | case SIFIVE_GPIO_REG_IOF_EN: |
166 | r = s->iof_en; |
167 | break; |
168 | |
169 | case SIFIVE_GPIO_REG_IOF_SEL: |
170 | r = s->iof_sel; |
171 | break; |
172 | |
173 | case SIFIVE_GPIO_REG_OUT_XOR: |
174 | r = s->out_xor; |
175 | break; |
176 | |
177 | default: |
178 | qemu_log_mask(LOG_GUEST_ERROR, |
179 | "%s: bad read offset 0x%" HWADDR_PRIx "\n" , |
180 | __func__, offset); |
181 | } |
182 | |
183 | trace_sifive_gpio_read(offset, r); |
184 | |
185 | return r; |
186 | } |
187 | |
188 | static void sifive_gpio_write(void *opaque, hwaddr offset, |
189 | uint64_t value, unsigned int size) |
190 | { |
191 | SIFIVEGPIOState *s = SIFIVE_GPIO(opaque); |
192 | |
193 | trace_sifive_gpio_write(offset, value); |
194 | |
195 | switch (offset) { |
196 | |
197 | case SIFIVE_GPIO_REG_INPUT_EN: |
198 | s->input_en = value; |
199 | break; |
200 | |
201 | case SIFIVE_GPIO_REG_OUTPUT_EN: |
202 | s->output_en = value; |
203 | break; |
204 | |
205 | case SIFIVE_GPIO_REG_PORT: |
206 | s->port = value; |
207 | break; |
208 | |
209 | case SIFIVE_GPIO_REG_PUE: |
210 | s->pue = value; |
211 | break; |
212 | |
213 | case SIFIVE_GPIO_REG_DS: |
214 | s->ds = value; |
215 | break; |
216 | |
217 | case SIFIVE_GPIO_REG_RISE_IE: |
218 | s->rise_ie = value; |
219 | break; |
220 | |
221 | case SIFIVE_GPIO_REG_RISE_IP: |
222 | /* Write 1 to clear */ |
223 | s->rise_ip &= ~value; |
224 | break; |
225 | |
226 | case SIFIVE_GPIO_REG_FALL_IE: |
227 | s->fall_ie = value; |
228 | break; |
229 | |
230 | case SIFIVE_GPIO_REG_FALL_IP: |
231 | /* Write 1 to clear */ |
232 | s->fall_ip &= ~value; |
233 | break; |
234 | |
235 | case SIFIVE_GPIO_REG_HIGH_IE: |
236 | s->high_ie = value; |
237 | break; |
238 | |
239 | case SIFIVE_GPIO_REG_HIGH_IP: |
240 | /* Write 1 to clear */ |
241 | s->high_ip &= ~value; |
242 | break; |
243 | |
244 | case SIFIVE_GPIO_REG_LOW_IE: |
245 | s->low_ie = value; |
246 | break; |
247 | |
248 | case SIFIVE_GPIO_REG_LOW_IP: |
249 | /* Write 1 to clear */ |
250 | s->low_ip &= ~value; |
251 | break; |
252 | |
253 | case SIFIVE_GPIO_REG_IOF_EN: |
254 | s->iof_en = value; |
255 | break; |
256 | |
257 | case SIFIVE_GPIO_REG_IOF_SEL: |
258 | s->iof_sel = value; |
259 | break; |
260 | |
261 | case SIFIVE_GPIO_REG_OUT_XOR: |
262 | s->out_xor = value; |
263 | break; |
264 | |
265 | default: |
266 | qemu_log_mask(LOG_GUEST_ERROR, |
267 | "%s: bad write offset 0x%" HWADDR_PRIx "\n" , |
268 | __func__, offset); |
269 | } |
270 | |
271 | update_state(s); |
272 | } |
273 | |
274 | static const MemoryRegionOps gpio_ops = { |
275 | .read = sifive_gpio_read, |
276 | .write = sifive_gpio_write, |
277 | .endianness = DEVICE_LITTLE_ENDIAN, |
278 | .impl.min_access_size = 4, |
279 | .impl.max_access_size = 4, |
280 | }; |
281 | |
282 | static void sifive_gpio_set(void *opaque, int line, int value) |
283 | { |
284 | SIFIVEGPIOState *s = SIFIVE_GPIO(opaque); |
285 | |
286 | trace_sifive_gpio_set(line, value); |
287 | |
288 | assert(line >= 0 && line < SIFIVE_GPIO_PINS); |
289 | |
290 | s->in_mask = deposit32(s->in_mask, line, 1, value >= 0); |
291 | if (value >= 0) { |
292 | s->in = deposit32(s->in, line, 1, value != 0); |
293 | } |
294 | |
295 | update_state(s); |
296 | } |
297 | |
298 | static void sifive_gpio_reset(DeviceState *dev) |
299 | { |
300 | SIFIVEGPIOState *s = SIFIVE_GPIO(dev); |
301 | |
302 | s->value = 0; |
303 | s->input_en = 0; |
304 | s->output_en = 0; |
305 | s->port = 0; |
306 | s->pue = 0; |
307 | s->ds = 0; |
308 | s->rise_ie = 0; |
309 | s->rise_ip = 0; |
310 | s->fall_ie = 0; |
311 | s->fall_ip = 0; |
312 | s->high_ie = 0; |
313 | s->high_ip = 0; |
314 | s->low_ie = 0; |
315 | s->low_ip = 0; |
316 | s->iof_en = 0; |
317 | s->iof_sel = 0; |
318 | s->out_xor = 0; |
319 | s->in = 0; |
320 | s->in_mask = 0; |
321 | |
322 | } |
323 | |
324 | static const VMStateDescription vmstate_sifive_gpio = { |
325 | .name = TYPE_SIFIVE_GPIO, |
326 | .version_id = 1, |
327 | .minimum_version_id = 1, |
328 | .fields = (VMStateField[]) { |
329 | VMSTATE_UINT32(value, SIFIVEGPIOState), |
330 | VMSTATE_UINT32(input_en, SIFIVEGPIOState), |
331 | VMSTATE_UINT32(output_en, SIFIVEGPIOState), |
332 | VMSTATE_UINT32(port, SIFIVEGPIOState), |
333 | VMSTATE_UINT32(pue, SIFIVEGPIOState), |
334 | VMSTATE_UINT32(rise_ie, SIFIVEGPIOState), |
335 | VMSTATE_UINT32(rise_ip, SIFIVEGPIOState), |
336 | VMSTATE_UINT32(fall_ie, SIFIVEGPIOState), |
337 | VMSTATE_UINT32(fall_ip, SIFIVEGPIOState), |
338 | VMSTATE_UINT32(high_ie, SIFIVEGPIOState), |
339 | VMSTATE_UINT32(high_ip, SIFIVEGPIOState), |
340 | VMSTATE_UINT32(low_ie, SIFIVEGPIOState), |
341 | VMSTATE_UINT32(low_ip, SIFIVEGPIOState), |
342 | VMSTATE_UINT32(iof_en, SIFIVEGPIOState), |
343 | VMSTATE_UINT32(iof_sel, SIFIVEGPIOState), |
344 | VMSTATE_UINT32(out_xor, SIFIVEGPIOState), |
345 | VMSTATE_UINT32(in, SIFIVEGPIOState), |
346 | VMSTATE_UINT32(in_mask, SIFIVEGPIOState), |
347 | VMSTATE_END_OF_LIST() |
348 | } |
349 | }; |
350 | |
351 | static void sifive_gpio_init(Object *obj) |
352 | { |
353 | SIFIVEGPIOState *s = SIFIVE_GPIO(obj); |
354 | |
355 | memory_region_init_io(&s->mmio, obj, &gpio_ops, s, |
356 | TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE); |
357 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); |
358 | |
359 | |
360 | for (int i = 0; i < SIFIVE_GPIO_PINS; i++) { |
361 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); |
362 | } |
363 | |
364 | qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS); |
365 | qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS); |
366 | } |
367 | |
368 | static void sifive_gpio_class_init(ObjectClass *klass, void *data) |
369 | { |
370 | DeviceClass *dc = DEVICE_CLASS(klass); |
371 | |
372 | dc->vmsd = &vmstate_sifive_gpio; |
373 | dc->reset = sifive_gpio_reset; |
374 | dc->desc = "sifive GPIO" ; |
375 | } |
376 | |
377 | static const TypeInfo sifive_gpio_info = { |
378 | .name = TYPE_SIFIVE_GPIO, |
379 | .parent = TYPE_SYS_BUS_DEVICE, |
380 | .instance_size = sizeof(SIFIVEGPIOState), |
381 | .instance_init = sifive_gpio_init, |
382 | .class_init = sifive_gpio_class_init |
383 | }; |
384 | |
385 | static void sifive_gpio_register_types(void) |
386 | { |
387 | type_register_static(&sifive_gpio_info); |
388 | } |
389 | |
390 | type_init(sifive_gpio_register_types) |
391 | |