1 | /* |
2 | * s390 PCI BUS definitions |
3 | * |
4 | * Copyright 2014 IBM Corp. |
5 | * Author(s): Frank Blaschka <frank.blaschka@de.ibm.com> |
6 | * Hong Bo Li <lihbbj@cn.ibm.com> |
7 | * Yi Min Zhao <zyimin@cn.ibm.com> |
8 | * |
9 | * This work is licensed under the terms of the GNU GPL, version 2 or (at |
10 | * your option) any later version. See the COPYING file in the top-level |
11 | * directory. |
12 | */ |
13 | |
14 | #ifndef HW_S390_PCI_BUS_H |
15 | #define HW_S390_PCI_BUS_H |
16 | |
17 | #include "hw/pci/pci.h" |
18 | #include "hw/pci/pci_host.h" |
19 | #include "hw/s390x/sclp.h" |
20 | #include "hw/s390x/s390_flic.h" |
21 | #include "hw/s390x/css.h" |
22 | |
23 | #define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost" |
24 | #define TYPE_S390_PCI_BUS "s390-pcibus" |
25 | #define TYPE_S390_PCI_DEVICE "zpci" |
26 | #define TYPE_S390_PCI_IOMMU "s390-pci-iommu" |
27 | #define TYPE_S390_IOMMU_MEMORY_REGION "s390-iommu-memory-region" |
28 | #define FH_MASK_ENABLE 0x80000000 |
29 | #define FH_MASK_INSTANCE 0x7f000000 |
30 | #define FH_MASK_SHM 0x00ff0000 |
31 | #define FH_MASK_INDEX 0x0000ffff |
32 | #define FH_SHM_VFIO 0x00010000 |
33 | #define FH_SHM_EMUL 0x00020000 |
34 | #define ZPCI_MAX_FID 0xffffffff |
35 | #define ZPCI_MAX_UID 0xffff |
36 | #define UID_UNDEFINED 0 |
37 | #define UID_CHECKING_ENABLED 0x01 |
38 | |
39 | #define S390_PCI_HOST_BRIDGE(obj) \ |
40 | OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE) |
41 | #define S390_PCI_BUS(obj) \ |
42 | OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS) |
43 | #define S390_PCI_DEVICE(obj) \ |
44 | OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE) |
45 | #define S390_PCI_IOMMU(obj) \ |
46 | OBJECT_CHECK(S390PCIIOMMU, (obj), TYPE_S390_PCI_IOMMU) |
47 | |
48 | #define HP_EVENT_TO_CONFIGURED 0x0301 |
49 | #define HP_EVENT_RESERVED_TO_STANDBY 0x0302 |
50 | #define HP_EVENT_DECONFIGURE_REQUEST 0x0303 |
51 | #define HP_EVENT_CONFIGURED_TO_STBRES 0x0304 |
52 | #define HP_EVENT_STANDBY_TO_RESERVED 0x0308 |
53 | |
54 | #define ERR_EVENT_INVALAS 0x1 |
55 | #define ERR_EVENT_OORANGE 0x2 |
56 | #define ERR_EVENT_INVALTF 0x3 |
57 | #define ERR_EVENT_TPROTE 0x4 |
58 | #define ERR_EVENT_APROTE 0x5 |
59 | #define ERR_EVENT_KEYE 0x6 |
60 | #define ERR_EVENT_INVALTE 0x7 |
61 | #define ERR_EVENT_INVALTL 0x8 |
62 | #define ERR_EVENT_TT 0x9 |
63 | #define ERR_EVENT_INVALMS 0xa |
64 | #define ERR_EVENT_SERR 0xb |
65 | #define ERR_EVENT_NOMSI 0x10 |
66 | #define ERR_EVENT_INVALBV 0x11 |
67 | #define ERR_EVENT_AIBV 0x12 |
68 | #define ERR_EVENT_AIRERR 0x13 |
69 | #define ERR_EVENT_FMBA 0x2a |
70 | #define ERR_EVENT_FMBUP 0x2b |
71 | #define ERR_EVENT_FMBPRO 0x2c |
72 | #define ERR_EVENT_CCONF 0x30 |
73 | #define ERR_EVENT_SERVAC 0x3a |
74 | #define ERR_EVENT_PERMERR 0x3b |
75 | |
76 | #define ERR_EVENT_Q_BIT 0x2 |
77 | #define ERR_EVENT_MVN_OFFSET 16 |
78 | |
79 | #define ZPCI_MSI_VEC_BITS 11 |
80 | #define ZPCI_MSI_VEC_MASK 0x7ff |
81 | |
82 | #define ZPCI_MSI_ADDR 0xfe00000000000000ULL |
83 | #define ZPCI_SDMA_ADDR 0x100000000ULL |
84 | #define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL |
85 | |
86 | #define PAGE_SHIFT 12 |
87 | #define PAGE_SIZE (1 << PAGE_SHIFT) |
88 | #define PAGE_MASK (~(PAGE_SIZE-1)) |
89 | #define PAGE_DEFAULT_ACC 0 |
90 | #define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4) |
91 | |
92 | /* I/O Translation Anchor (IOTA) */ |
93 | enum ZpciIoatDtype { |
94 | ZPCI_IOTA_STO = 0, |
95 | ZPCI_IOTA_RTTO = 1, |
96 | ZPCI_IOTA_RSTO = 2, |
97 | ZPCI_IOTA_RFTO = 3, |
98 | ZPCI_IOTA_PFAA = 4, |
99 | ZPCI_IOTA_IOPFAA = 5, |
100 | ZPCI_IOTA_IOPTO = 7 |
101 | }; |
102 | |
103 | #define ZPCI_IOTA_IOT_ENABLED 0x800ULL |
104 | #define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2) |
105 | #define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2) |
106 | #define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2) |
107 | #define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2) |
108 | #define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2) |
109 | #define ZPCI_IOTA_FS_4K 0 |
110 | #define ZPCI_IOTA_FS_1M 1 |
111 | #define ZPCI_IOTA_FS_2G 2 |
112 | #define ZPCI_KEY (PAGE_DEFAULT_KEY << 5) |
113 | |
114 | #define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST) |
115 | #define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT) |
116 | #define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS) |
117 | #define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF) |
118 | #define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\ |
119 | ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G) |
120 | |
121 | /* I/O Region and segment tables */ |
122 | #define ZPCI_INDEX_MASK 0x7ffULL |
123 | |
124 | #define ZPCI_TABLE_TYPE_MASK 0xc |
125 | #define ZPCI_TABLE_TYPE_RFX 0xc |
126 | #define ZPCI_TABLE_TYPE_RSX 0x8 |
127 | #define ZPCI_TABLE_TYPE_RTX 0x4 |
128 | #define ZPCI_TABLE_TYPE_SX 0x0 |
129 | |
130 | #define ZPCI_TABLE_LEN_RFX 0x3 |
131 | #define ZPCI_TABLE_LEN_RSX 0x3 |
132 | #define ZPCI_TABLE_LEN_RTX 0x3 |
133 | |
134 | #define ZPCI_TABLE_OFFSET_MASK 0xc0 |
135 | #define ZPCI_TABLE_SIZE 0x4000 |
136 | #define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE |
137 | #define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long)) |
138 | #define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE) |
139 | |
140 | #define ZPCI_TABLE_BITS 11 |
141 | #define ZPCI_PT_BITS 8 |
142 | #define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT) |
143 | #define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS) |
144 | |
145 | #define ZPCI_RTE_FLAG_MASK 0x3fffULL |
146 | #define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK) |
147 | #define ZPCI_STE_FLAG_MASK 0x7ffULL |
148 | #define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK) |
149 | |
150 | #define ZPCI_SFAA_MASK (~((1ULL << 20) - 1)) |
151 | |
152 | /* I/O Page tables */ |
153 | #define ZPCI_PTE_VALID_MASK 0x400 |
154 | #define ZPCI_PTE_INVALID 0x400 |
155 | #define ZPCI_PTE_VALID 0x000 |
156 | #define ZPCI_PT_SIZE 0x800 |
157 | #define ZPCI_PT_ALIGN ZPCI_PT_SIZE |
158 | #define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE) |
159 | #define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1) |
160 | |
161 | #define ZPCI_PTE_FLAG_MASK 0xfffULL |
162 | #define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK) |
163 | |
164 | /* Shared bits */ |
165 | #define ZPCI_TABLE_VALID 0x00 |
166 | #define ZPCI_TABLE_INVALID 0x20 |
167 | #define ZPCI_TABLE_PROTECTED 0x200 |
168 | #define ZPCI_TABLE_UNPROTECTED 0x000 |
169 | #define ZPCI_TABLE_FC 0x400 |
170 | |
171 | #define ZPCI_TABLE_VALID_MASK 0x20 |
172 | #define ZPCI_TABLE_PROT_MASK 0x200 |
173 | |
174 | #define ZPCI_ETT_RT 1 |
175 | #define ZPCI_ETT_ST 0 |
176 | #define ZPCI_ETT_PT -1 |
177 | |
178 | /* PCI Function States |
179 | * |
180 | * reserved: default; device has just been plugged or is in progress of being |
181 | * unplugged |
182 | * standby: device is present but not configured; transition from any |
183 | * configured state/to this state via sclp configure/deconfigure |
184 | * |
185 | * The following states make up the "configured" meta-state: |
186 | * disabled: device is configured but not enabled; transition between this |
187 | * state and enabled via clp enable/disable |
188 | * enbaled: device is ready for use; transition to disabled via clp disable; |
189 | * may enter an error state |
190 | * blocked: ignore all DMA and interrupts; transition back to enabled or from |
191 | * error state via mpcifc |
192 | * error: an error occurred; transition back to enabled via mpcifc |
193 | * permanent error: an unrecoverable error occurred; transition to standby via |
194 | * sclp deconfigure |
195 | */ |
196 | typedef enum { |
197 | ZPCI_FS_RESERVED, |
198 | ZPCI_FS_STANDBY, |
199 | ZPCI_FS_DISABLED, |
200 | ZPCI_FS_ENABLED, |
201 | ZPCI_FS_BLOCKED, |
202 | ZPCI_FS_ERROR, |
203 | ZPCI_FS_PERMANENT_ERROR, |
204 | } ZpciState; |
205 | |
206 | typedef struct SeiContainer { |
207 | QTAILQ_ENTRY(SeiContainer) link; |
208 | uint32_t fid; |
209 | uint32_t fh; |
210 | uint8_t cc; |
211 | uint16_t pec; |
212 | uint64_t faddr; |
213 | uint32_t e; |
214 | } SeiContainer; |
215 | |
216 | typedef struct PciCcdfErr { |
217 | uint32_t reserved1; |
218 | uint32_t fh; |
219 | uint32_t fid; |
220 | uint32_t e; |
221 | uint64_t faddr; |
222 | uint32_t reserved3; |
223 | uint16_t reserved4; |
224 | uint16_t pec; |
225 | } QEMU_PACKED PciCcdfErr; |
226 | |
227 | typedef struct PciCcdfAvail { |
228 | uint32_t reserved1; |
229 | uint32_t fh; |
230 | uint32_t fid; |
231 | uint32_t reserved2; |
232 | uint32_t reserved3; |
233 | uint32_t reserved4; |
234 | uint32_t reserved5; |
235 | uint16_t reserved6; |
236 | uint16_t pec; |
237 | } QEMU_PACKED PciCcdfAvail; |
238 | |
239 | typedef struct ChscSeiNt2Res { |
240 | uint16_t length; |
241 | uint16_t code; |
242 | uint16_t reserved1; |
243 | uint8_t reserved2; |
244 | uint8_t nt; |
245 | uint8_t flags; |
246 | uint8_t reserved3; |
247 | uint8_t reserved4; |
248 | uint8_t cc; |
249 | uint32_t reserved5[13]; |
250 | uint8_t ccdf[4016]; |
251 | } QEMU_PACKED ChscSeiNt2Res; |
252 | |
253 | typedef struct S390MsixInfo { |
254 | uint8_t table_bar; |
255 | uint8_t pba_bar; |
256 | uint16_t entries; |
257 | uint32_t table_offset; |
258 | uint32_t pba_offset; |
259 | } S390MsixInfo; |
260 | |
261 | typedef struct S390IOTLBEntry { |
262 | uint64_t iova; |
263 | uint64_t translated_addr; |
264 | uint64_t len; |
265 | uint64_t perm; |
266 | } S390IOTLBEntry; |
267 | |
268 | typedef struct S390PCIBusDevice S390PCIBusDevice; |
269 | typedef struct S390PCIIOMMU { |
270 | Object parent_obj; |
271 | S390PCIBusDevice *pbdev; |
272 | AddressSpace as; |
273 | MemoryRegion mr; |
274 | IOMMUMemoryRegion iommu_mr; |
275 | bool enabled; |
276 | uint64_t g_iota; |
277 | uint64_t pba; |
278 | uint64_t pal; |
279 | GHashTable *iotlb; |
280 | } S390PCIIOMMU; |
281 | |
282 | typedef struct S390PCIIOMMUTable { |
283 | uint64_t key; |
284 | S390PCIIOMMU *iommu[PCI_SLOT_MAX]; |
285 | } S390PCIIOMMUTable; |
286 | |
287 | /* Function Measurement Block */ |
288 | #define DEFAULT_MUI 4000 |
289 | #define UPDATE_U_BIT 0x1ULL |
290 | #define FMBK_MASK 0xfULL |
291 | |
292 | typedef struct ZpciFmbFmt0 { |
293 | uint64_t dma_rbytes; |
294 | uint64_t dma_wbytes; |
295 | } ZpciFmbFmt0; |
296 | |
297 | #define ZPCI_FMB_CNT_LD 0 |
298 | #define ZPCI_FMB_CNT_ST 1 |
299 | #define ZPCI_FMB_CNT_STB 2 |
300 | #define ZPCI_FMB_CNT_RPCIT 3 |
301 | #define ZPCI_FMB_CNT_MAX 4 |
302 | |
303 | #define ZPCI_FMB_FORMAT 0 |
304 | |
305 | typedef struct ZpciFmb { |
306 | uint32_t format; |
307 | uint32_t sample; |
308 | uint64_t last_update; |
309 | uint64_t counter[ZPCI_FMB_CNT_MAX]; |
310 | ZpciFmbFmt0 fmt0; |
311 | } ZpciFmb; |
312 | QEMU_BUILD_BUG_MSG(offsetof(ZpciFmb, fmt0) != 48, "padding in ZpciFmb" ); |
313 | |
314 | struct S390PCIBusDevice { |
315 | DeviceState qdev; |
316 | PCIDevice *pdev; |
317 | ZpciState state; |
318 | char *target; |
319 | uint16_t uid; |
320 | uint32_t idx; |
321 | uint32_t fh; |
322 | uint32_t fid; |
323 | bool fid_defined; |
324 | uint64_t fmb_addr; |
325 | ZpciFmb fmb; |
326 | QEMUTimer *fmb_timer; |
327 | uint8_t isc; |
328 | uint16_t noi; |
329 | uint16_t maxstbl; |
330 | uint8_t sum; |
331 | S390MsixInfo msix; |
332 | AdapterRoutes routes; |
333 | S390PCIIOMMU *iommu; |
334 | MemoryRegion msix_notify_mr; |
335 | IndAddr *summary_ind; |
336 | IndAddr *indicator; |
337 | bool pci_unplug_request_processed; |
338 | bool unplug_requested; |
339 | QTAILQ_ENTRY(S390PCIBusDevice) link; |
340 | }; |
341 | |
342 | typedef struct S390PCIBus { |
343 | BusState qbus; |
344 | } S390PCIBus; |
345 | |
346 | typedef struct S390pciState { |
347 | PCIHostState parent_obj; |
348 | uint32_t next_idx; |
349 | int bus_no; |
350 | S390PCIBus *bus; |
351 | GHashTable *iommu_table; |
352 | GHashTable *zpci_table; |
353 | QTAILQ_HEAD(, SeiContainer) pending_sei; |
354 | QTAILQ_HEAD(, S390PCIBusDevice) zpci_devs; |
355 | } S390pciState; |
356 | |
357 | S390pciState *s390_get_phb(void); |
358 | int pci_chsc_sei_nt2_get_event(void *res); |
359 | int pci_chsc_sei_nt2_have_event(void); |
360 | void s390_pci_sclp_configure(SCCB *sccb); |
361 | void s390_pci_sclp_deconfigure(SCCB *sccb); |
362 | void s390_pci_iommu_enable(S390PCIIOMMU *iommu); |
363 | void s390_pci_iommu_disable(S390PCIIOMMU *iommu); |
364 | void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid, |
365 | uint64_t faddr, uint32_t e); |
366 | uint16_t s390_guest_io_table_walk(uint64_t g_iota, hwaddr addr, |
367 | S390IOTLBEntry *entry); |
368 | S390PCIBusDevice *s390_pci_find_dev_by_idx(S390pciState *s, uint32_t idx); |
369 | S390PCIBusDevice *s390_pci_find_dev_by_fh(S390pciState *s, uint32_t fh); |
370 | S390PCIBusDevice *s390_pci_find_dev_by_fid(S390pciState *s, uint32_t fid); |
371 | S390PCIBusDevice *s390_pci_find_dev_by_target(S390pciState *s, |
372 | const char *target); |
373 | S390PCIBusDevice *s390_pci_find_next_avail_dev(S390pciState *s, |
374 | S390PCIBusDevice *pbdev); |
375 | |
376 | #endif |
377 | |