1/*
2 * QEMU model of the Altera timer.
3 *
4 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21#include "qemu/osdep.h"
22#include "qemu/main-loop.h"
23#include "qemu/module.h"
24#include "qapi/error.h"
25
26#include "hw/sysbus.h"
27#include "hw/irq.h"
28#include "hw/ptimer.h"
29#include "hw/qdev-properties.h"
30
31#define R_STATUS 0
32#define R_CONTROL 1
33#define R_PERIODL 2
34#define R_PERIODH 3
35#define R_SNAPL 4
36#define R_SNAPH 5
37#define R_MAX 6
38
39#define STATUS_TO 0x0001
40#define STATUS_RUN 0x0002
41
42#define CONTROL_ITO 0x0001
43#define CONTROL_CONT 0x0002
44#define CONTROL_START 0x0004
45#define CONTROL_STOP 0x0008
46
47#define TYPE_ALTERA_TIMER "ALTR.timer"
48#define ALTERA_TIMER(obj) \
49 OBJECT_CHECK(AlteraTimer, (obj), TYPE_ALTERA_TIMER)
50
51typedef struct AlteraTimer {
52 SysBusDevice busdev;
53 MemoryRegion mmio;
54 qemu_irq irq;
55 uint32_t freq_hz;
56 QEMUBH *bh;
57 ptimer_state *ptimer;
58 uint32_t regs[R_MAX];
59} AlteraTimer;
60
61static int timer_irq_state(AlteraTimer *t)
62{
63 bool irq = (t->regs[R_STATUS] & STATUS_TO) &&
64 (t->regs[R_CONTROL] & CONTROL_ITO);
65 return irq;
66}
67
68static uint64_t timer_read(void *opaque, hwaddr addr,
69 unsigned int size)
70{
71 AlteraTimer *t = opaque;
72 uint64_t r = 0;
73
74 addr >>= 2;
75
76 switch (addr) {
77 case R_CONTROL:
78 r = t->regs[R_CONTROL] & (CONTROL_ITO | CONTROL_CONT);
79 break;
80
81 default:
82 if (addr < ARRAY_SIZE(t->regs)) {
83 r = t->regs[addr];
84 }
85 break;
86 }
87
88 return r;
89}
90
91static void timer_write(void *opaque, hwaddr addr,
92 uint64_t value, unsigned int size)
93{
94 AlteraTimer *t = opaque;
95 uint64_t tvalue;
96 uint32_t count = 0;
97 int irqState = timer_irq_state(t);
98
99 addr >>= 2;
100
101 switch (addr) {
102 case R_STATUS:
103 /* The timeout bit is cleared by writing the status register. */
104 t->regs[R_STATUS] &= ~STATUS_TO;
105 break;
106
107 case R_CONTROL:
108 t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT);
109 if ((value & CONTROL_START) &&
110 !(t->regs[R_STATUS] & STATUS_RUN)) {
111 ptimer_run(t->ptimer, 1);
112 t->regs[R_STATUS] |= STATUS_RUN;
113 }
114 if ((value & CONTROL_STOP) && (t->regs[R_STATUS] & STATUS_RUN)) {
115 ptimer_stop(t->ptimer);
116 t->regs[R_STATUS] &= ~STATUS_RUN;
117 }
118 break;
119
120 case R_PERIODL:
121 case R_PERIODH:
122 t->regs[addr] = value & 0xFFFF;
123 if (t->regs[R_STATUS] & STATUS_RUN) {
124 ptimer_stop(t->ptimer);
125 t->regs[R_STATUS] &= ~STATUS_RUN;
126 }
127 tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
128 ptimer_set_limit(t->ptimer, tvalue + 1, 1);
129 break;
130
131 case R_SNAPL:
132 case R_SNAPH:
133 count = ptimer_get_count(t->ptimer);
134 t->regs[R_SNAPL] = count & 0xFFFF;
135 t->regs[R_SNAPH] = count >> 16;
136 break;
137
138 default:
139 break;
140 }
141
142 if (irqState != timer_irq_state(t)) {
143 qemu_set_irq(t->irq, timer_irq_state(t));
144 }
145}
146
147static const MemoryRegionOps timer_ops = {
148 .read = timer_read,
149 .write = timer_write,
150 .endianness = DEVICE_NATIVE_ENDIAN,
151 .valid = {
152 .min_access_size = 1,
153 .max_access_size = 4
154 }
155};
156
157static void timer_hit(void *opaque)
158{
159 AlteraTimer *t = opaque;
160 const uint64_t tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
161
162 t->regs[R_STATUS] |= STATUS_TO;
163
164 ptimer_set_limit(t->ptimer, tvalue + 1, 1);
165
166 if (!(t->regs[R_CONTROL] & CONTROL_CONT)) {
167 t->regs[R_STATUS] &= ~STATUS_RUN;
168 ptimer_set_count(t->ptimer, tvalue);
169 } else {
170 ptimer_run(t->ptimer, 1);
171 }
172
173 qemu_set_irq(t->irq, timer_irq_state(t));
174}
175
176static void altera_timer_realize(DeviceState *dev, Error **errp)
177{
178 AlteraTimer *t = ALTERA_TIMER(dev);
179 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
180
181 if (t->freq_hz == 0) {
182 error_setg(errp, "\"clock-frequency\" property must be provided.");
183 return;
184 }
185
186 t->bh = qemu_bh_new(timer_hit, t);
187 t->ptimer = ptimer_init(t->bh, PTIMER_POLICY_DEFAULT);
188 ptimer_set_freq(t->ptimer, t->freq_hz);
189
190 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
191 TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
192 sysbus_init_mmio(sbd, &t->mmio);
193}
194
195static void altera_timer_init(Object *obj)
196{
197 AlteraTimer *t = ALTERA_TIMER(obj);
198 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
199
200 sysbus_init_irq(sbd, &t->irq);
201}
202
203static void altera_timer_reset(DeviceState *dev)
204{
205 AlteraTimer *t = ALTERA_TIMER(dev);
206
207 ptimer_stop(t->ptimer);
208 ptimer_set_limit(t->ptimer, 0xffffffff, 1);
209 memset(t->regs, 0, sizeof(t->regs));
210}
211
212static Property altera_timer_properties[] = {
213 DEFINE_PROP_UINT32("clock-frequency", AlteraTimer, freq_hz, 0),
214 DEFINE_PROP_END_OF_LIST(),
215};
216
217static void altera_timer_class_init(ObjectClass *klass, void *data)
218{
219 DeviceClass *dc = DEVICE_CLASS(klass);
220
221 dc->realize = altera_timer_realize;
222 dc->props = altera_timer_properties;
223 dc->reset = altera_timer_reset;
224}
225
226static const TypeInfo altera_timer_info = {
227 .name = TYPE_ALTERA_TIMER,
228 .parent = TYPE_SYS_BUS_DEVICE,
229 .instance_size = sizeof(AlteraTimer),
230 .instance_init = altera_timer_init,
231 .class_init = altera_timer_class_init,
232};
233
234static void altera_timer_register(void)
235{
236 type_register_static(&altera_timer_info);
237}
238
239type_init(altera_timer_register)
240