1 | /* |
2 | * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP |
3 | * |
4 | * Copyright (c) 2006-2007 CodeSourcery. |
5 | * Copyright (c) 2011 Linaro Limited |
6 | * Written by Paul Brook, Peter Maydell |
7 | * |
8 | * This program is free software; you can redistribute it and/or |
9 | * modify it under the terms of the GNU General Public License |
10 | * as published by the Free Software Foundation; either version |
11 | * 2 of the License, or (at your option) any later version. |
12 | * |
13 | * This program is distributed in the hope that it will be useful, |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | * GNU General Public License for more details. |
17 | * |
18 | * You should have received a copy of the GNU General Public License along |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
20 | */ |
21 | |
22 | #include "qemu/osdep.h" |
23 | #include "hw/hw.h" |
24 | #include "hw/irq.h" |
25 | #include "hw/ptimer.h" |
26 | #include "hw/qdev-properties.h" |
27 | #include "hw/timer/arm_mptimer.h" |
28 | #include "migration/vmstate.h" |
29 | #include "qapi/error.h" |
30 | #include "qemu/main-loop.h" |
31 | #include "qemu/module.h" |
32 | #include "hw/core/cpu.h" |
33 | |
34 | #define PTIMER_POLICY \ |
35 | (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \ |
36 | PTIMER_POLICY_CONTINUOUS_TRIGGER | \ |
37 | PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | \ |
38 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | \ |
39 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) |
40 | |
41 | /* This device implements the per-cpu private timer and watchdog block |
42 | * which is used in both the ARM11MPCore and Cortex-A9MP. |
43 | */ |
44 | |
45 | static inline int get_current_cpu(ARMMPTimerState *s) |
46 | { |
47 | int cpu_id = current_cpu ? current_cpu->cpu_index : 0; |
48 | |
49 | if (cpu_id >= s->num_cpu) { |
50 | hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n" , |
51 | s->num_cpu, cpu_id); |
52 | } |
53 | |
54 | return cpu_id; |
55 | } |
56 | |
57 | static inline void timerblock_update_irq(TimerBlock *tb) |
58 | { |
59 | qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); |
60 | } |
61 | |
62 | /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ |
63 | static inline uint32_t timerblock_scale(uint32_t control) |
64 | { |
65 | return (((control >> 8) & 0xff) + 1) * 10; |
66 | } |
67 | |
68 | static inline void timerblock_set_count(struct ptimer_state *timer, |
69 | uint32_t control, uint64_t *count) |
70 | { |
71 | /* PTimer would trigger interrupt for periodic timer when counter set |
72 | * to 0, MPtimer under certain condition only. |
73 | */ |
74 | if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) { |
75 | *count = ptimer_get_limit(timer); |
76 | } |
77 | ptimer_set_count(timer, *count); |
78 | } |
79 | |
80 | static inline void timerblock_run(struct ptimer_state *timer, |
81 | uint32_t control, uint32_t load) |
82 | { |
83 | if ((control & 1) && ((control & 0xff00) || load != 0)) { |
84 | ptimer_run(timer, !(control & 2)); |
85 | } |
86 | } |
87 | |
88 | static void timerblock_tick(void *opaque) |
89 | { |
90 | TimerBlock *tb = (TimerBlock *)opaque; |
91 | /* Periodic timer with load = 0 and prescaler != 0 would re-trigger |
92 | * IRQ after one period, otherwise it either stops or wraps around. |
93 | */ |
94 | if ((tb->control & 2) && (tb->control & 0xff00) == 0 && |
95 | ptimer_get_limit(tb->timer) == 0) { |
96 | ptimer_stop(tb->timer); |
97 | } |
98 | tb->status = 1; |
99 | timerblock_update_irq(tb); |
100 | } |
101 | |
102 | static uint64_t timerblock_read(void *opaque, hwaddr addr, |
103 | unsigned size) |
104 | { |
105 | TimerBlock *tb = (TimerBlock *)opaque; |
106 | switch (addr) { |
107 | case 0: /* Load */ |
108 | return ptimer_get_limit(tb->timer); |
109 | case 4: /* Counter. */ |
110 | return ptimer_get_count(tb->timer); |
111 | case 8: /* Control. */ |
112 | return tb->control; |
113 | case 12: /* Interrupt status. */ |
114 | return tb->status; |
115 | default: |
116 | return 0; |
117 | } |
118 | } |
119 | |
120 | static void timerblock_write(void *opaque, hwaddr addr, |
121 | uint64_t value, unsigned size) |
122 | { |
123 | TimerBlock *tb = (TimerBlock *)opaque; |
124 | uint32_t control = tb->control; |
125 | switch (addr) { |
126 | case 0: /* Load */ |
127 | /* Setting load to 0 stops the timer without doing the tick if |
128 | * prescaler = 0. |
129 | */ |
130 | if ((control & 1) && (control & 0xff00) == 0 && value == 0) { |
131 | ptimer_stop(tb->timer); |
132 | } |
133 | ptimer_set_limit(tb->timer, value, 1); |
134 | timerblock_run(tb->timer, control, value); |
135 | break; |
136 | case 4: /* Counter. */ |
137 | /* Setting counter to 0 stops the one-shot timer, or periodic with |
138 | * load = 0, without doing the tick if prescaler = 0. |
139 | */ |
140 | if ((control & 1) && (control & 0xff00) == 0 && value == 0 && |
141 | (!(control & 2) || ptimer_get_limit(tb->timer) == 0)) { |
142 | ptimer_stop(tb->timer); |
143 | } |
144 | timerblock_set_count(tb->timer, control, &value); |
145 | timerblock_run(tb->timer, control, value); |
146 | break; |
147 | case 8: /* Control. */ |
148 | if ((control & 3) != (value & 3)) { |
149 | ptimer_stop(tb->timer); |
150 | } |
151 | if ((control & 0xff00) != (value & 0xff00)) { |
152 | ptimer_set_period(tb->timer, timerblock_scale(value)); |
153 | } |
154 | if (value & 1) { |
155 | uint64_t count = ptimer_get_count(tb->timer); |
156 | /* Re-load periodic timer counter if needed. */ |
157 | if ((value & 2) && count == 0) { |
158 | timerblock_set_count(tb->timer, value, &count); |
159 | } |
160 | timerblock_run(tb->timer, value, count); |
161 | } |
162 | tb->control = value; |
163 | break; |
164 | case 12: /* Interrupt status. */ |
165 | tb->status &= ~value; |
166 | timerblock_update_irq(tb); |
167 | break; |
168 | } |
169 | } |
170 | |
171 | /* Wrapper functions to implement the "read timer/watchdog for |
172 | * the current CPU" memory regions. |
173 | */ |
174 | static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, |
175 | unsigned size) |
176 | { |
177 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
178 | int id = get_current_cpu(s); |
179 | return timerblock_read(&s->timerblock[id], addr, size); |
180 | } |
181 | |
182 | static void arm_thistimer_write(void *opaque, hwaddr addr, |
183 | uint64_t value, unsigned size) |
184 | { |
185 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
186 | int id = get_current_cpu(s); |
187 | timerblock_write(&s->timerblock[id], addr, value, size); |
188 | } |
189 | |
190 | static const MemoryRegionOps arm_thistimer_ops = { |
191 | .read = arm_thistimer_read, |
192 | .write = arm_thistimer_write, |
193 | .valid = { |
194 | .min_access_size = 4, |
195 | .max_access_size = 4, |
196 | }, |
197 | .endianness = DEVICE_NATIVE_ENDIAN, |
198 | }; |
199 | |
200 | static const MemoryRegionOps timerblock_ops = { |
201 | .read = timerblock_read, |
202 | .write = timerblock_write, |
203 | .valid = { |
204 | .min_access_size = 4, |
205 | .max_access_size = 4, |
206 | }, |
207 | .endianness = DEVICE_NATIVE_ENDIAN, |
208 | }; |
209 | |
210 | static void timerblock_reset(TimerBlock *tb) |
211 | { |
212 | tb->control = 0; |
213 | tb->status = 0; |
214 | if (tb->timer) { |
215 | ptimer_stop(tb->timer); |
216 | ptimer_set_limit(tb->timer, 0, 1); |
217 | ptimer_set_period(tb->timer, timerblock_scale(0)); |
218 | } |
219 | } |
220 | |
221 | static void arm_mptimer_reset(DeviceState *dev) |
222 | { |
223 | ARMMPTimerState *s = ARM_MPTIMER(dev); |
224 | int i; |
225 | |
226 | for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { |
227 | timerblock_reset(&s->timerblock[i]); |
228 | } |
229 | } |
230 | |
231 | static void arm_mptimer_init(Object *obj) |
232 | { |
233 | ARMMPTimerState *s = ARM_MPTIMER(obj); |
234 | |
235 | memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s, |
236 | "arm_mptimer_timer" , 0x20); |
237 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); |
238 | } |
239 | |
240 | static void arm_mptimer_realize(DeviceState *dev, Error **errp) |
241 | { |
242 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
243 | ARMMPTimerState *s = ARM_MPTIMER(dev); |
244 | int i; |
245 | |
246 | if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) { |
247 | error_setg(errp, "num-cpu must be between 1 and %d" , |
248 | ARM_MPTIMER_MAX_CPUS); |
249 | return; |
250 | } |
251 | /* We implement one timer block per CPU, and expose multiple MMIO regions: |
252 | * * region 0 is "timer for this core" |
253 | * * region 1 is "timer for core 0" |
254 | * * region 2 is "timer for core 1" |
255 | * and so on. |
256 | * The outgoing interrupt lines are |
257 | * * timer for core 0 |
258 | * * timer for core 1 |
259 | * and so on. |
260 | */ |
261 | for (i = 0; i < s->num_cpu; i++) { |
262 | TimerBlock *tb = &s->timerblock[i]; |
263 | QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); |
264 | tb->timer = ptimer_init(bh, PTIMER_POLICY); |
265 | sysbus_init_irq(sbd, &tb->irq); |
266 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, |
267 | "arm_mptimer_timerblock" , 0x20); |
268 | sysbus_init_mmio(sbd, &tb->iomem); |
269 | } |
270 | } |
271 | |
272 | static const VMStateDescription vmstate_timerblock = { |
273 | .name = "arm_mptimer_timerblock" , |
274 | .version_id = 3, |
275 | .minimum_version_id = 3, |
276 | .fields = (VMStateField[]) { |
277 | VMSTATE_UINT32(control, TimerBlock), |
278 | VMSTATE_UINT32(status, TimerBlock), |
279 | VMSTATE_PTIMER(timer, TimerBlock), |
280 | VMSTATE_END_OF_LIST() |
281 | } |
282 | }; |
283 | |
284 | static const VMStateDescription vmstate_arm_mptimer = { |
285 | .name = "arm_mptimer" , |
286 | .version_id = 3, |
287 | .minimum_version_id = 3, |
288 | .fields = (VMStateField[]) { |
289 | VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu, |
290 | 3, vmstate_timerblock, TimerBlock), |
291 | VMSTATE_END_OF_LIST() |
292 | } |
293 | }; |
294 | |
295 | static Property arm_mptimer_properties[] = { |
296 | DEFINE_PROP_UINT32("num-cpu" , ARMMPTimerState, num_cpu, 0), |
297 | DEFINE_PROP_END_OF_LIST() |
298 | }; |
299 | |
300 | static void arm_mptimer_class_init(ObjectClass *klass, void *data) |
301 | { |
302 | DeviceClass *dc = DEVICE_CLASS(klass); |
303 | |
304 | dc->realize = arm_mptimer_realize; |
305 | dc->vmsd = &vmstate_arm_mptimer; |
306 | dc->reset = arm_mptimer_reset; |
307 | dc->props = arm_mptimer_properties; |
308 | } |
309 | |
310 | static const TypeInfo arm_mptimer_info = { |
311 | .name = TYPE_ARM_MPTIMER, |
312 | .parent = TYPE_SYS_BUS_DEVICE, |
313 | .instance_size = sizeof(ARMMPTimerState), |
314 | .instance_init = arm_mptimer_init, |
315 | .class_init = arm_mptimer_class_init, |
316 | }; |
317 | |
318 | static void arm_mptimer_register_types(void) |
319 | { |
320 | type_register_static(&arm_mptimer_info); |
321 | } |
322 | |
323 | type_init(arm_mptimer_register_types) |
324 | |