1 | /* |
2 | * STM32F2XX Timer |
3 | * |
4 | * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "hw/irq.h" |
27 | #include "hw/qdev-properties.h" |
28 | #include "hw/timer/stm32f2xx_timer.h" |
29 | #include "migration/vmstate.h" |
30 | #include "qemu/log.h" |
31 | #include "qemu/module.h" |
32 | |
33 | #ifndef STM_TIMER_ERR_DEBUG |
34 | #define STM_TIMER_ERR_DEBUG 0 |
35 | #endif |
36 | |
37 | #define DB_PRINT_L(lvl, fmt, args...) do { \ |
38 | if (STM_TIMER_ERR_DEBUG >= lvl) { \ |
39 | qemu_log("%s: " fmt, __func__, ## args); \ |
40 | } \ |
41 | } while (0) |
42 | |
43 | #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) |
44 | |
45 | static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); |
46 | |
47 | static void stm32f2xx_timer_interrupt(void *opaque) |
48 | { |
49 | STM32F2XXTimerState *s = opaque; |
50 | |
51 | DB_PRINT("Interrupt\n" ); |
52 | |
53 | if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { |
54 | s->tim_sr |= 1; |
55 | qemu_irq_pulse(s->irq); |
56 | stm32f2xx_timer_set_alarm(s, s->hit_time); |
57 | } |
58 | |
59 | if (s->tim_ccmr1 & (TIM_CCMR1_OC2M2 | TIM_CCMR1_OC2M1) && |
60 | !(s->tim_ccmr1 & TIM_CCMR1_OC2M0) && |
61 | s->tim_ccmr1 & TIM_CCMR1_OC2PE && |
62 | s->tim_ccer & TIM_CCER_CC2E) { |
63 | /* PWM 2 - Mode 1 */ |
64 | DB_PRINT("PWM2 Duty Cycle: %d%%\n" , |
65 | s->tim_ccr2 / (100 * (s->tim_psc + 1))); |
66 | } |
67 | } |
68 | |
69 | static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) |
70 | { |
71 | return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); |
72 | } |
73 | |
74 | static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) |
75 | { |
76 | uint64_t ticks; |
77 | int64_t now_ticks; |
78 | |
79 | if (s->tim_arr == 0) { |
80 | return; |
81 | } |
82 | |
83 | DB_PRINT("Alarm set at: 0x%x\n" , s->tim_cr1); |
84 | |
85 | now_ticks = stm32f2xx_ns_to_ticks(s, now); |
86 | ticks = s->tim_arr - (now_ticks - s->tick_offset); |
87 | |
88 | DB_PRINT("Alarm set in %d ticks\n" , (int) ticks); |
89 | |
90 | s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), |
91 | 1000000000ULL, s->freq_hz); |
92 | |
93 | timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); |
94 | DB_PRINT("Wait Time: %" PRId64 " ticks\n" , s->hit_time); |
95 | } |
96 | |
97 | static void stm32f2xx_timer_reset(DeviceState *dev) |
98 | { |
99 | STM32F2XXTimerState *s = STM32F2XXTIMER(dev); |
100 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
101 | |
102 | s->tim_cr1 = 0; |
103 | s->tim_cr2 = 0; |
104 | s->tim_smcr = 0; |
105 | s->tim_dier = 0; |
106 | s->tim_sr = 0; |
107 | s->tim_egr = 0; |
108 | s->tim_ccmr1 = 0; |
109 | s->tim_ccmr2 = 0; |
110 | s->tim_ccer = 0; |
111 | s->tim_psc = 0; |
112 | s->tim_arr = 0; |
113 | s->tim_ccr1 = 0; |
114 | s->tim_ccr2 = 0; |
115 | s->tim_ccr3 = 0; |
116 | s->tim_ccr4 = 0; |
117 | s->tim_dcr = 0; |
118 | s->tim_dmar = 0; |
119 | s->tim_or = 0; |
120 | |
121 | s->tick_offset = stm32f2xx_ns_to_ticks(s, now); |
122 | } |
123 | |
124 | static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, |
125 | unsigned size) |
126 | { |
127 | STM32F2XXTimerState *s = opaque; |
128 | |
129 | DB_PRINT("Read 0x%" HWADDR_PRIx"\n" , offset); |
130 | |
131 | switch (offset) { |
132 | case TIM_CR1: |
133 | return s->tim_cr1; |
134 | case TIM_CR2: |
135 | return s->tim_cr2; |
136 | case TIM_SMCR: |
137 | return s->tim_smcr; |
138 | case TIM_DIER: |
139 | return s->tim_dier; |
140 | case TIM_SR: |
141 | return s->tim_sr; |
142 | case TIM_EGR: |
143 | return s->tim_egr; |
144 | case TIM_CCMR1: |
145 | return s->tim_ccmr1; |
146 | case TIM_CCMR2: |
147 | return s->tim_ccmr2; |
148 | case TIM_CCER: |
149 | return s->tim_ccer; |
150 | case TIM_CNT: |
151 | return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - |
152 | s->tick_offset; |
153 | case TIM_PSC: |
154 | return s->tim_psc; |
155 | case TIM_ARR: |
156 | return s->tim_arr; |
157 | case TIM_CCR1: |
158 | return s->tim_ccr1; |
159 | case TIM_CCR2: |
160 | return s->tim_ccr2; |
161 | case TIM_CCR3: |
162 | return s->tim_ccr3; |
163 | case TIM_CCR4: |
164 | return s->tim_ccr4; |
165 | case TIM_DCR: |
166 | return s->tim_dcr; |
167 | case TIM_DMAR: |
168 | return s->tim_dmar; |
169 | case TIM_OR: |
170 | return s->tim_or; |
171 | default: |
172 | qemu_log_mask(LOG_GUEST_ERROR, |
173 | "%s: Bad offset 0x%" HWADDR_PRIx"\n" , __func__, offset); |
174 | } |
175 | |
176 | return 0; |
177 | } |
178 | |
179 | static void stm32f2xx_timer_write(void *opaque, hwaddr offset, |
180 | uint64_t val64, unsigned size) |
181 | { |
182 | STM32F2XXTimerState *s = opaque; |
183 | uint32_t value = val64; |
184 | int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
185 | uint32_t timer_val = 0; |
186 | |
187 | DB_PRINT("Write 0x%x, 0x%" HWADDR_PRIx"\n" , value, offset); |
188 | |
189 | switch (offset) { |
190 | case TIM_CR1: |
191 | s->tim_cr1 = value; |
192 | return; |
193 | case TIM_CR2: |
194 | s->tim_cr2 = value; |
195 | return; |
196 | case TIM_SMCR: |
197 | s->tim_smcr = value; |
198 | return; |
199 | case TIM_DIER: |
200 | s->tim_dier = value; |
201 | return; |
202 | case TIM_SR: |
203 | /* This is set by hardware and cleared by software */ |
204 | s->tim_sr &= value; |
205 | return; |
206 | case TIM_EGR: |
207 | s->tim_egr = value; |
208 | if (s->tim_egr & TIM_EGR_UG) { |
209 | timer_val = 0; |
210 | break; |
211 | } |
212 | return; |
213 | case TIM_CCMR1: |
214 | s->tim_ccmr1 = value; |
215 | return; |
216 | case TIM_CCMR2: |
217 | s->tim_ccmr2 = value; |
218 | return; |
219 | case TIM_CCER: |
220 | s->tim_ccer = value; |
221 | return; |
222 | case TIM_PSC: |
223 | timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; |
224 | s->tim_psc = value & 0xFFFF; |
225 | value = timer_val; |
226 | break; |
227 | case TIM_CNT: |
228 | timer_val = value; |
229 | break; |
230 | case TIM_ARR: |
231 | s->tim_arr = value; |
232 | stm32f2xx_timer_set_alarm(s, now); |
233 | return; |
234 | case TIM_CCR1: |
235 | s->tim_ccr1 = value; |
236 | return; |
237 | case TIM_CCR2: |
238 | s->tim_ccr2 = value; |
239 | return; |
240 | case TIM_CCR3: |
241 | s->tim_ccr3 = value; |
242 | return; |
243 | case TIM_CCR4: |
244 | s->tim_ccr4 = value; |
245 | return; |
246 | case TIM_DCR: |
247 | s->tim_dcr = value; |
248 | return; |
249 | case TIM_DMAR: |
250 | s->tim_dmar = value; |
251 | return; |
252 | case TIM_OR: |
253 | s->tim_or = value; |
254 | return; |
255 | default: |
256 | qemu_log_mask(LOG_GUEST_ERROR, |
257 | "%s: Bad offset 0x%" HWADDR_PRIx"\n" , __func__, offset); |
258 | return; |
259 | } |
260 | |
261 | /* This means that a register write has affected the timer in a way that |
262 | * requires a refresh of both tick_offset and the alarm. |
263 | */ |
264 | s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; |
265 | stm32f2xx_timer_set_alarm(s, now); |
266 | } |
267 | |
268 | static const MemoryRegionOps stm32f2xx_timer_ops = { |
269 | .read = stm32f2xx_timer_read, |
270 | .write = stm32f2xx_timer_write, |
271 | .endianness = DEVICE_NATIVE_ENDIAN, |
272 | }; |
273 | |
274 | static const VMStateDescription vmstate_stm32f2xx_timer = { |
275 | .name = TYPE_STM32F2XX_TIMER, |
276 | .version_id = 1, |
277 | .minimum_version_id = 1, |
278 | .fields = (VMStateField[]) { |
279 | VMSTATE_INT64(tick_offset, STM32F2XXTimerState), |
280 | VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), |
281 | VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), |
282 | VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), |
283 | VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), |
284 | VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), |
285 | VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), |
286 | VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), |
287 | VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), |
288 | VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), |
289 | VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), |
290 | VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), |
291 | VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), |
292 | VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), |
293 | VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), |
294 | VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), |
295 | VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), |
296 | VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), |
297 | VMSTATE_UINT32(tim_or, STM32F2XXTimerState), |
298 | VMSTATE_END_OF_LIST() |
299 | } |
300 | }; |
301 | |
302 | static Property stm32f2xx_timer_properties[] = { |
303 | DEFINE_PROP_UINT64("clock-frequency" , struct STM32F2XXTimerState, |
304 | freq_hz, 1000000000), |
305 | DEFINE_PROP_END_OF_LIST(), |
306 | }; |
307 | |
308 | static void stm32f2xx_timer_init(Object *obj) |
309 | { |
310 | STM32F2XXTimerState *s = STM32F2XXTIMER(obj); |
311 | |
312 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); |
313 | |
314 | memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, |
315 | "stm32f2xx_timer" , 0x400); |
316 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); |
317 | |
318 | s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); |
319 | } |
320 | |
321 | static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) |
322 | { |
323 | DeviceClass *dc = DEVICE_CLASS(klass); |
324 | |
325 | dc->reset = stm32f2xx_timer_reset; |
326 | dc->props = stm32f2xx_timer_properties; |
327 | dc->vmsd = &vmstate_stm32f2xx_timer; |
328 | } |
329 | |
330 | static const TypeInfo stm32f2xx_timer_info = { |
331 | .name = TYPE_STM32F2XX_TIMER, |
332 | .parent = TYPE_SYS_BUS_DEVICE, |
333 | .instance_size = sizeof(STM32F2XXTimerState), |
334 | .instance_init = stm32f2xx_timer_init, |
335 | .class_init = stm32f2xx_timer_class_init, |
336 | }; |
337 | |
338 | static void stm32f2xx_timer_register_types(void) |
339 | { |
340 | type_register_static(&stm32f2xx_timer_info); |
341 | } |
342 | |
343 | type_init(stm32f2xx_timer_register_types) |
344 | |