1/*
2 * QEMU model of the Xilinx timer block.
3 *
4 * Copyright (c) 2009 Edgar E. Iglesias.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "hw/irq.h"
28#include "hw/ptimer.h"
29#include "hw/qdev-properties.h"
30#include "qemu/log.h"
31#include "qemu/main-loop.h"
32#include "qemu/module.h"
33
34#define D(x)
35
36#define R_TCSR 0
37#define R_TLR 1
38#define R_TCR 2
39#define R_MAX 4
40
41#define TCSR_MDT (1<<0)
42#define TCSR_UDT (1<<1)
43#define TCSR_GENT (1<<2)
44#define TCSR_CAPT (1<<3)
45#define TCSR_ARHT (1<<4)
46#define TCSR_LOAD (1<<5)
47#define TCSR_ENIT (1<<6)
48#define TCSR_ENT (1<<7)
49#define TCSR_TINT (1<<8)
50#define TCSR_PWMA (1<<9)
51#define TCSR_ENALL (1<<10)
52
53struct xlx_timer
54{
55 QEMUBH *bh;
56 ptimer_state *ptimer;
57 void *parent;
58 int nr; /* for debug. */
59
60 unsigned long timer_div;
61
62 uint32_t regs[R_MAX];
63};
64
65#define TYPE_XILINX_TIMER "xlnx.xps-timer"
66#define XILINX_TIMER(obj) \
67 OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
68
69struct timerblock
70{
71 SysBusDevice parent_obj;
72
73 MemoryRegion mmio;
74 qemu_irq irq;
75 uint8_t one_timer_only;
76 uint32_t freq_hz;
77 struct xlx_timer *timers;
78};
79
80static inline unsigned int num_timers(struct timerblock *t)
81{
82 return 2 - t->one_timer_only;
83}
84
85static inline unsigned int timer_from_addr(hwaddr addr)
86{
87 /* Timers get a 4x32bit control reg area each. */
88 return addr >> 2;
89}
90
91static void timer_update_irq(struct timerblock *t)
92{
93 unsigned int i, irq = 0;
94 uint32_t csr;
95
96 for (i = 0; i < num_timers(t); i++) {
97 csr = t->timers[i].regs[R_TCSR];
98 irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
99 }
100
101 /* All timers within the same slave share a single IRQ line. */
102 qemu_set_irq(t->irq, !!irq);
103}
104
105static uint64_t
106timer_read(void *opaque, hwaddr addr, unsigned int size)
107{
108 struct timerblock *t = opaque;
109 struct xlx_timer *xt;
110 uint32_t r = 0;
111 unsigned int timer;
112
113 addr >>= 2;
114 timer = timer_from_addr(addr);
115 xt = &t->timers[timer];
116 /* Further decoding to address a specific timers reg. */
117 addr &= 0x3;
118 switch (addr)
119 {
120 case R_TCR:
121 r = ptimer_get_count(xt->ptimer);
122 if (!(xt->regs[R_TCSR] & TCSR_UDT))
123 r = ~r;
124 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
125 timer, r, xt->regs[R_TCSR] & TCSR_UDT));
126 break;
127 default:
128 if (addr < ARRAY_SIZE(xt->regs))
129 r = xt->regs[addr];
130 break;
131
132 }
133 D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
134 return r;
135}
136
137static void timer_enable(struct xlx_timer *xt)
138{
139 uint64_t count;
140
141 D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
142 xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
143
144 ptimer_stop(xt->ptimer);
145
146 if (xt->regs[R_TCSR] & TCSR_UDT)
147 count = xt->regs[R_TLR];
148 else
149 count = ~0 - xt->regs[R_TLR];
150 ptimer_set_limit(xt->ptimer, count, 1);
151 ptimer_run(xt->ptimer, 1);
152}
153
154static void
155timer_write(void *opaque, hwaddr addr,
156 uint64_t val64, unsigned int size)
157{
158 struct timerblock *t = opaque;
159 struct xlx_timer *xt;
160 unsigned int timer;
161 uint32_t value = val64;
162
163 addr >>= 2;
164 timer = timer_from_addr(addr);
165 xt = &t->timers[timer];
166 D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
167 __func__, addr * 4, value, timer, addr & 3));
168 /* Further decoding to address a specific timers reg. */
169 addr &= 3;
170 switch (addr)
171 {
172 case R_TCSR:
173 if (value & TCSR_TINT)
174 value &= ~TCSR_TINT;
175
176 xt->regs[addr] = value & 0x7ff;
177 if (value & TCSR_ENT)
178 timer_enable(xt);
179 break;
180
181 default:
182 if (addr < ARRAY_SIZE(xt->regs))
183 xt->regs[addr] = value;
184 break;
185 }
186 timer_update_irq(t);
187}
188
189static const MemoryRegionOps timer_ops = {
190 .read = timer_read,
191 .write = timer_write,
192 .endianness = DEVICE_NATIVE_ENDIAN,
193 .valid = {
194 .min_access_size = 4,
195 .max_access_size = 4
196 }
197};
198
199static void timer_hit(void *opaque)
200{
201 struct xlx_timer *xt = opaque;
202 struct timerblock *t = xt->parent;
203 D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
204 xt->regs[R_TCSR] |= TCSR_TINT;
205
206 if (xt->regs[R_TCSR] & TCSR_ARHT)
207 timer_enable(xt);
208 timer_update_irq(t);
209}
210
211static void xilinx_timer_realize(DeviceState *dev, Error **errp)
212{
213 struct timerblock *t = XILINX_TIMER(dev);
214 unsigned int i;
215
216 /* Init all the ptimers. */
217 t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
218 for (i = 0; i < num_timers(t); i++) {
219 struct xlx_timer *xt = &t->timers[i];
220
221 xt->parent = t;
222 xt->nr = i;
223 xt->bh = qemu_bh_new(timer_hit, xt);
224 xt->ptimer = ptimer_init(xt->bh, PTIMER_POLICY_DEFAULT);
225 ptimer_set_freq(xt->ptimer, t->freq_hz);
226 }
227
228 memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
229 R_MAX * 4 * num_timers(t));
230 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->mmio);
231}
232
233static void xilinx_timer_init(Object *obj)
234{
235 struct timerblock *t = XILINX_TIMER(obj);
236
237 /* All timers share a single irq line. */
238 sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq);
239}
240
241static Property xilinx_timer_properties[] = {
242 DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
243 62 * 1000000),
244 DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
245 DEFINE_PROP_END_OF_LIST(),
246};
247
248static void xilinx_timer_class_init(ObjectClass *klass, void *data)
249{
250 DeviceClass *dc = DEVICE_CLASS(klass);
251
252 dc->realize = xilinx_timer_realize;
253 dc->props = xilinx_timer_properties;
254}
255
256static const TypeInfo xilinx_timer_info = {
257 .name = TYPE_XILINX_TIMER,
258 .parent = TYPE_SYS_BUS_DEVICE,
259 .instance_size = sizeof(struct timerblock),
260 .instance_init = xilinx_timer_init,
261 .class_init = xilinx_timer_class_init,
262};
263
264static void xilinx_timer_register_types(void)
265{
266 type_register_static(&xilinx_timer_info);
267}
268
269type_init(xilinx_timer_register_types)
270