1 | /* |
2 | * Texas Instruments OMAP processors. |
3 | * |
4 | * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org> |
5 | * |
6 | * This program is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU General Public License as |
8 | * published by the Free Software Foundation; either version 2 or |
9 | * (at your option) version 3 of the License. |
10 | * |
11 | * This program is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
14 | * GNU General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU General Public License along |
17 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #ifndef HW_ARM_OMAP_H |
21 | #define HW_ARM_OMAP_H |
22 | |
23 | #include "exec/memory.h" |
24 | #include "hw/input/tsc2xxx.h" |
25 | #include "target/arm/cpu-qom.h" |
26 | #include "qemu/log.h" |
27 | |
28 | # define OMAP_EMIFS_BASE 0x00000000 |
29 | # define OMAP2_Q0_BASE 0x00000000 |
30 | # define OMAP_CS0_BASE 0x00000000 |
31 | # define OMAP_CS1_BASE 0x04000000 |
32 | # define OMAP_CS2_BASE 0x08000000 |
33 | # define OMAP_CS3_BASE 0x0c000000 |
34 | # define OMAP_EMIFF_BASE 0x10000000 |
35 | # define OMAP_IMIF_BASE 0x20000000 |
36 | # define OMAP_LOCALBUS_BASE 0x30000000 |
37 | # define OMAP2_Q1_BASE 0x40000000 |
38 | # define OMAP2_L4_BASE 0x48000000 |
39 | # define OMAP2_SRAM_BASE 0x40200000 |
40 | # define OMAP2_L3_BASE 0x68000000 |
41 | # define OMAP2_Q2_BASE 0x80000000 |
42 | # define OMAP2_Q3_BASE 0xc0000000 |
43 | # define OMAP_MPUI_BASE 0xe1000000 |
44 | |
45 | # define OMAP730_SRAM_SIZE 0x00032000 |
46 | # define OMAP15XX_SRAM_SIZE 0x00030000 |
47 | # define OMAP16XX_SRAM_SIZE 0x00004000 |
48 | # define OMAP1611_SRAM_SIZE 0x0003e800 |
49 | # define OMAP242X_SRAM_SIZE 0x000a0000 |
50 | # define OMAP243X_SRAM_SIZE 0x00010000 |
51 | # define OMAP_CS0_SIZE 0x04000000 |
52 | # define OMAP_CS1_SIZE 0x04000000 |
53 | # define OMAP_CS2_SIZE 0x04000000 |
54 | # define OMAP_CS3_SIZE 0x04000000 |
55 | |
56 | /* omap_clk.c */ |
57 | struct omap_mpu_state_s; |
58 | typedef struct clk *omap_clk; |
59 | omap_clk omap_findclk(struct omap_mpu_state_s *mpu, const char *name); |
60 | void omap_clk_init(struct omap_mpu_state_s *mpu); |
61 | void omap_clk_adduser(struct clk *clk, qemu_irq user); |
62 | void omap_clk_get(omap_clk clk); |
63 | void omap_clk_put(omap_clk clk); |
64 | void omap_clk_onoff(omap_clk clk, int on); |
65 | void omap_clk_canidle(omap_clk clk, int can); |
66 | void omap_clk_setrate(omap_clk clk, int divide, int multiply); |
67 | int64_t omap_clk_getrate(omap_clk clk); |
68 | void omap_clk_reparent(omap_clk clk, omap_clk parent); |
69 | |
70 | /* OMAP2 l4 Interconnect */ |
71 | struct omap_l4_s; |
72 | struct omap_l4_region_s { |
73 | hwaddr offset; |
74 | size_t size; |
75 | int access; |
76 | }; |
77 | struct omap_l4_agent_info_s { |
78 | int ta; |
79 | int region; |
80 | int regions; |
81 | int ta_region; |
82 | }; |
83 | struct omap_target_agent_s { |
84 | MemoryRegion iomem; |
85 | struct omap_l4_s *bus; |
86 | int regions; |
87 | const struct omap_l4_region_s *start; |
88 | hwaddr base; |
89 | uint32_t component; |
90 | uint32_t control; |
91 | uint32_t status; |
92 | }; |
93 | struct omap_l4_s *omap_l4_init(MemoryRegion *address_space, |
94 | hwaddr base, int ta_num); |
95 | |
96 | struct omap_target_agent_s; |
97 | struct omap_target_agent_s *omap_l4ta_get( |
98 | struct omap_l4_s *bus, |
99 | const struct omap_l4_region_s *regions, |
100 | const struct omap_l4_agent_info_s *agents, |
101 | int cs); |
102 | hwaddr omap_l4_attach(struct omap_target_agent_s *ta, |
103 | int region, MemoryRegion *mr); |
104 | hwaddr omap_l4_region_base(struct omap_target_agent_s *ta, |
105 | int region); |
106 | hwaddr omap_l4_region_size(struct omap_target_agent_s *ta, |
107 | int region); |
108 | |
109 | /* OMAP2 SDRAM controller */ |
110 | struct omap_sdrc_s; |
111 | struct omap_sdrc_s *omap_sdrc_init(MemoryRegion *sysmem, |
112 | hwaddr base); |
113 | void omap_sdrc_reset(struct omap_sdrc_s *s); |
114 | |
115 | /* OMAP2 general purpose memory controller */ |
116 | struct omap_gpmc_s; |
117 | struct omap_gpmc_s *omap_gpmc_init(struct omap_mpu_state_s *mpu, |
118 | hwaddr base, |
119 | qemu_irq irq, qemu_irq drq); |
120 | void omap_gpmc_reset(struct omap_gpmc_s *s); |
121 | void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, MemoryRegion *iomem); |
122 | void omap_gpmc_attach_nand(struct omap_gpmc_s *s, int cs, DeviceState *nand); |
123 | |
124 | /* |
125 | * Common IRQ numbers for level 1 interrupt handler |
126 | * See /usr/include/asm-arm/arch-omap/irqs.h in Linux. |
127 | */ |
128 | # define OMAP_INT_CAMERA 1 |
129 | # define OMAP_INT_FIQ 3 |
130 | # define OMAP_INT_RTDX 6 |
131 | # define OMAP_INT_DSP_MMU_ABORT 7 |
132 | # define OMAP_INT_HOST 8 |
133 | # define OMAP_INT_ABORT 9 |
134 | # define OMAP_INT_BRIDGE_PRIV 13 |
135 | # define OMAP_INT_GPIO_BANK1 14 |
136 | # define OMAP_INT_UART3 15 |
137 | # define OMAP_INT_TIMER3 16 |
138 | # define OMAP_INT_DMA_CH0_6 19 |
139 | # define OMAP_INT_DMA_CH1_7 20 |
140 | # define OMAP_INT_DMA_CH2_8 21 |
141 | # define OMAP_INT_DMA_CH3 22 |
142 | # define OMAP_INT_DMA_CH4 23 |
143 | # define OMAP_INT_DMA_CH5 24 |
144 | # define OMAP_INT_DMA_LCD 25 |
145 | # define OMAP_INT_TIMER1 26 |
146 | # define OMAP_INT_WD_TIMER 27 |
147 | # define OMAP_INT_BRIDGE_PUB 28 |
148 | # define OMAP_INT_TIMER2 30 |
149 | # define OMAP_INT_LCD_CTRL 31 |
150 | |
151 | /* |
152 | * Common OMAP-15xx IRQ numbers for level 1 interrupt handler |
153 | */ |
154 | # define OMAP_INT_15XX_IH2_IRQ 0 |
155 | # define OMAP_INT_15XX_LB_MMU 17 |
156 | # define OMAP_INT_15XX_LOCAL_BUS 29 |
157 | |
158 | /* |
159 | * OMAP-1510 specific IRQ numbers for level 1 interrupt handler |
160 | */ |
161 | # define OMAP_INT_1510_SPI_TX 4 |
162 | # define OMAP_INT_1510_SPI_RX 5 |
163 | # define OMAP_INT_1510_DSP_MAILBOX1 10 |
164 | # define OMAP_INT_1510_DSP_MAILBOX2 11 |
165 | |
166 | /* |
167 | * OMAP-310 specific IRQ numbers for level 1 interrupt handler |
168 | */ |
169 | # define OMAP_INT_310_McBSP2_TX 4 |
170 | # define OMAP_INT_310_McBSP2_RX 5 |
171 | # define OMAP_INT_310_HSB_MAILBOX1 12 |
172 | # define OMAP_INT_310_HSAB_MMU 18 |
173 | |
174 | /* |
175 | * OMAP-1610 specific IRQ numbers for level 1 interrupt handler |
176 | */ |
177 | # define OMAP_INT_1610_IH2_IRQ 0 |
178 | # define OMAP_INT_1610_IH2_FIQ 2 |
179 | # define OMAP_INT_1610_McBSP2_TX 4 |
180 | # define OMAP_INT_1610_McBSP2_RX 5 |
181 | # define OMAP_INT_1610_DSP_MAILBOX1 10 |
182 | # define OMAP_INT_1610_DSP_MAILBOX2 11 |
183 | # define OMAP_INT_1610_LCD_LINE 12 |
184 | # define OMAP_INT_1610_GPTIMER1 17 |
185 | # define OMAP_INT_1610_GPTIMER2 18 |
186 | # define OMAP_INT_1610_SSR_FIFO_0 29 |
187 | |
188 | /* |
189 | * OMAP-730 specific IRQ numbers for level 1 interrupt handler |
190 | */ |
191 | # define OMAP_INT_730_IH2_FIQ 0 |
192 | # define OMAP_INT_730_IH2_IRQ 1 |
193 | # define OMAP_INT_730_USB_NON_ISO 2 |
194 | # define OMAP_INT_730_USB_ISO 3 |
195 | # define OMAP_INT_730_ICR 4 |
196 | # define OMAP_INT_730_EAC 5 |
197 | # define OMAP_INT_730_GPIO_BANK1 6 |
198 | # define OMAP_INT_730_GPIO_BANK2 7 |
199 | # define OMAP_INT_730_GPIO_BANK3 8 |
200 | # define OMAP_INT_730_McBSP2TX 10 |
201 | # define OMAP_INT_730_McBSP2RX 11 |
202 | # define OMAP_INT_730_McBSP2RX_OVF 12 |
203 | # define OMAP_INT_730_LCD_LINE 14 |
204 | # define OMAP_INT_730_GSM_PROTECT 15 |
205 | # define OMAP_INT_730_TIMER3 16 |
206 | # define OMAP_INT_730_GPIO_BANK5 17 |
207 | # define OMAP_INT_730_GPIO_BANK6 18 |
208 | # define OMAP_INT_730_SPGIO_WR 29 |
209 | |
210 | /* |
211 | * Common IRQ numbers for level 2 interrupt handler |
212 | */ |
213 | # define OMAP_INT_KEYBOARD 1 |
214 | # define OMAP_INT_uWireTX 2 |
215 | # define OMAP_INT_uWireRX 3 |
216 | # define OMAP_INT_I2C 4 |
217 | # define OMAP_INT_MPUIO 5 |
218 | # define OMAP_INT_USB_HHC_1 6 |
219 | # define OMAP_INT_McBSP3TX 10 |
220 | # define OMAP_INT_McBSP3RX 11 |
221 | # define OMAP_INT_McBSP1TX 12 |
222 | # define OMAP_INT_McBSP1RX 13 |
223 | # define OMAP_INT_UART1 14 |
224 | # define OMAP_INT_UART2 15 |
225 | # define OMAP_INT_USB_W2FC 20 |
226 | # define OMAP_INT_1WIRE 21 |
227 | # define OMAP_INT_OS_TIMER 22 |
228 | # define OMAP_INT_OQN 23 |
229 | # define OMAP_INT_GAUGE_32K 24 |
230 | # define OMAP_INT_RTC_TIMER 25 |
231 | # define OMAP_INT_RTC_ALARM 26 |
232 | # define OMAP_INT_DSP_MMU 28 |
233 | |
234 | /* |
235 | * OMAP-1510 specific IRQ numbers for level 2 interrupt handler |
236 | */ |
237 | # define OMAP_INT_1510_BT_MCSI1TX 16 |
238 | # define OMAP_INT_1510_BT_MCSI1RX 17 |
239 | # define OMAP_INT_1510_SoSSI_MATCH 19 |
240 | # define OMAP_INT_1510_MEM_STICK 27 |
241 | # define OMAP_INT_1510_COM_SPI_RO 31 |
242 | |
243 | /* |
244 | * OMAP-310 specific IRQ numbers for level 2 interrupt handler |
245 | */ |
246 | # define OMAP_INT_310_FAC 0 |
247 | # define OMAP_INT_310_USB_HHC_2 7 |
248 | # define OMAP_INT_310_MCSI1_FE 16 |
249 | # define OMAP_INT_310_MCSI2_FE 17 |
250 | # define OMAP_INT_310_USB_W2FC_ISO 29 |
251 | # define OMAP_INT_310_USB_W2FC_NON_ISO 30 |
252 | # define OMAP_INT_310_McBSP2RX_OF 31 |
253 | |
254 | /* |
255 | * OMAP-1610 specific IRQ numbers for level 2 interrupt handler |
256 | */ |
257 | # define OMAP_INT_1610_FAC 0 |
258 | # define OMAP_INT_1610_USB_HHC_2 7 |
259 | # define OMAP_INT_1610_USB_OTG 8 |
260 | # define OMAP_INT_1610_SoSSI 9 |
261 | # define OMAP_INT_1610_BT_MCSI1TX 16 |
262 | # define OMAP_INT_1610_BT_MCSI1RX 17 |
263 | # define OMAP_INT_1610_SoSSI_MATCH 19 |
264 | # define OMAP_INT_1610_MEM_STICK 27 |
265 | # define OMAP_INT_1610_McBSP2RX_OF 31 |
266 | # define OMAP_INT_1610_STI 32 |
267 | # define OMAP_INT_1610_STI_WAKEUP 33 |
268 | # define OMAP_INT_1610_GPTIMER3 34 |
269 | # define OMAP_INT_1610_GPTIMER4 35 |
270 | # define OMAP_INT_1610_GPTIMER5 36 |
271 | # define OMAP_INT_1610_GPTIMER6 37 |
272 | # define OMAP_INT_1610_GPTIMER7 38 |
273 | # define OMAP_INT_1610_GPTIMER8 39 |
274 | # define OMAP_INT_1610_GPIO_BANK2 40 |
275 | # define OMAP_INT_1610_GPIO_BANK3 41 |
276 | # define OMAP_INT_1610_MMC2 42 |
277 | # define OMAP_INT_1610_CF 43 |
278 | # define OMAP_INT_1610_WAKE_UP_REQ 46 |
279 | # define OMAP_INT_1610_GPIO_BANK4 48 |
280 | # define OMAP_INT_1610_SPI 49 |
281 | # define OMAP_INT_1610_DMA_CH6 53 |
282 | # define OMAP_INT_1610_DMA_CH7 54 |
283 | # define OMAP_INT_1610_DMA_CH8 55 |
284 | # define OMAP_INT_1610_DMA_CH9 56 |
285 | # define OMAP_INT_1610_DMA_CH10 57 |
286 | # define OMAP_INT_1610_DMA_CH11 58 |
287 | # define OMAP_INT_1610_DMA_CH12 59 |
288 | # define OMAP_INT_1610_DMA_CH13 60 |
289 | # define OMAP_INT_1610_DMA_CH14 61 |
290 | # define OMAP_INT_1610_DMA_CH15 62 |
291 | # define OMAP_INT_1610_NAND 63 |
292 | |
293 | /* |
294 | * OMAP-730 specific IRQ numbers for level 2 interrupt handler |
295 | */ |
296 | # define OMAP_INT_730_HW_ERRORS 0 |
297 | # define OMAP_INT_730_NFIQ_PWR_FAIL 1 |
298 | # define OMAP_INT_730_CFCD 2 |
299 | # define OMAP_INT_730_CFIREQ 3 |
300 | # define OMAP_INT_730_I2C 4 |
301 | # define OMAP_INT_730_PCC 5 |
302 | # define OMAP_INT_730_MPU_EXT_NIRQ 6 |
303 | # define OMAP_INT_730_SPI_100K_1 7 |
304 | # define OMAP_INT_730_SYREN_SPI 8 |
305 | # define OMAP_INT_730_VLYNQ 9 |
306 | # define OMAP_INT_730_GPIO_BANK4 10 |
307 | # define OMAP_INT_730_McBSP1TX 11 |
308 | # define OMAP_INT_730_McBSP1RX 12 |
309 | # define OMAP_INT_730_McBSP1RX_OF 13 |
310 | # define OMAP_INT_730_UART_MODEM_IRDA_2 14 |
311 | # define OMAP_INT_730_UART_MODEM_1 15 |
312 | # define OMAP_INT_730_MCSI 16 |
313 | # define OMAP_INT_730_uWireTX 17 |
314 | # define OMAP_INT_730_uWireRX 18 |
315 | # define OMAP_INT_730_SMC_CD 19 |
316 | # define OMAP_INT_730_SMC_IREQ 20 |
317 | # define OMAP_INT_730_HDQ_1WIRE 21 |
318 | # define OMAP_INT_730_TIMER32K 22 |
319 | # define OMAP_INT_730_MMC_SDIO 23 |
320 | # define OMAP_INT_730_UPLD 24 |
321 | # define OMAP_INT_730_USB_HHC_1 27 |
322 | # define OMAP_INT_730_USB_HHC_2 28 |
323 | # define OMAP_INT_730_USB_GENI 29 |
324 | # define OMAP_INT_730_USB_OTG 30 |
325 | # define OMAP_INT_730_CAMERA_IF 31 |
326 | # define OMAP_INT_730_RNG 32 |
327 | # define OMAP_INT_730_DUAL_MODE_TIMER 33 |
328 | # define OMAP_INT_730_DBB_RF_EN 34 |
329 | # define OMAP_INT_730_MPUIO_KEYPAD 35 |
330 | # define OMAP_INT_730_SHA1_MD5 36 |
331 | # define OMAP_INT_730_SPI_100K_2 37 |
332 | # define OMAP_INT_730_RNG_IDLE 38 |
333 | # define OMAP_INT_730_MPUIO 39 |
334 | # define OMAP_INT_730_LLPC_LCD_CTRL_OFF 40 |
335 | # define OMAP_INT_730_LLPC_OE_FALLING 41 |
336 | # define OMAP_INT_730_LLPC_OE_RISING 42 |
337 | # define OMAP_INT_730_LLPC_VSYNC 43 |
338 | # define OMAP_INT_730_WAKE_UP_REQ 46 |
339 | # define OMAP_INT_730_DMA_CH6 53 |
340 | # define OMAP_INT_730_DMA_CH7 54 |
341 | # define OMAP_INT_730_DMA_CH8 55 |
342 | # define OMAP_INT_730_DMA_CH9 56 |
343 | # define OMAP_INT_730_DMA_CH10 57 |
344 | # define OMAP_INT_730_DMA_CH11 58 |
345 | # define OMAP_INT_730_DMA_CH12 59 |
346 | # define OMAP_INT_730_DMA_CH13 60 |
347 | # define OMAP_INT_730_DMA_CH14 61 |
348 | # define OMAP_INT_730_DMA_CH15 62 |
349 | # define OMAP_INT_730_NAND 63 |
350 | |
351 | /* |
352 | * OMAP-24xx common IRQ numbers |
353 | */ |
354 | # define OMAP_INT_24XX_STI 4 |
355 | # define OMAP_INT_24XX_SYS_NIRQ 7 |
356 | # define OMAP_INT_24XX_L3_IRQ 10 |
357 | # define OMAP_INT_24XX_PRCM_MPU_IRQ 11 |
358 | # define OMAP_INT_24XX_SDMA_IRQ0 12 |
359 | # define OMAP_INT_24XX_SDMA_IRQ1 13 |
360 | # define OMAP_INT_24XX_SDMA_IRQ2 14 |
361 | # define OMAP_INT_24XX_SDMA_IRQ3 15 |
362 | # define OMAP_INT_243X_MCBSP2_IRQ 16 |
363 | # define OMAP_INT_243X_MCBSP3_IRQ 17 |
364 | # define OMAP_INT_243X_MCBSP4_IRQ 18 |
365 | # define OMAP_INT_243X_MCBSP5_IRQ 19 |
366 | # define OMAP_INT_24XX_GPMC_IRQ 20 |
367 | # define OMAP_INT_24XX_GUFFAW_IRQ 21 |
368 | # define OMAP_INT_24XX_IVA_IRQ 22 |
369 | # define OMAP_INT_24XX_EAC_IRQ 23 |
370 | # define OMAP_INT_24XX_CAM_IRQ 24 |
371 | # define OMAP_INT_24XX_DSS_IRQ 25 |
372 | # define OMAP_INT_24XX_MAIL_U0_MPU 26 |
373 | # define OMAP_INT_24XX_DSP_UMA 27 |
374 | # define OMAP_INT_24XX_DSP_MMU 28 |
375 | # define OMAP_INT_24XX_GPIO_BANK1 29 |
376 | # define OMAP_INT_24XX_GPIO_BANK2 30 |
377 | # define OMAP_INT_24XX_GPIO_BANK3 31 |
378 | # define OMAP_INT_24XX_GPIO_BANK4 32 |
379 | # define OMAP_INT_243X_GPIO_BANK5 33 |
380 | # define OMAP_INT_24XX_MAIL_U3_MPU 34 |
381 | # define OMAP_INT_24XX_WDT3 35 |
382 | # define OMAP_INT_24XX_WDT4 36 |
383 | # define OMAP_INT_24XX_GPTIMER1 37 |
384 | # define OMAP_INT_24XX_GPTIMER2 38 |
385 | # define OMAP_INT_24XX_GPTIMER3 39 |
386 | # define OMAP_INT_24XX_GPTIMER4 40 |
387 | # define OMAP_INT_24XX_GPTIMER5 41 |
388 | # define OMAP_INT_24XX_GPTIMER6 42 |
389 | # define OMAP_INT_24XX_GPTIMER7 43 |
390 | # define OMAP_INT_24XX_GPTIMER8 44 |
391 | # define OMAP_INT_24XX_GPTIMER9 45 |
392 | # define OMAP_INT_24XX_GPTIMER10 46 |
393 | # define OMAP_INT_24XX_GPTIMER11 47 |
394 | # define OMAP_INT_24XX_GPTIMER12 48 |
395 | # define OMAP_INT_24XX_PKA_IRQ 50 |
396 | # define OMAP_INT_24XX_SHA1MD5_IRQ 51 |
397 | # define OMAP_INT_24XX_RNG_IRQ 52 |
398 | # define OMAP_INT_24XX_MG_IRQ 53 |
399 | # define OMAP_INT_24XX_I2C1_IRQ 56 |
400 | # define OMAP_INT_24XX_I2C2_IRQ 57 |
401 | # define OMAP_INT_24XX_MCBSP1_IRQ_TX 59 |
402 | # define OMAP_INT_24XX_MCBSP1_IRQ_RX 60 |
403 | # define OMAP_INT_24XX_MCBSP2_IRQ_TX 62 |
404 | # define OMAP_INT_24XX_MCBSP2_IRQ_RX 63 |
405 | # define OMAP_INT_243X_MCBSP1_IRQ 64 |
406 | # define OMAP_INT_24XX_MCSPI1_IRQ 65 |
407 | # define OMAP_INT_24XX_MCSPI2_IRQ 66 |
408 | # define OMAP_INT_24XX_SSI1_IRQ0 67 |
409 | # define OMAP_INT_24XX_SSI1_IRQ1 68 |
410 | # define OMAP_INT_24XX_SSI2_IRQ0 69 |
411 | # define OMAP_INT_24XX_SSI2_IRQ1 70 |
412 | # define OMAP_INT_24XX_SSI_GDD_IRQ 71 |
413 | # define OMAP_INT_24XX_UART1_IRQ 72 |
414 | # define OMAP_INT_24XX_UART2_IRQ 73 |
415 | # define OMAP_INT_24XX_UART3_IRQ 74 |
416 | # define OMAP_INT_24XX_USB_IRQ_GEN 75 |
417 | # define OMAP_INT_24XX_USB_IRQ_NISO 76 |
418 | # define OMAP_INT_24XX_USB_IRQ_ISO 77 |
419 | # define OMAP_INT_24XX_USB_IRQ_HGEN 78 |
420 | # define OMAP_INT_24XX_USB_IRQ_HSOF 79 |
421 | # define OMAP_INT_24XX_USB_IRQ_OTG 80 |
422 | # define OMAP_INT_24XX_VLYNQ_IRQ 81 |
423 | # define OMAP_INT_24XX_MMC_IRQ 83 |
424 | # define OMAP_INT_24XX_MS_IRQ 84 |
425 | # define OMAP_INT_24XX_FAC_IRQ 85 |
426 | # define OMAP_INT_24XX_MCSPI3_IRQ 91 |
427 | # define OMAP_INT_243X_HS_USB_MC 92 |
428 | # define OMAP_INT_243X_HS_USB_DMA 93 |
429 | # define OMAP_INT_243X_CARKIT 94 |
430 | # define OMAP_INT_34XX_GPTIMER12 95 |
431 | |
432 | /* omap_dma.c */ |
433 | enum omap_dma_model { |
434 | omap_dma_3_0, |
435 | omap_dma_3_1, |
436 | omap_dma_3_2, |
437 | omap_dma_4, |
438 | }; |
439 | |
440 | struct soc_dma_s; |
441 | struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs, |
442 | MemoryRegion *sysmem, |
443 | qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk, |
444 | enum omap_dma_model model); |
445 | struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs, |
446 | MemoryRegion *sysmem, |
447 | struct omap_mpu_state_s *mpu, int fifo, |
448 | int chans, omap_clk iclk, omap_clk fclk); |
449 | void omap_dma_reset(struct soc_dma_s *s); |
450 | |
451 | struct dma_irq_map { |
452 | int ih; |
453 | int intr; |
454 | }; |
455 | |
456 | /* Only used in OMAP DMA 3.x gigacells */ |
457 | enum omap_dma_port { |
458 | emiff = 0, |
459 | emifs, |
460 | imif, /* omap16xx: ocp_t1 */ |
461 | tipb, |
462 | local, /* omap16xx: ocp_t2 */ |
463 | tipb_mpui, |
464 | __omap_dma_port_last, |
465 | }; |
466 | |
467 | typedef enum { |
468 | constant = 0, |
469 | post_incremented, |
470 | single_index, |
471 | double_index, |
472 | } omap_dma_addressing_t; |
473 | |
474 | /* Only used in OMAP DMA 3.x gigacells */ |
475 | struct omap_dma_lcd_channel_s { |
476 | enum omap_dma_port src; |
477 | hwaddr src_f1_top; |
478 | hwaddr src_f1_bottom; |
479 | hwaddr src_f2_top; |
480 | hwaddr src_f2_bottom; |
481 | |
482 | /* Used in OMAP DMA 3.2 gigacell */ |
483 | unsigned char brust_f1; |
484 | unsigned char pack_f1; |
485 | unsigned char data_type_f1; |
486 | unsigned char brust_f2; |
487 | unsigned char pack_f2; |
488 | unsigned char data_type_f2; |
489 | unsigned char end_prog; |
490 | unsigned char repeat; |
491 | unsigned char auto_init; |
492 | unsigned char priority; |
493 | unsigned char fs; |
494 | unsigned char running; |
495 | unsigned char bs; |
496 | unsigned char omap_3_1_compatible_disable; |
497 | unsigned char dst; |
498 | unsigned char lch_type; |
499 | int16_t element_index_f1; |
500 | int16_t element_index_f2; |
501 | int32_t frame_index_f1; |
502 | int32_t frame_index_f2; |
503 | uint16_t elements_f1; |
504 | uint16_t frames_f1; |
505 | uint16_t elements_f2; |
506 | uint16_t frames_f2; |
507 | omap_dma_addressing_t mode_f1; |
508 | omap_dma_addressing_t mode_f2; |
509 | |
510 | /* Destination port is fixed. */ |
511 | int interrupts; |
512 | int condition; |
513 | int dual; |
514 | |
515 | int current_frame; |
516 | hwaddr phys_framebuffer[2]; |
517 | qemu_irq irq; |
518 | struct omap_mpu_state_s *mpu; |
519 | } *omap_dma_get_lcdch(struct soc_dma_s *s); |
520 | |
521 | /* |
522 | * DMA request numbers for OMAP1 |
523 | * See /usr/include/asm-arm/arch-omap/dma.h in Linux. |
524 | */ |
525 | # define OMAP_DMA_NO_DEVICE 0 |
526 | # define OMAP_DMA_MCSI1_TX 1 |
527 | # define OMAP_DMA_MCSI1_RX 2 |
528 | # define OMAP_DMA_I2C_RX 3 |
529 | # define OMAP_DMA_I2C_TX 4 |
530 | # define OMAP_DMA_EXT_NDMA_REQ0 5 |
531 | # define OMAP_DMA_EXT_NDMA_REQ1 6 |
532 | # define OMAP_DMA_UWIRE_TX 7 |
533 | # define OMAP_DMA_MCBSP1_TX 8 |
534 | # define OMAP_DMA_MCBSP1_RX 9 |
535 | # define OMAP_DMA_MCBSP3_TX 10 |
536 | # define OMAP_DMA_MCBSP3_RX 11 |
537 | # define OMAP_DMA_UART1_TX 12 |
538 | # define OMAP_DMA_UART1_RX 13 |
539 | # define OMAP_DMA_UART2_TX 14 |
540 | # define OMAP_DMA_UART2_RX 15 |
541 | # define OMAP_DMA_MCBSP2_TX 16 |
542 | # define OMAP_DMA_MCBSP2_RX 17 |
543 | # define OMAP_DMA_UART3_TX 18 |
544 | # define OMAP_DMA_UART3_RX 19 |
545 | # define OMAP_DMA_CAMERA_IF_RX 20 |
546 | # define OMAP_DMA_MMC_TX 21 |
547 | # define OMAP_DMA_MMC_RX 22 |
548 | # define OMAP_DMA_NAND 23 /* Not in OMAP310 */ |
549 | # define OMAP_DMA_IRQ_LCD_LINE 24 /* Not in OMAP310 */ |
550 | # define OMAP_DMA_MEMORY_STICK 25 /* Not in OMAP310 */ |
551 | # define OMAP_DMA_USB_W2FC_RX0 26 |
552 | # define OMAP_DMA_USB_W2FC_RX1 27 |
553 | # define OMAP_DMA_USB_W2FC_RX2 28 |
554 | # define OMAP_DMA_USB_W2FC_TX0 29 |
555 | # define OMAP_DMA_USB_W2FC_TX1 30 |
556 | # define OMAP_DMA_USB_W2FC_TX2 31 |
557 | |
558 | /* These are only for 1610 */ |
559 | # define OMAP_DMA_CRYPTO_DES_IN 32 |
560 | # define OMAP_DMA_SPI_TX 33 |
561 | # define OMAP_DMA_SPI_RX 34 |
562 | # define OMAP_DMA_CRYPTO_HASH 35 |
563 | # define OMAP_DMA_CCP_ATTN 36 |
564 | # define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37 |
565 | # define OMAP_DMA_CMT_APE_TX_CHAN_0 38 |
566 | # define OMAP_DMA_CMT_APE_RV_CHAN_0 39 |
567 | # define OMAP_DMA_CMT_APE_TX_CHAN_1 40 |
568 | # define OMAP_DMA_CMT_APE_RV_CHAN_1 41 |
569 | # define OMAP_DMA_CMT_APE_TX_CHAN_2 42 |
570 | # define OMAP_DMA_CMT_APE_RV_CHAN_2 43 |
571 | # define OMAP_DMA_CMT_APE_TX_CHAN_3 44 |
572 | # define OMAP_DMA_CMT_APE_RV_CHAN_3 45 |
573 | # define OMAP_DMA_CMT_APE_TX_CHAN_4 46 |
574 | # define OMAP_DMA_CMT_APE_RV_CHAN_4 47 |
575 | # define OMAP_DMA_CMT_APE_TX_CHAN_5 48 |
576 | # define OMAP_DMA_CMT_APE_RV_CHAN_5 49 |
577 | # define OMAP_DMA_CMT_APE_TX_CHAN_6 50 |
578 | # define OMAP_DMA_CMT_APE_RV_CHAN_6 51 |
579 | # define OMAP_DMA_CMT_APE_TX_CHAN_7 52 |
580 | # define OMAP_DMA_CMT_APE_RV_CHAN_7 53 |
581 | # define OMAP_DMA_MMC2_TX 54 |
582 | # define OMAP_DMA_MMC2_RX 55 |
583 | # define OMAP_DMA_CRYPTO_DES_OUT 56 |
584 | |
585 | /* |
586 | * DMA request numbers for the OMAP2 |
587 | */ |
588 | # define OMAP24XX_DMA_NO_DEVICE 0 |
589 | # define OMAP24XX_DMA_XTI_DMA 1 /* Not in OMAP2420 */ |
590 | # define OMAP24XX_DMA_EXT_DMAREQ0 2 |
591 | # define OMAP24XX_DMA_EXT_DMAREQ1 3 |
592 | # define OMAP24XX_DMA_GPMC 4 |
593 | # define OMAP24XX_DMA_GFX 5 /* Not in OMAP2420 */ |
594 | # define OMAP24XX_DMA_DSS 6 |
595 | # define OMAP24XX_DMA_VLYNQ_TX 7 /* Not in OMAP2420 */ |
596 | # define OMAP24XX_DMA_CWT 8 /* Not in OMAP2420 */ |
597 | # define OMAP24XX_DMA_AES_TX 9 /* Not in OMAP2420 */ |
598 | # define OMAP24XX_DMA_AES_RX 10 /* Not in OMAP2420 */ |
599 | # define OMAP24XX_DMA_DES_TX 11 /* Not in OMAP2420 */ |
600 | # define OMAP24XX_DMA_DES_RX 12 /* Not in OMAP2420 */ |
601 | # define OMAP24XX_DMA_SHA1MD5_RX 13 /* Not in OMAP2420 */ |
602 | # define OMAP24XX_DMA_EXT_DMAREQ2 14 |
603 | # define OMAP24XX_DMA_EXT_DMAREQ3 15 |
604 | # define OMAP24XX_DMA_EXT_DMAREQ4 16 |
605 | # define OMAP24XX_DMA_EAC_AC_RD 17 |
606 | # define OMAP24XX_DMA_EAC_AC_WR 18 |
607 | # define OMAP24XX_DMA_EAC_MD_UL_RD 19 |
608 | # define OMAP24XX_DMA_EAC_MD_UL_WR 20 |
609 | # define OMAP24XX_DMA_EAC_MD_DL_RD 21 |
610 | # define OMAP24XX_DMA_EAC_MD_DL_WR 22 |
611 | # define OMAP24XX_DMA_EAC_BT_UL_RD 23 |
612 | # define OMAP24XX_DMA_EAC_BT_UL_WR 24 |
613 | # define OMAP24XX_DMA_EAC_BT_DL_RD 25 |
614 | # define OMAP24XX_DMA_EAC_BT_DL_WR 26 |
615 | # define OMAP24XX_DMA_I2C1_TX 27 |
616 | # define OMAP24XX_DMA_I2C1_RX 28 |
617 | # define OMAP24XX_DMA_I2C2_TX 29 |
618 | # define OMAP24XX_DMA_I2C2_RX 30 |
619 | # define OMAP24XX_DMA_MCBSP1_TX 31 |
620 | # define OMAP24XX_DMA_MCBSP1_RX 32 |
621 | # define OMAP24XX_DMA_MCBSP2_TX 33 |
622 | # define OMAP24XX_DMA_MCBSP2_RX 34 |
623 | # define OMAP24XX_DMA_SPI1_TX0 35 |
624 | # define OMAP24XX_DMA_SPI1_RX0 36 |
625 | # define OMAP24XX_DMA_SPI1_TX1 37 |
626 | # define OMAP24XX_DMA_SPI1_RX1 38 |
627 | # define OMAP24XX_DMA_SPI1_TX2 39 |
628 | # define OMAP24XX_DMA_SPI1_RX2 40 |
629 | # define OMAP24XX_DMA_SPI1_TX3 41 |
630 | # define OMAP24XX_DMA_SPI1_RX3 42 |
631 | # define OMAP24XX_DMA_SPI2_TX0 43 |
632 | # define OMAP24XX_DMA_SPI2_RX0 44 |
633 | # define OMAP24XX_DMA_SPI2_TX1 45 |
634 | # define OMAP24XX_DMA_SPI2_RX1 46 |
635 | |
636 | # define OMAP24XX_DMA_UART1_TX 49 |
637 | # define OMAP24XX_DMA_UART1_RX 50 |
638 | # define OMAP24XX_DMA_UART2_TX 51 |
639 | # define OMAP24XX_DMA_UART2_RX 52 |
640 | # define OMAP24XX_DMA_UART3_TX 53 |
641 | # define OMAP24XX_DMA_UART3_RX 54 |
642 | # define OMAP24XX_DMA_USB_W2FC_TX0 55 |
643 | # define OMAP24XX_DMA_USB_W2FC_RX0 56 |
644 | # define OMAP24XX_DMA_USB_W2FC_TX1 57 |
645 | # define OMAP24XX_DMA_USB_W2FC_RX1 58 |
646 | # define OMAP24XX_DMA_USB_W2FC_TX2 59 |
647 | # define OMAP24XX_DMA_USB_W2FC_RX2 60 |
648 | # define OMAP24XX_DMA_MMC1_TX 61 |
649 | # define OMAP24XX_DMA_MMC1_RX 62 |
650 | # define OMAP24XX_DMA_MS 63 /* Not in OMAP2420 */ |
651 | # define OMAP24XX_DMA_EXT_DMAREQ5 64 |
652 | |
653 | /* omap[123].c */ |
654 | /* OMAP2 gp timer */ |
655 | struct omap_gp_timer_s; |
656 | struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta, |
657 | qemu_irq irq, omap_clk fclk, omap_clk iclk); |
658 | void omap_gp_timer_reset(struct omap_gp_timer_s *s); |
659 | |
660 | /* OMAP2 sysctimer */ |
661 | struct omap_synctimer_s; |
662 | struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, |
663 | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk); |
664 | void omap_synctimer_reset(struct omap_synctimer_s *s); |
665 | |
666 | struct omap_uart_s; |
667 | struct omap_uart_s *omap_uart_init(hwaddr base, |
668 | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
669 | qemu_irq txdma, qemu_irq rxdma, |
670 | const char *label, Chardev *chr); |
671 | struct omap_uart_s *omap2_uart_init(MemoryRegion *sysmem, |
672 | struct omap_target_agent_s *ta, |
673 | qemu_irq irq, omap_clk fclk, omap_clk iclk, |
674 | qemu_irq txdma, qemu_irq rxdma, |
675 | const char *label, Chardev *chr); |
676 | void omap_uart_reset(struct omap_uart_s *s); |
677 | void omap_uart_attach(struct omap_uart_s *s, Chardev *chr); |
678 | |
679 | struct omap_mpuio_s; |
680 | qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); |
681 | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); |
682 | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); |
683 | |
684 | struct omap_uwire_s; |
685 | void omap_uwire_attach(struct omap_uwire_s *s, |
686 | uWireSlave *slave, int chipselect); |
687 | |
688 | /* OMAP2 spi */ |
689 | struct omap_mcspi_s; |
690 | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
691 | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk); |
692 | void omap_mcspi_attach(struct omap_mcspi_s *s, |
693 | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
694 | int chipselect); |
695 | void omap_mcspi_reset(struct omap_mcspi_s *s); |
696 | |
697 | struct I2SCodec { |
698 | void *opaque; |
699 | |
700 | /* The CPU can call this if it is generating the clock signal on the |
701 | * i2s port. The CODEC can ignore it if it is set up as a clock |
702 | * master and generates its own clock. */ |
703 | void (*set_rate)(void *opaque, int in, int out); |
704 | |
705 | void (*tx_swallow)(void *opaque); |
706 | qemu_irq rx_swallow; |
707 | qemu_irq tx_start; |
708 | |
709 | int tx_rate; |
710 | int cts; |
711 | int rx_rate; |
712 | int rts; |
713 | |
714 | struct i2s_fifo_s { |
715 | uint8_t *fifo; |
716 | int len; |
717 | int start; |
718 | int size; |
719 | } in, out; |
720 | }; |
721 | struct omap_mcbsp_s; |
722 | void omap_mcbsp_i2s_attach(struct omap_mcbsp_s *s, I2SCodec *slave); |
723 | |
724 | void omap_tap_init(struct omap_target_agent_s *ta, |
725 | struct omap_mpu_state_s *mpu); |
726 | |
727 | /* omap_lcdc.c */ |
728 | struct omap_lcd_panel_s; |
729 | void omap_lcdc_reset(struct omap_lcd_panel_s *s); |
730 | struct omap_lcd_panel_s *omap_lcdc_init(MemoryRegion *sysmem, |
731 | hwaddr base, |
732 | qemu_irq irq, |
733 | struct omap_dma_lcd_channel_s *dma, |
734 | omap_clk clk); |
735 | |
736 | /* omap_dss.c */ |
737 | struct rfbi_chip_s { |
738 | void *opaque; |
739 | void (*write)(void *opaque, int dc, uint16_t value); |
740 | void (*block)(void *opaque, int dc, void *buf, size_t len, int pitch); |
741 | uint16_t (*read)(void *opaque, int dc); |
742 | }; |
743 | struct omap_dss_s; |
744 | void omap_dss_reset(struct omap_dss_s *s); |
745 | struct omap_dss_s *omap_dss_init(struct omap_target_agent_s *ta, |
746 | MemoryRegion *sysmem, |
747 | hwaddr l3_base, |
748 | qemu_irq irq, qemu_irq drq, |
749 | omap_clk fck1, omap_clk fck2, omap_clk ck54m, |
750 | omap_clk ick1, omap_clk ick2); |
751 | void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip); |
752 | |
753 | /* omap_mmc.c */ |
754 | struct omap_mmc_s; |
755 | struct omap_mmc_s *omap_mmc_init(hwaddr base, |
756 | MemoryRegion *sysmem, |
757 | BlockBackend *blk, |
758 | qemu_irq irq, qemu_irq dma[], omap_clk clk); |
759 | struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
760 | BlockBackend *blk, qemu_irq irq, qemu_irq dma[], |
761 | omap_clk fclk, omap_clk iclk); |
762 | void omap_mmc_reset(struct omap_mmc_s *s); |
763 | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover); |
764 | void omap_mmc_enable(struct omap_mmc_s *s, int enable); |
765 | |
766 | /* omap_i2c.c */ |
767 | I2CBus *omap_i2c_bus(DeviceState *omap_i2c); |
768 | |
769 | # define cpu_is_omap310(cpu) (cpu->mpu_model == omap310) |
770 | # define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510) |
771 | # define cpu_is_omap1610(cpu) (cpu->mpu_model == omap1610) |
772 | # define cpu_is_omap1710(cpu) (cpu->mpu_model == omap1710) |
773 | # define cpu_is_omap2410(cpu) (cpu->mpu_model == omap2410) |
774 | # define cpu_is_omap2420(cpu) (cpu->mpu_model == omap2420) |
775 | # define cpu_is_omap2430(cpu) (cpu->mpu_model == omap2430) |
776 | # define cpu_is_omap3430(cpu) (cpu->mpu_model == omap3430) |
777 | # define cpu_is_omap3630(cpu) (cpu->mpu_model == omap3630) |
778 | |
779 | # define cpu_is_omap15xx(cpu) \ |
780 | (cpu_is_omap310(cpu) || cpu_is_omap1510(cpu)) |
781 | # define cpu_is_omap16xx(cpu) \ |
782 | (cpu_is_omap1610(cpu) || cpu_is_omap1710(cpu)) |
783 | # define cpu_is_omap24xx(cpu) \ |
784 | (cpu_is_omap2410(cpu) || cpu_is_omap2420(cpu) || cpu_is_omap2430(cpu)) |
785 | |
786 | # define cpu_class_omap1(cpu) \ |
787 | (cpu_is_omap15xx(cpu) || cpu_is_omap16xx(cpu)) |
788 | # define cpu_class_omap2(cpu) cpu_is_omap24xx(cpu) |
789 | # define cpu_class_omap3(cpu) \ |
790 | (cpu_is_omap3430(cpu) || cpu_is_omap3630(cpu)) |
791 | |
792 | struct omap_mpu_state_s { |
793 | enum omap_mpu_model { |
794 | omap310, |
795 | omap1510, |
796 | omap1610, |
797 | omap1710, |
798 | omap2410, |
799 | omap2420, |
800 | omap2422, |
801 | omap2423, |
802 | omap2430, |
803 | omap3430, |
804 | omap3630, |
805 | } mpu_model; |
806 | |
807 | ARMCPU *cpu; |
808 | |
809 | qemu_irq *drq; |
810 | |
811 | qemu_irq wakeup; |
812 | |
813 | MemoryRegion ulpd_pm_iomem; |
814 | MemoryRegion pin_cfg_iomem; |
815 | MemoryRegion id_iomem; |
816 | MemoryRegion id_iomem_e18; |
817 | MemoryRegion id_iomem_ed4; |
818 | MemoryRegion id_iomem_e20; |
819 | MemoryRegion mpui_iomem; |
820 | MemoryRegion tcmi_iomem; |
821 | MemoryRegion clkm_iomem; |
822 | MemoryRegion clkdsp_iomem; |
823 | MemoryRegion mpui_io_iomem; |
824 | MemoryRegion tap_iomem; |
825 | MemoryRegion imif_ram; |
826 | MemoryRegion emiff_ram; |
827 | MemoryRegion sdram; |
828 | MemoryRegion sram; |
829 | |
830 | struct omap_dma_port_if_s { |
831 | uint32_t (*read[3])(struct omap_mpu_state_s *s, |
832 | hwaddr offset); |
833 | void (*write[3])(struct omap_mpu_state_s *s, |
834 | hwaddr offset, uint32_t value); |
835 | int (*addr_valid)(struct omap_mpu_state_s *s, |
836 | hwaddr addr); |
837 | } port[__omap_dma_port_last]; |
838 | |
839 | unsigned long sdram_size; |
840 | unsigned long sram_size; |
841 | |
842 | /* MPUI-TIPB peripherals */ |
843 | struct omap_uart_s *uart[3]; |
844 | |
845 | DeviceState *gpio; |
846 | |
847 | struct omap_mcbsp_s *mcbsp1; |
848 | struct omap_mcbsp_s *mcbsp3; |
849 | |
850 | /* MPU public TIPB peripherals */ |
851 | struct omap_32khz_timer_s *os_timer; |
852 | |
853 | struct omap_mmc_s *mmc; |
854 | |
855 | struct omap_mpuio_s *mpuio; |
856 | |
857 | struct omap_uwire_s *microwire; |
858 | |
859 | struct omap_pwl_s *pwl; |
860 | struct omap_pwt_s *pwt; |
861 | DeviceState *i2c[2]; |
862 | |
863 | struct omap_rtc_s *rtc; |
864 | |
865 | struct omap_mcbsp_s *mcbsp2; |
866 | |
867 | struct omap_lpg_s *led[2]; |
868 | |
869 | /* MPU private TIPB peripherals */ |
870 | DeviceState *ih[2]; |
871 | |
872 | struct soc_dma_s *dma; |
873 | |
874 | struct omap_mpu_timer_s *timer[3]; |
875 | struct omap_watchdog_timer_s *wdt; |
876 | |
877 | struct omap_lcd_panel_s *lcd; |
878 | |
879 | uint32_t ulpd_pm_regs[21]; |
880 | int64_t ulpd_gauge_start; |
881 | |
882 | uint32_t func_mux_ctrl[14]; |
883 | uint32_t comp_mode_ctrl[1]; |
884 | uint32_t pull_dwn_ctrl[4]; |
885 | uint32_t gate_inh_ctrl[1]; |
886 | uint32_t voltage_ctrl[1]; |
887 | uint32_t test_dbg_ctrl[1]; |
888 | uint32_t mod_conf_ctrl[1]; |
889 | int compat1509; |
890 | |
891 | uint32_t mpui_ctrl; |
892 | |
893 | struct omap_tipb_bridge_s *private_tipb; |
894 | struct omap_tipb_bridge_s *public_tipb; |
895 | |
896 | uint32_t tcmi_regs[17]; |
897 | |
898 | struct dpll_ctl_s *dpll[3]; |
899 | |
900 | omap_clk clks; |
901 | struct { |
902 | int cold_start; |
903 | int clocking_scheme; |
904 | uint16_t arm_ckctl; |
905 | uint16_t arm_idlect1; |
906 | uint16_t arm_idlect2; |
907 | uint16_t arm_ewupct; |
908 | uint16_t arm_rstct1; |
909 | uint16_t arm_rstct2; |
910 | uint16_t arm_ckout1; |
911 | int dpll1_mode; |
912 | uint16_t dsp_idlect1; |
913 | uint16_t dsp_idlect2; |
914 | uint16_t dsp_rstct2; |
915 | } clkm; |
916 | |
917 | /* OMAP2-only peripherals */ |
918 | struct omap_l4_s *l4; |
919 | |
920 | struct omap_gp_timer_s *gptimer[12]; |
921 | struct omap_synctimer_s *synctimer; |
922 | |
923 | struct omap_prcm_s *prcm; |
924 | struct omap_sdrc_s *sdrc; |
925 | struct omap_gpmc_s *gpmc; |
926 | struct omap_sysctl_s *sysc; |
927 | |
928 | struct omap_mcspi_s *mcspi[2]; |
929 | |
930 | struct omap_dss_s *dss; |
931 | |
932 | struct omap_eac_s *eac; |
933 | }; |
934 | |
935 | /* omap1.c */ |
936 | struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, |
937 | unsigned long sdram_size, |
938 | const char *core); |
939 | |
940 | /* omap2.c */ |
941 | struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, |
942 | unsigned long sdram_size, |
943 | const char *core); |
944 | |
945 | uint32_t omap_badwidth_read8(void *opaque, hwaddr addr); |
946 | void omap_badwidth_write8(void *opaque, hwaddr addr, |
947 | uint32_t value); |
948 | uint32_t omap_badwidth_read16(void *opaque, hwaddr addr); |
949 | void omap_badwidth_write16(void *opaque, hwaddr addr, |
950 | uint32_t value); |
951 | uint32_t omap_badwidth_read32(void *opaque, hwaddr addr); |
952 | void omap_badwidth_write32(void *opaque, hwaddr addr, |
953 | uint32_t value); |
954 | |
955 | void omap_mpu_wakeup(void *opaque, int irq, int req); |
956 | |
957 | # define OMAP_BAD_REG(paddr) \ |
958 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad register %#08"HWADDR_PRIx"\n", \ |
959 | __func__, paddr) |
960 | # define OMAP_RO_REG(paddr) \ |
961 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Read-only register %#08" \ |
962 | HWADDR_PRIx "\n", \ |
963 | __func__, paddr) |
964 | |
965 | /* OMAP-specific Linux bootloader tags for the ATAG_BOARD area |
966 | (Board-specifc tags are not here) */ |
967 | #define OMAP_TAG_CLOCK 0x4f01 |
968 | #define OMAP_TAG_MMC 0x4f02 |
969 | #define OMAP_TAG_SERIAL_CONSOLE 0x4f03 |
970 | #define OMAP_TAG_USB 0x4f04 |
971 | #define OMAP_TAG_LCD 0x4f05 |
972 | #define OMAP_TAG_GPIO_SWITCH 0x4f06 |
973 | #define OMAP_TAG_UART 0x4f07 |
974 | #define OMAP_TAG_FBMEM 0x4f08 |
975 | #define OMAP_TAG_STI_CONSOLE 0x4f09 |
976 | #define OMAP_TAG_CAMERA_SENSOR 0x4f0a |
977 | #define OMAP_TAG_PARTITION 0x4f0b |
978 | #define OMAP_TAG_TEA5761 0x4f10 |
979 | #define OMAP_TAG_TMP105 0x4f11 |
980 | #define OMAP_TAG_BOOT_REASON 0x4f80 |
981 | #define OMAP_TAG_FLASH_PART_STR 0x4f81 |
982 | #define OMAP_TAG_VERSION_STR 0x4f82 |
983 | |
984 | enum { |
985 | OMAP_GPIOSW_TYPE_COVER = 0 << 4, |
986 | OMAP_GPIOSW_TYPE_CONNECTION = 1 << 4, |
987 | OMAP_GPIOSW_TYPE_ACTIVITY = 2 << 4, |
988 | }; |
989 | |
990 | #define OMAP_GPIOSW_INVERTED 0x0001 |
991 | #define OMAP_GPIOSW_OUTPUT 0x0002 |
992 | |
993 | # define OMAP_MPUI_REG_MASK 0x000007ff |
994 | |
995 | #endif |
996 | |