1 | /* |
2 | * Device model for i.MX UART |
3 | * |
4 | * Copyright (c) 2008 OKL |
5 | * Originally Written by Hans Jiang |
6 | * Copyright (c) 2011 NICTA Pty Ltd. |
7 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
8 | * |
9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License |
11 | * as published by the Free Software Foundation; either version |
12 | * 2 of the License, or (at your option) any later version. |
13 | * |
14 | * You should have received a copy of the GNU General Public License along |
15 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
16 | */ |
17 | |
18 | #ifndef IMX_SERIAL_H |
19 | #define IMX_SERIAL_H |
20 | |
21 | #include "hw/sysbus.h" |
22 | #include "chardev/char-fe.h" |
23 | |
24 | #define TYPE_IMX_SERIAL "imx.serial" |
25 | #define IMX_SERIAL(obj) OBJECT_CHECK(IMXSerialState, (obj), TYPE_IMX_SERIAL) |
26 | |
27 | #define URXD_CHARRDY (1<<15) /* character read is valid */ |
28 | #define URXD_ERR (1<<14) /* Character has error */ |
29 | #define URXD_FRMERR (1<<12) /* Character has frame error */ |
30 | #define URXD_BRK (1<<11) /* Break received */ |
31 | |
32 | #define USR1_PARTYER (1<<15) /* Parity Error */ |
33 | #define USR1_RTSS (1<<14) /* RTS pin status */ |
34 | #define USR1_TRDY (1<<13) /* Tx ready */ |
35 | #define USR1_RTSD (1<<12) /* RTS delta: pin changed state */ |
36 | #define USR1_ESCF (1<<11) /* Escape sequence interrupt */ |
37 | #define USR1_FRAMERR (1<<10) /* Framing error */ |
38 | #define USR1_RRDY (1<<9) /* receiver ready */ |
39 | #define USR1_AGTIM (1<<8) /* Aging timer interrupt */ |
40 | #define USR1_DTRD (1<<7) /* DTR changed */ |
41 | #define USR1_RXDS (1<<6) /* Receiver is idle */ |
42 | #define USR1_AIRINT (1<<5) /* Aysnch IR interrupt */ |
43 | #define USR1_AWAKE (1<<4) /* Falling edge detected on RXd pin */ |
44 | |
45 | #define USR2_ADET (1<<15) /* Autobaud complete */ |
46 | #define USR2_TXFE (1<<14) /* Transmit FIFO empty */ |
47 | #define USR2_DTRF (1<<13) /* DTR/DSR transition */ |
48 | #define USR2_IDLE (1<<12) /* UART has been idle for too long */ |
49 | #define USR2_ACST (1<<11) /* Autobaud counter stopped */ |
50 | #define USR2_RIDELT (1<<10) /* Ring Indicator delta */ |
51 | #define USR2_RIIN (1<<9) /* Ring Indicator Input */ |
52 | #define USR2_IRINT (1<<8) /* Serial Infrared Interrupt */ |
53 | #define USR2_WAKE (1<<7) /* Start bit detected */ |
54 | #define USR2_DCDDELT (1<<6) /* Data Carrier Detect delta */ |
55 | #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ |
56 | #define USR2_RTSF (1<<4) /* RTS transition */ |
57 | #define USR2_TXDC (1<<3) /* Transmission complete */ |
58 | #define USR2_BRCD (1<<2) /* Break condition detected */ |
59 | #define USR2_ORE (1<<1) /* Overrun error */ |
60 | #define USR2_RDR (1<<0) /* Receive data ready */ |
61 | |
62 | #define UCR1_TRDYEN (1<<13) /* Tx Ready Interrupt Enable */ |
63 | #define UCR1_RRDYEN (1<<9) /* Rx Ready Interrupt Enable */ |
64 | #define UCR1_TXMPTYEN (1<<6) /* Tx Empty Interrupt Enable */ |
65 | #define UCR1_UARTEN (1<<0) /* UART Enable */ |
66 | |
67 | #define UCR2_TXEN (1<<2) /* Transmitter enable */ |
68 | #define UCR2_RXEN (1<<1) /* Receiver enable */ |
69 | #define UCR2_SRST (1<<0) /* Reset complete */ |
70 | |
71 | #define UCR4_DREN BIT(0) /* Receive Data Ready interrupt enable */ |
72 | #define UCR4_TCEN BIT(3) /* TX complete interrupt enable */ |
73 | |
74 | #define UTS1_TXEMPTY (1<<6) |
75 | #define UTS1_RXEMPTY (1<<5) |
76 | #define UTS1_TXFULL (1<<4) |
77 | #define UTS1_RXFULL (1<<3) |
78 | |
79 | typedef struct IMXSerialState { |
80 | /*< private >*/ |
81 | SysBusDevice parent_obj; |
82 | |
83 | /*< public >*/ |
84 | MemoryRegion iomem; |
85 | int32_t readbuff; |
86 | |
87 | uint32_t usr1; |
88 | uint32_t usr2; |
89 | uint32_t ucr1; |
90 | uint32_t ucr2; |
91 | uint32_t uts1; |
92 | |
93 | /* |
94 | * The registers below are implemented just so that the |
95 | * guest OS sees what it has written |
96 | */ |
97 | uint32_t onems; |
98 | uint32_t ufcr; |
99 | uint32_t ubmr; |
100 | uint32_t ubrc; |
101 | uint32_t ucr3; |
102 | uint32_t ucr4; |
103 | |
104 | qemu_irq irq; |
105 | CharBackend chr; |
106 | } IMXSerialState; |
107 | |
108 | #endif |
109 | |