1/*
2 * QEMU SPAPR Option/Architecture Vector Definitions
3 *
4 * Each architecture option is organized/documented by the following
5 * in LoPAPR 1.1, Table 244:
6 *
7 * <vector number>: the bit-vector in which the option is located
8 * <vector byte>: the byte offset of the vector entry
9 * <vector bit>: the bit offset within the vector entry
10 *
11 * where each vector entry can be one or more bytes.
12 *
13 * Firmware expects a somewhat literal encoding of this bit-vector
14 * structure, where each entry is stored in little-endian so that the
15 * byte ordering reflects that of the documentation, but where each bit
16 * offset is from "left-to-right" in the traditional representation of
17 * a byte value where the MSB is the left-most bit. Thus, each
18 * individual byte encodes the option bits in reverse order of the
19 * documented bit.
20 *
21 * These definitions/helpers attempt to abstract away this internal
22 * representation so that we can define/set/test for individual option
23 * bits using only the documented values. This is done mainly by relying
24 * on a bitmap to approximate the documented "bit-vector" structure and
25 * handling conversations to-from the internal representation under the
26 * covers.
27 *
28 * Copyright IBM Corp. 2016
29 *
30 * Authors:
31 * Michael Roth <mdroth@linux.vnet.ibm.com>
32 *
33 * This work is licensed under the terms of the GNU GPL, version 2 or later.
34 * See the COPYING file in the top-level directory.
35 */
36
37#ifndef SPAPR_OVEC_H
38#define SPAPR_OVEC_H
39
40#include "cpu.h"
41
42typedef struct SpaprOptionVector SpaprOptionVector;
43
44#define OV_BIT(byte, bit) ((byte - 1) * BITS_PER_BYTE + bit)
45
46/* option vector 1 */
47#define OV1_PPC_3_00 OV_BIT(3, 0) /* guest supports PowerPC 3.00? */
48
49/* option vector 5 */
50#define OV5_DRCONF_MEMORY OV_BIT(2, 2)
51#define OV5_FORM1_AFFINITY OV_BIT(5, 0)
52#define OV5_HP_EVT OV_BIT(6, 5)
53#define OV5_HPT_RESIZE OV_BIT(6, 7)
54#define OV5_DRMEM_V2 OV_BIT(22, 0)
55#define OV5_XIVE_BOTH OV_BIT(23, 0)
56#define OV5_XIVE_EXPLOIT OV_BIT(23, 1) /* 1=exploitation 0=legacy */
57
58/* ISA 3.00 MMU features: */
59#define OV5_MMU_BOTH OV_BIT(24, 0) /* Radix and hash */
60#define OV5_MMU_RADIX_300 OV_BIT(24, 1) /* 1=Radix only, 0=Hash only */
61#define OV5_MMU_RADIX_GTSE OV_BIT(26, 1) /* Radix GTSE */
62
63/* interfaces */
64SpaprOptionVector *spapr_ovec_new(void);
65SpaprOptionVector *spapr_ovec_clone(SpaprOptionVector *ov_orig);
66void spapr_ovec_intersect(SpaprOptionVector *ov,
67 SpaprOptionVector *ov1,
68 SpaprOptionVector *ov2);
69bool spapr_ovec_diff(SpaprOptionVector *ov,
70 SpaprOptionVector *ov_old,
71 SpaprOptionVector *ov_new);
72void spapr_ovec_cleanup(SpaprOptionVector *ov);
73void spapr_ovec_set(SpaprOptionVector *ov, long bitnr);
74void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr);
75bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr);
76SpaprOptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int vector);
77int spapr_ovec_populate_dt(void *fdt, int fdt_offset,
78 SpaprOptionVector *ov, const char *name);
79
80/* migration */
81extern const VMStateDescription vmstate_spapr_ovec;
82
83#endif /* SPAPR_OVEC_H */
84