1 | /* |
2 | * QEMU HPPA CPU |
3 | * |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2.1 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see |
18 | * <http://www.gnu.org/licenses/lgpl-2.1.html> |
19 | */ |
20 | |
21 | #include "qemu/osdep.h" |
22 | #include "qapi/error.h" |
23 | #include "qemu/qemu-print.h" |
24 | #include "cpu.h" |
25 | #include "qemu/module.h" |
26 | #include "exec/exec-all.h" |
27 | #include "fpu/softfloat.h" |
28 | |
29 | |
30 | static void hppa_cpu_set_pc(CPUState *cs, vaddr value) |
31 | { |
32 | HPPACPU *cpu = HPPA_CPU(cs); |
33 | |
34 | cpu->env.iaoq_f = value; |
35 | cpu->env.iaoq_b = value + 4; |
36 | } |
37 | |
38 | static void hppa_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) |
39 | { |
40 | HPPACPU *cpu = HPPA_CPU(cs); |
41 | |
42 | #ifdef CONFIG_USER_ONLY |
43 | cpu->env.iaoq_f = tb->pc; |
44 | cpu->env.iaoq_b = tb->cs_base; |
45 | #else |
46 | /* Recover the IAOQ values from the GVA + PRIV. */ |
47 | uint32_t priv = (tb->flags >> TB_FLAG_PRIV_SHIFT) & 3; |
48 | target_ulong cs_base = tb->cs_base; |
49 | target_ulong iasq_f = cs_base & ~0xffffffffull; |
50 | int32_t diff = cs_base; |
51 | |
52 | cpu->env.iasq_f = iasq_f; |
53 | cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; |
54 | if (diff) { |
55 | cpu->env.iaoq_b = cpu->env.iaoq_f + diff; |
56 | } |
57 | #endif |
58 | |
59 | cpu->env.psw_n = (tb->flags & PSW_N) != 0; |
60 | } |
61 | |
62 | static bool hppa_cpu_has_work(CPUState *cs) |
63 | { |
64 | return cs->interrupt_request & CPU_INTERRUPT_HARD; |
65 | } |
66 | |
67 | static void hppa_cpu_disas_set_info(CPUState *cs, disassemble_info *info) |
68 | { |
69 | info->mach = bfd_mach_hppa20; |
70 | info->print_insn = print_insn_hppa; |
71 | } |
72 | |
73 | static void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, |
74 | MMUAccessType access_type, |
75 | int mmu_idx, uintptr_t retaddr) |
76 | { |
77 | HPPACPU *cpu = HPPA_CPU(cs); |
78 | CPUHPPAState *env = &cpu->env; |
79 | |
80 | cs->exception_index = EXCP_UNALIGN; |
81 | if (env->psw & PSW_Q) { |
82 | /* ??? Needs tweaking for hppa64. */ |
83 | env->cr[CR_IOR] = addr; |
84 | env->cr[CR_ISR] = addr >> 32; |
85 | } |
86 | |
87 | cpu_loop_exit_restore(cs, retaddr); |
88 | } |
89 | |
90 | static void hppa_cpu_realizefn(DeviceState *dev, Error **errp) |
91 | { |
92 | CPUState *cs = CPU(dev); |
93 | HPPACPUClass *acc = HPPA_CPU_GET_CLASS(dev); |
94 | Error *local_err = NULL; |
95 | |
96 | cpu_exec_realizefn(cs, &local_err); |
97 | if (local_err != NULL) { |
98 | error_propagate(errp, local_err); |
99 | return; |
100 | } |
101 | |
102 | qemu_init_vcpu(cs); |
103 | acc->parent_realize(dev, errp); |
104 | |
105 | #ifndef CONFIG_USER_ONLY |
106 | { |
107 | HPPACPU *cpu = HPPA_CPU(cs); |
108 | cpu->alarm_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, |
109 | hppa_cpu_alarm_timer, cpu); |
110 | } |
111 | #endif |
112 | } |
113 | |
114 | static void hppa_cpu_initfn(Object *obj) |
115 | { |
116 | CPUState *cs = CPU(obj); |
117 | HPPACPU *cpu = HPPA_CPU(obj); |
118 | CPUHPPAState *env = &cpu->env; |
119 | |
120 | cpu_set_cpustate_pointers(cpu); |
121 | cs->exception_index = -1; |
122 | cpu_hppa_loaded_fr0(env); |
123 | cpu_hppa_put_psw(env, PSW_W); |
124 | } |
125 | |
126 | static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) |
127 | { |
128 | return object_class_by_name(TYPE_HPPA_CPU); |
129 | } |
130 | |
131 | static void hppa_cpu_class_init(ObjectClass *oc, void *data) |
132 | { |
133 | DeviceClass *dc = DEVICE_CLASS(oc); |
134 | CPUClass *cc = CPU_CLASS(oc); |
135 | HPPACPUClass *acc = HPPA_CPU_CLASS(oc); |
136 | |
137 | device_class_set_parent_realize(dc, hppa_cpu_realizefn, |
138 | &acc->parent_realize); |
139 | |
140 | cc->class_by_name = hppa_cpu_class_by_name; |
141 | cc->has_work = hppa_cpu_has_work; |
142 | cc->do_interrupt = hppa_cpu_do_interrupt; |
143 | cc->cpu_exec_interrupt = hppa_cpu_exec_interrupt; |
144 | cc->dump_state = hppa_cpu_dump_state; |
145 | cc->set_pc = hppa_cpu_set_pc; |
146 | cc->synchronize_from_tb = hppa_cpu_synchronize_from_tb; |
147 | cc->gdb_read_register = hppa_cpu_gdb_read_register; |
148 | cc->gdb_write_register = hppa_cpu_gdb_write_register; |
149 | cc->tlb_fill = hppa_cpu_tlb_fill; |
150 | #ifndef CONFIG_USER_ONLY |
151 | cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; |
152 | dc->vmsd = &vmstate_hppa_cpu; |
153 | #endif |
154 | cc->do_unaligned_access = hppa_cpu_do_unaligned_access; |
155 | cc->disas_set_info = hppa_cpu_disas_set_info; |
156 | cc->tcg_initialize = hppa_translate_init; |
157 | |
158 | cc->gdb_num_core_regs = 128; |
159 | } |
160 | |
161 | static const TypeInfo hppa_cpu_type_info = { |
162 | .name = TYPE_HPPA_CPU, |
163 | .parent = TYPE_CPU, |
164 | .instance_size = sizeof(HPPACPU), |
165 | .instance_init = hppa_cpu_initfn, |
166 | .abstract = false, |
167 | .class_size = sizeof(HPPACPUClass), |
168 | .class_init = hppa_cpu_class_init, |
169 | }; |
170 | |
171 | static void hppa_cpu_register_types(void) |
172 | { |
173 | type_register_static(&hppa_cpu_type_info); |
174 | } |
175 | |
176 | type_init(hppa_cpu_register_types) |
177 | |