1 | /* |
2 | * PA-RISC emulation cpu definitions for qemu. |
3 | * |
4 | * Copyright (c) 2016 Richard Henderson <rth@twiddle.net> |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #ifndef HPPA_CPU_H |
21 | #define HPPA_CPU_H |
22 | |
23 | #include "cpu-qom.h" |
24 | #include "exec/cpu-defs.h" |
25 | #include "exec/memory.h" |
26 | |
27 | /* PA-RISC 1.x processors have a strong memory model. */ |
28 | /* ??? While we do not yet implement PA-RISC 2.0, those processors have |
29 | a weak memory model, but with TLB bits that force ordering on a per-page |
30 | basis. It's probably easier to fall back to a strong memory model. */ |
31 | #define TCG_GUEST_DEFAULT_MO TCG_MO_ALL |
32 | |
33 | #define MMU_KERNEL_IDX 0 |
34 | #define MMU_USER_IDX 3 |
35 | #define MMU_PHYS_IDX 4 |
36 | #define 1 |
37 | |
38 | /* Hardware exceptions, interupts, faults, and traps. */ |
39 | #define EXCP_HPMC 1 /* high priority machine check */ |
40 | #define EXCP_POWER_FAIL 2 |
41 | #define EXCP_RC 3 /* recovery counter */ |
42 | #define EXCP_EXT_INTERRUPT 4 /* external interrupt */ |
43 | #define EXCP_LPMC 5 /* low priority machine check */ |
44 | #define EXCP_ITLB_MISS 6 /* itlb miss / instruction page fault */ |
45 | #define EXCP_IMP 7 /* instruction memory protection trap */ |
46 | #define EXCP_ILL 8 /* illegal instruction trap */ |
47 | #define EXCP_BREAK 9 /* break instruction */ |
48 | #define EXCP_PRIV_OPR 10 /* privileged operation trap */ |
49 | #define EXCP_PRIV_REG 11 /* privileged register trap */ |
50 | #define EXCP_OVERFLOW 12 /* signed overflow trap */ |
51 | #define EXCP_COND 13 /* trap-on-condition */ |
52 | #define EXCP_ASSIST 14 /* assist exception trap */ |
53 | #define EXCP_DTLB_MISS 15 /* dtlb miss / data page fault */ |
54 | #define EXCP_NA_ITLB_MISS 16 /* non-access itlb miss */ |
55 | #define EXCP_NA_DTLB_MISS 17 /* non-access dtlb miss */ |
56 | #define EXCP_DMP 18 /* data memory protection trap */ |
57 | #define EXCP_DMB 19 /* data memory break trap */ |
58 | #define EXCP_TLB_DIRTY 20 /* tlb dirty bit trap */ |
59 | #define EXCP_PAGE_REF 21 /* page reference trap */ |
60 | #define EXCP_ASSIST_EMU 22 /* assist emulation trap */ |
61 | #define EXCP_HPT 23 /* high-privilege transfer trap */ |
62 | #define EXCP_LPT 24 /* low-privilege transfer trap */ |
63 | #define EXCP_TB 25 /* taken branch trap */ |
64 | #define EXCP_DMAR 26 /* data memory access rights trap */ |
65 | #define EXCP_DMPI 27 /* data memory protection id trap */ |
66 | #define EXCP_UNALIGN 28 /* unaligned data reference trap */ |
67 | #define EXCP_PER_INTERRUPT 29 /* performance monitor interrupt */ |
68 | |
69 | /* Exceptions for linux-user emulation. */ |
70 | #define EXCP_SYSCALL 30 |
71 | #define EXCP_SYSCALL_LWS 31 |
72 | |
73 | /* Taken from Linux kernel: arch/parisc/include/asm/psw.h */ |
74 | #define PSW_I 0x00000001 |
75 | #define PSW_D 0x00000002 |
76 | #define PSW_P 0x00000004 |
77 | #define PSW_Q 0x00000008 |
78 | #define PSW_R 0x00000010 |
79 | #define PSW_F 0x00000020 |
80 | #define PSW_G 0x00000040 /* PA1.x only */ |
81 | #define PSW_O 0x00000080 /* PA2.0 only */ |
82 | #define PSW_CB 0x0000ff00 |
83 | #define PSW_M 0x00010000 |
84 | #define PSW_V 0x00020000 |
85 | #define PSW_C 0x00040000 |
86 | #define PSW_B 0x00080000 |
87 | #define PSW_X 0x00100000 |
88 | #define PSW_N 0x00200000 |
89 | #define PSW_L 0x00400000 |
90 | #define PSW_H 0x00800000 |
91 | #define PSW_T 0x01000000 |
92 | #define PSW_S 0x02000000 |
93 | #define PSW_E 0x04000000 |
94 | #ifdef TARGET_HPPA64 |
95 | #define PSW_W 0x08000000 /* PA2.0 only */ |
96 | #else |
97 | #define PSW_W 0 |
98 | #endif |
99 | #define PSW_Z 0x40000000 /* PA1.x only */ |
100 | #define PSW_Y 0x80000000 /* PA1.x only */ |
101 | |
102 | #define PSW_SM (PSW_W | PSW_E | PSW_O | PSW_G | PSW_F \ |
103 | | PSW_R | PSW_Q | PSW_P | PSW_D | PSW_I) |
104 | |
105 | /* ssm/rsm instructions number PSW_W and PSW_E differently */ |
106 | #define PSW_SM_I PSW_I /* Enable External Interrupts */ |
107 | #define PSW_SM_D PSW_D |
108 | #define PSW_SM_P PSW_P |
109 | #define PSW_SM_Q PSW_Q /* Enable Interrupt State Collection */ |
110 | #define PSW_SM_R PSW_R /* Enable Recover Counter Trap */ |
111 | #ifdef TARGET_HPPA64 |
112 | #define PSW_SM_E 0x100 |
113 | #define PSW_SM_W 0x200 /* PA2.0 only : Enable Wide Mode */ |
114 | #else |
115 | #define PSW_SM_E 0 |
116 | #define PSW_SM_W 0 |
117 | #endif |
118 | |
119 | #define CR_RC 0 |
120 | #define CR_PID1 8 |
121 | #define CR_PID2 9 |
122 | #define CR_PID3 12 |
123 | #define CR_PID4 13 |
124 | #define CR_SCRCCR 10 |
125 | #define CR_SAR 11 |
126 | #define CR_IVA 14 |
127 | #define CR_EIEM 15 |
128 | #define CR_IT 16 |
129 | #define CR_IIASQ 17 |
130 | #define CR_IIAOQ 18 |
131 | #define CR_IIR 19 |
132 | #define CR_ISR 20 |
133 | #define CR_IOR 21 |
134 | #define CR_IPSW 22 |
135 | #define CR_EIRR 23 |
136 | |
137 | typedef struct CPUHPPAState CPUHPPAState; |
138 | |
139 | #if TARGET_REGISTER_BITS == 32 |
140 | typedef uint32_t target_ureg; |
141 | typedef int32_t target_sreg; |
142 | #define TREG_FMT_lx "%08"PRIx32 |
143 | #define TREG_FMT_ld "%"PRId32 |
144 | #else |
145 | typedef uint64_t target_ureg; |
146 | typedef int64_t target_sreg; |
147 | #define TREG_FMT_lx "%016"PRIx64 |
148 | #define TREG_FMT_ld "%"PRId64 |
149 | #endif |
150 | |
151 | typedef struct { |
152 | uint64_t va_b; |
153 | uint64_t va_e; |
154 | target_ureg pa; |
155 | unsigned u : 1; |
156 | unsigned t : 1; |
157 | unsigned d : 1; |
158 | unsigned b : 1; |
159 | unsigned page_size : 4; |
160 | unsigned ar_type : 3; |
161 | unsigned ar_pl1 : 2; |
162 | unsigned ar_pl2 : 2; |
163 | unsigned entry_valid : 1; |
164 | unsigned access_id : 16; |
165 | } hppa_tlb_entry; |
166 | |
167 | struct CPUHPPAState { |
168 | target_ureg gr[32]; |
169 | uint64_t fr[32]; |
170 | uint64_t sr[8]; /* stored shifted into place for gva */ |
171 | |
172 | target_ureg psw; /* All psw bits except the following: */ |
173 | target_ureg psw_n; /* boolean */ |
174 | target_sreg psw_v; /* in most significant bit */ |
175 | |
176 | /* Splitting the carry-borrow field into the MSB and "the rest", allows |
177 | * for "the rest" to be deleted when it is unused, but the MSB is in use. |
178 | * In addition, it's easier to compute carry-in for bit B+1 than it is to |
179 | * compute carry-out for bit B (3 vs 4 insns for addition, assuming the |
180 | * host has the appropriate add-with-carry insn to compute the msb). |
181 | * Therefore the carry bits are stored as: cb_msb : cb & 0x11111110. |
182 | */ |
183 | target_ureg psw_cb; /* in least significant bit of next nibble */ |
184 | target_ureg psw_cb_msb; /* boolean */ |
185 | |
186 | target_ureg iaoq_f; /* front */ |
187 | target_ureg iaoq_b; /* back, aka next instruction */ |
188 | uint64_t iasq_f; |
189 | uint64_t iasq_b; |
190 | |
191 | uint32_t fr0_shadow; /* flags, c, ca/cq, rm, d, enables */ |
192 | float_status fp_status; |
193 | |
194 | target_ureg cr[32]; /* control registers */ |
195 | target_ureg cr_back[2]; /* back of cr17/cr18 */ |
196 | target_ureg shadow[7]; /* shadow registers */ |
197 | |
198 | /* ??? The number of entries isn't specified by the architecture. */ |
199 | /* ??? Implement a unified itlb/dtlb for the moment. */ |
200 | /* ??? We should use a more intelligent data structure. */ |
201 | hppa_tlb_entry tlb[256]; |
202 | uint32_t tlb_last; |
203 | }; |
204 | |
205 | /** |
206 | * HPPACPU: |
207 | * @env: #CPUHPPAState |
208 | * |
209 | * An HPPA CPU. |
210 | */ |
211 | struct HPPACPU { |
212 | /*< private >*/ |
213 | CPUState parent_obj; |
214 | /*< public >*/ |
215 | |
216 | CPUNegativeOffsetState neg; |
217 | CPUHPPAState env; |
218 | QEMUTimer *alarm_timer; |
219 | }; |
220 | |
221 | |
222 | typedef CPUHPPAState CPUArchState; |
223 | typedef HPPACPU ArchCPU; |
224 | |
225 | #include "exec/cpu-all.h" |
226 | |
227 | static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) |
228 | { |
229 | #ifdef CONFIG_USER_ONLY |
230 | return MMU_USER_IDX; |
231 | #else |
232 | if (env->psw & (ifetch ? PSW_C : PSW_D)) { |
233 | return env->iaoq_f & 3; |
234 | } |
235 | return MMU_PHYS_IDX; /* mmu disabled */ |
236 | #endif |
237 | } |
238 | |
239 | void hppa_translate_init(void); |
240 | |
241 | #define CPU_RESOLVING_TYPE TYPE_HPPA_CPU |
242 | |
243 | static inline target_ulong hppa_form_gva_psw(target_ureg psw, uint64_t spc, |
244 | target_ureg off) |
245 | { |
246 | #ifdef CONFIG_USER_ONLY |
247 | return off; |
248 | #else |
249 | off &= (psw & PSW_W ? 0x3fffffffffffffffull : 0xffffffffull); |
250 | return spc | off; |
251 | #endif |
252 | } |
253 | |
254 | static inline target_ulong hppa_form_gva(CPUHPPAState *env, uint64_t spc, |
255 | target_ureg off) |
256 | { |
257 | return hppa_form_gva_psw(env->psw, spc, off); |
258 | } |
259 | |
260 | /* Since PSW_{I,CB} will never need to be in tb->flags, reuse them. |
261 | * TB_FLAG_SR_SAME indicates that SR4 through SR7 all contain the |
262 | * same value. |
263 | */ |
264 | #define TB_FLAG_SR_SAME PSW_I |
265 | #define TB_FLAG_PRIV_SHIFT 8 |
266 | |
267 | static inline void cpu_get_tb_cpu_state(CPUHPPAState *env, target_ulong *pc, |
268 | target_ulong *cs_base, |
269 | uint32_t *pflags) |
270 | { |
271 | uint32_t flags = env->psw_n * PSW_N; |
272 | |
273 | /* TB lookup assumes that PC contains the complete virtual address. |
274 | If we leave space+offset separate, we'll get ITLB misses to an |
275 | incomplete virtual address. This also means that we must separate |
276 | out current cpu priviledge from the low bits of IAOQ_F. */ |
277 | #ifdef CONFIG_USER_ONLY |
278 | *pc = env->iaoq_f & -4; |
279 | *cs_base = env->iaoq_b & -4; |
280 | #else |
281 | /* ??? E, T, H, L, B, P bits need to be here, when implemented. */ |
282 | flags |= env->psw & (PSW_W | PSW_C | PSW_D); |
283 | flags |= (env->iaoq_f & 3) << TB_FLAG_PRIV_SHIFT; |
284 | |
285 | *pc = (env->psw & PSW_C |
286 | ? hppa_form_gva_psw(env->psw, env->iasq_f, env->iaoq_f & -4) |
287 | : env->iaoq_f & -4); |
288 | *cs_base = env->iasq_f; |
289 | |
290 | /* Insert a difference between IAOQ_B and IAOQ_F within the otherwise zero |
291 | low 32-bits of CS_BASE. This will succeed for all direct branches, |
292 | which is the primary case we care about -- using goto_tb within a page. |
293 | Failure is indicated by a zero difference. */ |
294 | if (env->iasq_f == env->iasq_b) { |
295 | target_sreg diff = env->iaoq_b - env->iaoq_f; |
296 | if (TARGET_REGISTER_BITS == 32 || diff == (int32_t)diff) { |
297 | *cs_base |= (uint32_t)diff; |
298 | } |
299 | } |
300 | if ((env->sr[4] == env->sr[5]) |
301 | & (env->sr[4] == env->sr[6]) |
302 | & (env->sr[4] == env->sr[7])) { |
303 | flags |= TB_FLAG_SR_SAME; |
304 | } |
305 | #endif |
306 | |
307 | *pflags = flags; |
308 | } |
309 | |
310 | target_ureg cpu_hppa_get_psw(CPUHPPAState *env); |
311 | void cpu_hppa_put_psw(CPUHPPAState *env, target_ureg); |
312 | void cpu_hppa_loaded_fr0(CPUHPPAState *env); |
313 | |
314 | #ifdef CONFIG_USER_ONLY |
315 | static inline void cpu_hppa_change_prot_id(CPUHPPAState *env) { } |
316 | #else |
317 | void cpu_hppa_change_prot_id(CPUHPPAState *env); |
318 | #endif |
319 | |
320 | #define cpu_signal_handler cpu_hppa_signal_handler |
321 | |
322 | int cpu_hppa_signal_handler(int host_signum, void *pinfo, void *puc); |
323 | hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); |
324 | int hppa_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); |
325 | int hppa_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); |
326 | void hppa_cpu_do_interrupt(CPUState *cpu); |
327 | bool hppa_cpu_exec_interrupt(CPUState *cpu, int int_req); |
328 | void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); |
329 | bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, |
330 | MMUAccessType access_type, int mmu_idx, |
331 | bool probe, uintptr_t retaddr); |
332 | #ifndef CONFIG_USER_ONLY |
333 | int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, |
334 | int type, hwaddr *pphys, int *pprot); |
335 | extern const MemoryRegionOps hppa_io_eir_ops; |
336 | extern const VMStateDescription vmstate_hppa_cpu; |
337 | void hppa_cpu_alarm_timer(void *); |
338 | int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr); |
339 | #endif |
340 | void QEMU_NORETURN hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra); |
341 | |
342 | #endif /* HPPA_CPU_H */ |
343 | |