1 | #include "qemu/osdep.h" |
2 | #include "cpu.h" |
3 | #include "internal.h" |
4 | #include "migration/cpu.h" |
5 | |
6 | static int cpu_post_load(void *opaque, int version_id) |
7 | { |
8 | MIPSCPU *cpu = opaque; |
9 | CPUMIPSState *env = &cpu->env; |
10 | |
11 | restore_fp_status(env); |
12 | restore_msa_fp_status(env); |
13 | compute_hflags(env); |
14 | restore_pamask(env); |
15 | |
16 | return 0; |
17 | } |
18 | |
19 | /* FPU state */ |
20 | |
21 | static int get_fpr(QEMUFile *f, void *pv, size_t size, |
22 | const VMStateField *field) |
23 | { |
24 | int i; |
25 | fpr_t *v = pv; |
26 | /* Restore entire MSA vector register */ |
27 | for (i = 0; i < MSA_WRLEN / 64; i++) { |
28 | qemu_get_sbe64s(f, &v->wr.d[i]); |
29 | } |
30 | return 0; |
31 | } |
32 | |
33 | static int put_fpr(QEMUFile *f, void *pv, size_t size, |
34 | const VMStateField *field, QJSON *vmdesc) |
35 | { |
36 | int i; |
37 | fpr_t *v = pv; |
38 | /* Save entire MSA vector register */ |
39 | for (i = 0; i < MSA_WRLEN / 64; i++) { |
40 | qemu_put_sbe64s(f, &v->wr.d[i]); |
41 | } |
42 | |
43 | return 0; |
44 | } |
45 | |
46 | const VMStateInfo vmstate_info_fpr = { |
47 | .name = "fpr" , |
48 | .get = get_fpr, |
49 | .put = put_fpr, |
50 | }; |
51 | |
52 | #define VMSTATE_FPR_ARRAY_V(_f, _s, _n, _v) \ |
53 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_fpr, fpr_t) |
54 | |
55 | #define VMSTATE_FPR_ARRAY(_f, _s, _n) \ |
56 | VMSTATE_FPR_ARRAY_V(_f, _s, _n, 0) |
57 | |
58 | static VMStateField vmstate_fpu_fields[] = { |
59 | VMSTATE_FPR_ARRAY(fpr, CPUMIPSFPUContext, 32), |
60 | VMSTATE_UINT32(fcr0, CPUMIPSFPUContext), |
61 | VMSTATE_UINT32(fcr31, CPUMIPSFPUContext), |
62 | VMSTATE_END_OF_LIST() |
63 | }; |
64 | |
65 | const VMStateDescription vmstate_fpu = { |
66 | .name = "cpu/fpu" , |
67 | .version_id = 1, |
68 | .minimum_version_id = 1, |
69 | .fields = vmstate_fpu_fields |
70 | }; |
71 | |
72 | const VMStateDescription vmstate_inactive_fpu = { |
73 | .name = "cpu/inactive_fpu" , |
74 | .version_id = 1, |
75 | .minimum_version_id = 1, |
76 | .fields = vmstate_fpu_fields |
77 | }; |
78 | |
79 | /* TC state */ |
80 | |
81 | static VMStateField vmstate_tc_fields[] = { |
82 | VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), |
83 | VMSTATE_UINTTL(PC, TCState), |
84 | VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), |
85 | VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), |
86 | VMSTATE_UINTTL_ARRAY(ACX, TCState, MIPS_DSP_ACC), |
87 | VMSTATE_UINTTL(DSPControl, TCState), |
88 | VMSTATE_INT32(CP0_TCStatus, TCState), |
89 | VMSTATE_INT32(CP0_TCBind, TCState), |
90 | VMSTATE_UINTTL(CP0_TCHalt, TCState), |
91 | VMSTATE_UINTTL(CP0_TCContext, TCState), |
92 | VMSTATE_UINTTL(CP0_TCSchedule, TCState), |
93 | VMSTATE_UINTTL(CP0_TCScheFBack, TCState), |
94 | VMSTATE_INT32(CP0_Debug_tcstatus, TCState), |
95 | VMSTATE_UINTTL(CP0_UserLocal, TCState), |
96 | VMSTATE_INT32(msacsr, TCState), |
97 | VMSTATE_END_OF_LIST() |
98 | }; |
99 | |
100 | const VMStateDescription vmstate_tc = { |
101 | .name = "cpu/tc" , |
102 | .version_id = 1, |
103 | .minimum_version_id = 1, |
104 | .fields = vmstate_tc_fields |
105 | }; |
106 | |
107 | const VMStateDescription vmstate_inactive_tc = { |
108 | .name = "cpu/inactive_tc" , |
109 | .version_id = 1, |
110 | .minimum_version_id = 1, |
111 | .fields = vmstate_tc_fields |
112 | }; |
113 | |
114 | /* MVP state */ |
115 | |
116 | const VMStateDescription vmstate_mvp = { |
117 | .name = "cpu/mvp" , |
118 | .version_id = 1, |
119 | .minimum_version_id = 1, |
120 | .fields = (VMStateField[]) { |
121 | VMSTATE_INT32(CP0_MVPControl, CPUMIPSMVPContext), |
122 | VMSTATE_INT32(CP0_MVPConf0, CPUMIPSMVPContext), |
123 | VMSTATE_INT32(CP0_MVPConf1, CPUMIPSMVPContext), |
124 | VMSTATE_END_OF_LIST() |
125 | } |
126 | }; |
127 | |
128 | /* TLB state */ |
129 | |
130 | static int get_tlb(QEMUFile *f, void *pv, size_t size, |
131 | const VMStateField *field) |
132 | { |
133 | r4k_tlb_t *v = pv; |
134 | uint16_t flags; |
135 | |
136 | qemu_get_betls(f, &v->VPN); |
137 | qemu_get_be32s(f, &v->PageMask); |
138 | qemu_get_be16s(f, &v->ASID); |
139 | qemu_get_be16s(f, &flags); |
140 | v->G = (flags >> 10) & 1; |
141 | v->C0 = (flags >> 7) & 3; |
142 | v->C1 = (flags >> 4) & 3; |
143 | v->V0 = (flags >> 3) & 1; |
144 | v->V1 = (flags >> 2) & 1; |
145 | v->D0 = (flags >> 1) & 1; |
146 | v->D1 = (flags >> 0) & 1; |
147 | v->EHINV = (flags >> 15) & 1; |
148 | v->RI1 = (flags >> 14) & 1; |
149 | v->RI0 = (flags >> 13) & 1; |
150 | v->XI1 = (flags >> 12) & 1; |
151 | v->XI0 = (flags >> 11) & 1; |
152 | qemu_get_be64s(f, &v->PFN[0]); |
153 | qemu_get_be64s(f, &v->PFN[1]); |
154 | |
155 | return 0; |
156 | } |
157 | |
158 | static int put_tlb(QEMUFile *f, void *pv, size_t size, |
159 | const VMStateField *field, QJSON *vmdesc) |
160 | { |
161 | r4k_tlb_t *v = pv; |
162 | |
163 | uint16_t asid = v->ASID; |
164 | uint16_t flags = ((v->EHINV << 15) | |
165 | (v->RI1 << 14) | |
166 | (v->RI0 << 13) | |
167 | (v->XI1 << 12) | |
168 | (v->XI0 << 11) | |
169 | (v->G << 10) | |
170 | (v->C0 << 7) | |
171 | (v->C1 << 4) | |
172 | (v->V0 << 3) | |
173 | (v->V1 << 2) | |
174 | (v->D0 << 1) | |
175 | (v->D1 << 0)); |
176 | |
177 | qemu_put_betls(f, &v->VPN); |
178 | qemu_put_be32s(f, &v->PageMask); |
179 | qemu_put_be16s(f, &asid); |
180 | qemu_put_be16s(f, &flags); |
181 | qemu_put_be64s(f, &v->PFN[0]); |
182 | qemu_put_be64s(f, &v->PFN[1]); |
183 | |
184 | return 0; |
185 | } |
186 | |
187 | const VMStateInfo vmstate_info_tlb = { |
188 | .name = "tlb_entry" , |
189 | .get = get_tlb, |
190 | .put = put_tlb, |
191 | }; |
192 | |
193 | #define VMSTATE_TLB_ARRAY_V(_f, _s, _n, _v) \ |
194 | VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_tlb, r4k_tlb_t) |
195 | |
196 | #define VMSTATE_TLB_ARRAY(_f, _s, _n) \ |
197 | VMSTATE_TLB_ARRAY_V(_f, _s, _n, 0) |
198 | |
199 | const VMStateDescription vmstate_tlb = { |
200 | .name = "cpu/tlb" , |
201 | .version_id = 2, |
202 | .minimum_version_id = 2, |
203 | .fields = (VMStateField[]) { |
204 | VMSTATE_UINT32(nb_tlb, CPUMIPSTLBContext), |
205 | VMSTATE_UINT32(tlb_in_use, CPUMIPSTLBContext), |
206 | VMSTATE_TLB_ARRAY(mmu.r4k.tlb, CPUMIPSTLBContext, MIPS_TLB_MAX), |
207 | VMSTATE_END_OF_LIST() |
208 | } |
209 | }; |
210 | |
211 | /* MIPS CPU state */ |
212 | |
213 | const VMStateDescription vmstate_mips_cpu = { |
214 | .name = "cpu" , |
215 | .version_id = 18, |
216 | .minimum_version_id = 18, |
217 | .post_load = cpu_post_load, |
218 | .fields = (VMStateField[]) { |
219 | /* Active TC */ |
220 | VMSTATE_STRUCT(env.active_tc, MIPSCPU, 1, vmstate_tc, TCState), |
221 | |
222 | /* Active FPU */ |
223 | VMSTATE_STRUCT(env.active_fpu, MIPSCPU, 1, vmstate_fpu, |
224 | CPUMIPSFPUContext), |
225 | |
226 | /* MVP */ |
227 | VMSTATE_STRUCT_POINTER(env.mvp, MIPSCPU, vmstate_mvp, |
228 | CPUMIPSMVPContext), |
229 | |
230 | /* TLB */ |
231 | VMSTATE_STRUCT_POINTER(env.tlb, MIPSCPU, vmstate_tlb, |
232 | CPUMIPSTLBContext), |
233 | |
234 | /* CPU metastate */ |
235 | VMSTATE_UINT32(env.current_tc, MIPSCPU), |
236 | VMSTATE_UINT32(env.current_fpu, MIPSCPU), |
237 | VMSTATE_INT32(env.error_code, MIPSCPU), |
238 | VMSTATE_UINTTL(env.btarget, MIPSCPU), |
239 | VMSTATE_UINTTL(env.bcond, MIPSCPU), |
240 | |
241 | /* Remaining CP0 registers */ |
242 | VMSTATE_INT32(env.CP0_Index, MIPSCPU), |
243 | VMSTATE_INT32(env.CP0_Random, MIPSCPU), |
244 | VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), |
245 | VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), |
246 | VMSTATE_INT32(env.CP0_VPEConf1, MIPSCPU), |
247 | VMSTATE_UINTTL(env.CP0_YQMask, MIPSCPU), |
248 | VMSTATE_UINTTL(env.CP0_VPESchedule, MIPSCPU), |
249 | VMSTATE_UINTTL(env.CP0_VPEScheFBack, MIPSCPU), |
250 | VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), |
251 | VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), |
252 | VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), |
253 | VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), |
254 | VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), |
255 | VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), |
256 | VMSTATE_INT32(env.CP0_PageGrain, MIPSCPU), |
257 | VMSTATE_UINTTL(env.CP0_SegCtl0, MIPSCPU), |
258 | VMSTATE_UINTTL(env.CP0_SegCtl1, MIPSCPU), |
259 | VMSTATE_UINTTL(env.CP0_SegCtl2, MIPSCPU), |
260 | VMSTATE_UINTTL(env.CP0_PWBase, MIPSCPU), |
261 | VMSTATE_UINTTL(env.CP0_PWField, MIPSCPU), |
262 | VMSTATE_UINTTL(env.CP0_PWSize, MIPSCPU), |
263 | VMSTATE_INT32(env.CP0_Wired, MIPSCPU), |
264 | VMSTATE_INT32(env.CP0_PWCtl, MIPSCPU), |
265 | VMSTATE_INT32(env.CP0_SRSConf0, MIPSCPU), |
266 | VMSTATE_INT32(env.CP0_SRSConf1, MIPSCPU), |
267 | VMSTATE_INT32(env.CP0_SRSConf2, MIPSCPU), |
268 | VMSTATE_INT32(env.CP0_SRSConf3, MIPSCPU), |
269 | VMSTATE_INT32(env.CP0_SRSConf4, MIPSCPU), |
270 | VMSTATE_INT32(env.CP0_HWREna, MIPSCPU), |
271 | VMSTATE_UINTTL(env.CP0_BadVAddr, MIPSCPU), |
272 | VMSTATE_UINT32(env.CP0_BadInstr, MIPSCPU), |
273 | VMSTATE_UINT32(env.CP0_BadInstrP, MIPSCPU), |
274 | VMSTATE_UINT32(env.CP0_BadInstrX, MIPSCPU), |
275 | VMSTATE_INT32(env.CP0_Count, MIPSCPU), |
276 | VMSTATE_UINT32(env.CP0_SAARI, MIPSCPU), |
277 | VMSTATE_UINT64_ARRAY(env.CP0_SAAR, MIPSCPU, 2), |
278 | VMSTATE_UINTTL(env.CP0_EntryHi, MIPSCPU), |
279 | VMSTATE_INT32(env.CP0_Compare, MIPSCPU), |
280 | VMSTATE_INT32(env.CP0_Status, MIPSCPU), |
281 | VMSTATE_INT32(env.CP0_IntCtl, MIPSCPU), |
282 | VMSTATE_INT32(env.CP0_SRSCtl, MIPSCPU), |
283 | VMSTATE_INT32(env.CP0_SRSMap, MIPSCPU), |
284 | VMSTATE_INT32(env.CP0_Cause, MIPSCPU), |
285 | VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), |
286 | VMSTATE_INT32(env.CP0_PRid, MIPSCPU), |
287 | VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU), |
288 | VMSTATE_INT32(env.CP0_Config0, MIPSCPU), |
289 | VMSTATE_INT32(env.CP0_Config1, MIPSCPU), |
290 | VMSTATE_INT32(env.CP0_Config2, MIPSCPU), |
291 | VMSTATE_INT32(env.CP0_Config3, MIPSCPU), |
292 | VMSTATE_INT32(env.CP0_Config6, MIPSCPU), |
293 | VMSTATE_INT32(env.CP0_Config7, MIPSCPU), |
294 | VMSTATE_UINT64(env.CP0_LLAddr, MIPSCPU), |
295 | VMSTATE_UINT64_ARRAY(env.CP0_MAAR, MIPSCPU, MIPS_MAAR_MAX), |
296 | VMSTATE_INT32(env.CP0_MAARI, MIPSCPU), |
297 | VMSTATE_UINTTL(env.lladdr, MIPSCPU), |
298 | VMSTATE_UINTTL_ARRAY(env.CP0_WatchLo, MIPSCPU, 8), |
299 | VMSTATE_INT32_ARRAY(env.CP0_WatchHi, MIPSCPU, 8), |
300 | VMSTATE_UINTTL(env.CP0_XContext, MIPSCPU), |
301 | VMSTATE_INT32(env.CP0_Framemask, MIPSCPU), |
302 | VMSTATE_INT32(env.CP0_Debug, MIPSCPU), |
303 | VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), |
304 | VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), |
305 | VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), |
306 | VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), |
307 | VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), |
308 | VMSTATE_INT32(env.CP0_DataHi, MIPSCPU), |
309 | VMSTATE_UINTTL(env.CP0_ErrorEPC, MIPSCPU), |
310 | VMSTATE_INT32(env.CP0_DESAVE, MIPSCPU), |
311 | VMSTATE_UINTTL_ARRAY(env.CP0_KScratch, MIPSCPU, MIPS_KSCRATCH_NUM), |
312 | |
313 | /* Inactive TC */ |
314 | VMSTATE_STRUCT_ARRAY(env.tcs, MIPSCPU, MIPS_SHADOW_SET_MAX, 1, |
315 | vmstate_inactive_tc, TCState), |
316 | VMSTATE_STRUCT_ARRAY(env.fpus, MIPSCPU, MIPS_FPU_MAX, 1, |
317 | vmstate_inactive_fpu, CPUMIPSFPUContext), |
318 | |
319 | VMSTATE_END_OF_LIST() |
320 | }, |
321 | }; |
322 | |