1 | /* |
2 | * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. |
3 | * |
4 | * Copyright (c) 2014 Imagination Technologies |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #include "qemu/osdep.h" |
21 | #include "cpu.h" |
22 | #include "internal.h" |
23 | #include "exec/exec-all.h" |
24 | #include "exec/helper-proto.h" |
25 | #include "fpu/softfloat.h" |
26 | |
27 | /* Data format min and max values */ |
28 | #define DF_BITS(df) (1 << ((df) + 3)) |
29 | |
30 | #define DF_MAX_INT(df) (int64_t)((1LL << (DF_BITS(df) - 1)) - 1) |
31 | #define M_MAX_INT(m) (int64_t)((1LL << ((m) - 1)) - 1) |
32 | |
33 | #define DF_MIN_INT(df) (int64_t)(-(1LL << (DF_BITS(df) - 1))) |
34 | #define M_MIN_INT(m) (int64_t)(-(1LL << ((m) - 1))) |
35 | |
36 | #define DF_MAX_UINT(df) (uint64_t)(-1ULL >> (64 - DF_BITS(df))) |
37 | #define M_MAX_UINT(m) (uint64_t)(-1ULL >> (64 - (m))) |
38 | |
39 | #define UNSIGNED(x, df) ((x) & DF_MAX_UINT(df)) |
40 | #define SIGNED(x, df) \ |
41 | ((((int64_t)x) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df))) |
42 | |
43 | /* Element-by-element access macros */ |
44 | #define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df)) |
45 | |
46 | |
47 | |
48 | /* |
49 | * Bit Count |
50 | * --------- |
51 | * |
52 | * +---------------+----------------------------------------------------------+ |
53 | * | NLOC.B | Vector Leading Ones Count (byte) | |
54 | * | NLOC.H | Vector Leading Ones Count (halfword) | |
55 | * | NLOC.W | Vector Leading Ones Count (word) | |
56 | * | NLOC.D | Vector Leading Ones Count (doubleword) | |
57 | * | NLZC.B | Vector Leading Zeros Count (byte) | |
58 | * | NLZC.H | Vector Leading Zeros Count (halfword) | |
59 | * | NLZC.W | Vector Leading Zeros Count (word) | |
60 | * | NLZC.D | Vector Leading Zeros Count (doubleword) | |
61 | * | PCNT.B | Vector Population Count (byte) | |
62 | * | PCNT.H | Vector Population Count (halfword) | |
63 | * | PCNT.W | Vector Population Count (word) | |
64 | * | PCNT.D | Vector Population Count (doubleword) | |
65 | * +---------------+----------------------------------------------------------+ |
66 | */ |
67 | |
68 | /* TODO: insert Bit Count group helpers here */ |
69 | |
70 | |
71 | /* |
72 | * Bit Move |
73 | * -------- |
74 | * |
75 | * +---------------+----------------------------------------------------------+ |
76 | * | BINSL.B | Vector Bit Insert Left (byte) | |
77 | * | BINSL.H | Vector Bit Insert Left (halfword) | |
78 | * | BINSL.W | Vector Bit Insert Left (word) | |
79 | * | BINSL.D | Vector Bit Insert Left (doubleword) | |
80 | * | BINSR.B | Vector Bit Insert Right (byte) | |
81 | * | BINSR.H | Vector Bit Insert Right (halfword) | |
82 | * | BINSR.W | Vector Bit Insert Right (word) | |
83 | * | BINSR.D | Vector Bit Insert Right (doubleword) | |
84 | * | BMNZ.V | Vector Bit Move If Not Zero | |
85 | * | BMZ.V | Vector Bit Move If Zero | |
86 | * | BSEL.V | Vector Bit Select | |
87 | * +---------------+----------------------------------------------------------+ |
88 | */ |
89 | |
90 | /* TODO: insert Bit Move group helpers here */ |
91 | |
92 | |
93 | /* |
94 | * Bit Set |
95 | * ------- |
96 | * |
97 | * +---------------+----------------------------------------------------------+ |
98 | * | BCLR.B | Vector Bit Clear (byte) | |
99 | * | BCLR.H | Vector Bit Clear (halfword) | |
100 | * | BCLR.W | Vector Bit Clear (word) | |
101 | * | BCLR.D | Vector Bit Clear (doubleword) | |
102 | * | BNEG.B | Vector Bit Negate (byte) | |
103 | * | BNEG.H | Vector Bit Negate (halfword) | |
104 | * | BNEG.W | Vector Bit Negate (word) | |
105 | * | BNEG.D | Vector Bit Negate (doubleword) | |
106 | * | BSET.B | Vector Bit Set (byte) | |
107 | * | BSET.H | Vector Bit Set (halfword) | |
108 | * | BSET.W | Vector Bit Set (word) | |
109 | * | BSET.D | Vector Bit Set (doubleword) | |
110 | * +---------------+----------------------------------------------------------+ |
111 | */ |
112 | |
113 | /* TODO: insert Bit Set group helpers here */ |
114 | |
115 | |
116 | /* |
117 | * Fixed Multiply |
118 | * -------------- |
119 | * |
120 | * +---------------+----------------------------------------------------------+ |
121 | * | MADD_Q.H | Vector Fixed-Point Multiply and Add (halfword) | |
122 | * | MADD_Q.W | Vector Fixed-Point Multiply and Add (word) | |
123 | * | MADDR_Q.H | Vector Fixed-Point Multiply and Add Rounded (halfword) | |
124 | * | MADDR_Q.W | Vector Fixed-Point Multiply and Add Rounded (word) | |
125 | * | MSUB_Q.H | Vector Fixed-Point Multiply and Subtr. (halfword) | |
126 | * | MSUB_Q.W | Vector Fixed-Point Multiply and Subtr. (word) | |
127 | * | MSUBR_Q.H | Vector Fixed-Point Multiply and Subtr. Rounded (halfword)| |
128 | * | MSUBR_Q.W | Vector Fixed-Point Multiply and Subtr. Rounded (word) | |
129 | * | MUL_Q.H | Vector Fixed-Point Multiply (halfword) | |
130 | * | MUL_Q.W | Vector Fixed-Point Multiply (word) | |
131 | * | MULR_Q.H | Vector Fixed-Point Multiply Rounded (halfword) | |
132 | * | MULR_Q.W | Vector Fixed-Point Multiply Rounded (word) | |
133 | * +---------------+----------------------------------------------------------+ |
134 | */ |
135 | |
136 | /* TODO: insert Fixed Multiply group helpers here */ |
137 | |
138 | |
139 | /* |
140 | * Float Max Min |
141 | * ------------- |
142 | * |
143 | * +---------------+----------------------------------------------------------+ |
144 | * | FMAX_A.W | Vector Floating-Point Maximum (Absolute) (word) | |
145 | * | FMAX_A.D | Vector Floating-Point Maximum (Absolute) (doubleword) | |
146 | * | FMAX.W | Vector Floating-Point Maximum (word) | |
147 | * | FMAX.D | Vector Floating-Point Maximum (doubleword) | |
148 | * | FMIN_A.W | Vector Floating-Point Minimum (Absolute) (word) | |
149 | * | FMIN_A.D | Vector Floating-Point Minimum (Absolute) (doubleword) | |
150 | * | FMIN.W | Vector Floating-Point Minimum (word) | |
151 | * | FMIN.D | Vector Floating-Point Minimum (doubleword) | |
152 | * +---------------+----------------------------------------------------------+ |
153 | */ |
154 | |
155 | /* TODO: insert Float Max Min group helpers here */ |
156 | |
157 | |
158 | /* |
159 | * Int Add |
160 | * ------- |
161 | * |
162 | * +---------------+----------------------------------------------------------+ |
163 | * | ADD_A.B | Vector Add Absolute Values (byte) | |
164 | * | ADD_A.H | Vector Add Absolute Values (halfword) | |
165 | * | ADD_A.W | Vector Add Absolute Values (word) | |
166 | * | ADD_A.D | Vector Add Absolute Values (doubleword) | |
167 | * | ADDS_A.B | Vector Signed Saturated Add (of Absolute) (byte) | |
168 | * | ADDS_A.H | Vector Signed Saturated Add (of Absolute) (halfword) | |
169 | * | ADDS_A.W | Vector Signed Saturated Add (of Absolute) (word) | |
170 | * | ADDS_A.D | Vector Signed Saturated Add (of Absolute) (doubleword) | |
171 | * | ADDS_S.B | Vector Signed Saturated Add (of Signed) (byte) | |
172 | * | ADDS_S.H | Vector Signed Saturated Add (of Signed) (halfword) | |
173 | * | ADDS_S.W | Vector Signed Saturated Add (of Signed) (word) | |
174 | * | ADDS_S.D | Vector Signed Saturated Add (of Signed) (doubleword) | |
175 | * | ADDS_U.B | Vector Unsigned Saturated Add (of Unsigned) (byte) | |
176 | * | ADDS_U.H | Vector Unsigned Saturated Add (of Unsigned) (halfword) | |
177 | * | ADDS_U.W | Vector Unsigned Saturated Add (of Unsigned) (word) | |
178 | * | ADDS_U.D | Vector Unsigned Saturated Add (of Unsigned) (doubleword) | |
179 | * | ADDV.B | Vector Add (byte) | |
180 | * | ADDV.H | Vector Add (halfword) | |
181 | * | ADDV.W | Vector Add (word) | |
182 | * | ADDV.D | Vector Add (doubleword) | |
183 | * | HADD_S.H | Vector Signed Horizontal Add (halfword) | |
184 | * | HADD_S.W | Vector Signed Horizontal Add (word) | |
185 | * | HADD_S.D | Vector Signed Horizontal Add (doubleword) | |
186 | * | HADD_U.H | Vector Unigned Horizontal Add (halfword) | |
187 | * | HADD_U.W | Vector Unigned Horizontal Add (word) | |
188 | * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) | |
189 | * +---------------+----------------------------------------------------------+ |
190 | */ |
191 | |
192 | /* TODO: insert Int Add group helpers here */ |
193 | |
194 | |
195 | /* |
196 | * Int Average |
197 | * ----------- |
198 | * |
199 | * +---------------+----------------------------------------------------------+ |
200 | * | AVE_S.B | Vector Signed Average (byte) | |
201 | * | AVE_S.H | Vector Signed Average (halfword) | |
202 | * | AVE_S.W | Vector Signed Average (word) | |
203 | * | AVE_S.D | Vector Signed Average (doubleword) | |
204 | * | AVE_U.B | Vector Unsigned Average (byte) | |
205 | * | AVE_U.H | Vector Unsigned Average (halfword) | |
206 | * | AVE_U.W | Vector Unsigned Average (word) | |
207 | * | AVE_U.D | Vector Unsigned Average (doubleword) | |
208 | * | AVER_S.B | Vector Signed Average Rounded (byte) | |
209 | * | AVER_S.H | Vector Signed Average Rounded (halfword) | |
210 | * | AVER_S.W | Vector Signed Average Rounded (word) | |
211 | * | AVER_S.D | Vector Signed Average Rounded (doubleword) | |
212 | * | AVER_U.B | Vector Unsigned Average Rounded (byte) | |
213 | * | AVER_U.H | Vector Unsigned Average Rounded (halfword) | |
214 | * | AVER_U.W | Vector Unsigned Average Rounded (word) | |
215 | * | AVER_U.D | Vector Unsigned Average Rounded (doubleword) | |
216 | * +---------------+----------------------------------------------------------+ |
217 | */ |
218 | |
219 | /* TODO: insert Int Average group helpers here */ |
220 | |
221 | |
222 | /* |
223 | * Int Compare |
224 | * ----------- |
225 | * |
226 | * +---------------+----------------------------------------------------------+ |
227 | * | CEQ.B | Vector Compare Equal (byte) | |
228 | * | CEQ.H | Vector Compare Equal (halfword) | |
229 | * | CEQ.W | Vector Compare Equal (word) | |
230 | * | CEQ.D | Vector Compare Equal (doubleword) | |
231 | * | CLE_S.B | Vector Compare Signed Less Than or Equal (byte) | |
232 | * | CLE_S.H | Vector Compare Signed Less Than or Equal (halfword) | |
233 | * | CLE_S.W | Vector Compare Signed Less Than or Equal (word) | |
234 | * | CLE_S.D | Vector Compare Signed Less Than or Equal (doubleword) | |
235 | * | CLE_U.B | Vector Compare Unsigned Less Than or Equal (byte) | |
236 | * | CLE_U.H | Vector Compare Unsigned Less Than or Equal (halfword) | |
237 | * | CLE_U.W | Vector Compare Unsigned Less Than or Equal (word) | |
238 | * | CLE_U.D | Vector Compare Unsigned Less Than or Equal (doubleword) | |
239 | * | CLT_S.B | Vector Compare Signed Less Than (byte) | |
240 | * | CLT_S.H | Vector Compare Signed Less Than (halfword) | |
241 | * | CLT_S.W | Vector Compare Signed Less Than (word) | |
242 | * | CLT_S.D | Vector Compare Signed Less Than (doubleword) | |
243 | * | CLT_U.B | Vector Compare Unsigned Less Than (byte) | |
244 | * | CLT_U.H | Vector Compare Unsigned Less Than (halfword) | |
245 | * | CLT_U.W | Vector Compare Unsigned Less Than (word) | |
246 | * | CLT_U.D | Vector Compare Unsigned Less Than (doubleword) | |
247 | * +---------------+----------------------------------------------------------+ |
248 | */ |
249 | |
250 | /* TODO: insert Int Compare group helpers here */ |
251 | |
252 | |
253 | /* |
254 | * Int Divide |
255 | * ---------- |
256 | * |
257 | * +---------------+----------------------------------------------------------+ |
258 | * | DIV_S.B | Vector Signed Divide (byte) | |
259 | * | DIV_S.H | Vector Signed Divide (halfword) | |
260 | * | DIV_S.W | Vector Signed Divide (word) | |
261 | * | DIV_S.D | Vector Signed Divide (doubleword) | |
262 | * | DIV_U.B | Vector Unsigned Divide (byte) | |
263 | * | DIV_U.H | Vector Unsigned Divide (halfword) | |
264 | * | DIV_U.W | Vector Unsigned Divide (word) | |
265 | * | DIV_U.D | Vector Unsigned Divide (doubleword) | |
266 | * +---------------+----------------------------------------------------------+ |
267 | */ |
268 | |
269 | /* TODO: insert Int Divide group helpers here */ |
270 | |
271 | |
272 | /* |
273 | * Int Dot Product |
274 | * --------------- |
275 | * |
276 | * +---------------+----------------------------------------------------------+ |
277 | * | DOTP_S.H | Vector Signed Dot Product (halfword) | |
278 | * | DOTP_S.W | Vector Signed Dot Product (word) | |
279 | * | DOTP_S.D | Vector Signed Dot Product (doubleword) | |
280 | * | DOTP_U.H | Vector Unsigned Dot Product (halfword) | |
281 | * | DOTP_U.W | Vector Unsigned Dot Product (word) | |
282 | * | DOTP_U.D | Vector Unsigned Dot Product (doubleword) | |
283 | * | DPADD_S.H | Vector Signed Dot Product (halfword) | |
284 | * | DPADD_S.W | Vector Signed Dot Product (word) | |
285 | * | DPADD_S.D | Vector Signed Dot Product (doubleword) | |
286 | * | DPADD_U.H | Vector Unsigned Dot Product (halfword) | |
287 | * | DPADD_U.W | Vector Unsigned Dot Product (word) | |
288 | * | DPADD_U.D | Vector Unsigned Dot Product (doubleword) | |
289 | * | DPSUB_S.H | Vector Signed Dot Product (halfword) | |
290 | * | DPSUB_S.W | Vector Signed Dot Product (word) | |
291 | * | DPSUB_S.D | Vector Signed Dot Product (doubleword) | |
292 | * | DPSUB_U.H | Vector Unsigned Dot Product (halfword) | |
293 | * | DPSUB_U.W | Vector Unsigned Dot Product (word) | |
294 | * | DPSUB_U.D | Vector Unsigned Dot Product (doubleword) | |
295 | * +---------------+----------------------------------------------------------+ |
296 | */ |
297 | |
298 | /* TODO: insert Int Dot Product group helpers here */ |
299 | |
300 | |
301 | /* |
302 | * Int Max Min |
303 | * ----------- |
304 | * |
305 | * +---------------+----------------------------------------------------------+ |
306 | * | MAX_A.B | Vector Maximum Based on Absolute Value (byte) | |
307 | * | MAX_A.H | Vector Maximum Based on Absolute Value (halfword) | |
308 | * | MAX_A.W | Vector Maximum Based on Absolute Value (word) | |
309 | * | MAX_A.D | Vector Maximum Based on Absolute Value (doubleword) | |
310 | * | MAX_S.B | Vector Signed Maximum (byte) | |
311 | * | MAX_S.H | Vector Signed Maximum (halfword) | |
312 | * | MAX_S.W | Vector Signed Maximum (word) | |
313 | * | MAX_S.D | Vector Signed Maximum (doubleword) | |
314 | * | MAX_U.B | Vector Unsigned Maximum (byte) | |
315 | * | MAX_U.H | Vector Unsigned Maximum (halfword) | |
316 | * | MAX_U.W | Vector Unsigned Maximum (word) | |
317 | * | MAX_U.D | Vector Unsigned Maximum (doubleword) | |
318 | * | MIN_A.B | Vector Minimum Based on Absolute Value (byte) | |
319 | * | MIN_A.H | Vector Minimum Based on Absolute Value (halfword) | |
320 | * | MIN_A.W | Vector Minimum Based on Absolute Value (word) | |
321 | * | MIN_A.D | Vector Minimum Based on Absolute Value (doubleword) | |
322 | * | MIN_S.B | Vector Signed Minimum (byte) | |
323 | * | MIN_S.H | Vector Signed Minimum (halfword) | |
324 | * | MIN_S.W | Vector Signed Minimum (word) | |
325 | * | MIN_S.D | Vector Signed Minimum (doubleword) | |
326 | * | MIN_U.B | Vector Unsigned Minimum (byte) | |
327 | * | MIN_U.H | Vector Unsigned Minimum (halfword) | |
328 | * | MIN_U.W | Vector Unsigned Minimum (word) | |
329 | * | MIN_U.D | Vector Unsigned Minimum (doubleword) | |
330 | * +---------------+----------------------------------------------------------+ |
331 | */ |
332 | |
333 | /* TODO: insert Int Max Min group helpers here */ |
334 | |
335 | |
336 | /* |
337 | * Int Modulo |
338 | * ---------- |
339 | * |
340 | * +---------------+----------------------------------------------------------+ |
341 | * | MOD_S.B | Vector Signed Modulo (byte) | |
342 | * | MOD_S.H | Vector Signed Modulo (halfword) | |
343 | * | MOD_S.W | Vector Signed Modulo (word) | |
344 | * | MOD_S.D | Vector Signed Modulo (doubleword) | |
345 | * | MOD_U.B | Vector Unsigned Modulo (byte) | |
346 | * | MOD_U.H | Vector Unsigned Modulo (halfword) | |
347 | * | MOD_U.W | Vector Unsigned Modulo (word) | |
348 | * | MOD_U.D | Vector Unsigned Modulo (doubleword) | |
349 | * +---------------+----------------------------------------------------------+ |
350 | */ |
351 | |
352 | /* TODO: insert Int Modulo group helpers here */ |
353 | |
354 | |
355 | /* |
356 | * Int Multiply |
357 | * ------------ |
358 | * |
359 | * +---------------+----------------------------------------------------------+ |
360 | * | MADDV.B | Vector Multiply and Add (byte) | |
361 | * | MADDV.H | Vector Multiply and Add (halfword) | |
362 | * | MADDV.W | Vector Multiply and Add (word) | |
363 | * | MADDV.D | Vector Multiply and Add (doubleword) | |
364 | * | MSUBV.B | Vector Multiply and Subtract (byte) | |
365 | * | MSUBV.H | Vector Multiply and Subtract (halfword) | |
366 | * | MSUBV.W | Vector Multiply and Subtract (word) | |
367 | * | MSUBV.D | Vector Multiply and Subtract (doubleword) | |
368 | * | MULV.B | Vector Multiply (byte) | |
369 | * | MULV.H | Vector Multiply (halfword) | |
370 | * | MULV.W | Vector Multiply (word) | |
371 | * | MULV.D | Vector Multiply (doubleword) | |
372 | * +---------------+----------------------------------------------------------+ |
373 | */ |
374 | |
375 | /* TODO: insert Int Multiply group helpers here */ |
376 | |
377 | |
378 | /* |
379 | * Int Subtract |
380 | * ------------ |
381 | * |
382 | * +---------------+----------------------------------------------------------+ |
383 | * | ASUB_S.B | Vector Absolute Values of Signed Subtract (byte) | |
384 | * | ASUB_S.H | Vector Absolute Values of Signed Subtract (halfword) | |
385 | * | ASUB_S.W | Vector Absolute Values of Signed Subtract (word) | |
386 | * | ASUB_S.D | Vector Absolute Values of Signed Subtract (doubleword) | |
387 | * | ASUB_U.B | Vector Absolute Values of Unsigned Subtract (byte) | |
388 | * | ASUB_U.H | Vector Absolute Values of Unsigned Subtract (halfword) | |
389 | * | ASUB_U.W | Vector Absolute Values of Unsigned Subtract (word) | |
390 | * | ASUB_U.D | Vector Absolute Values of Unsigned Subtract (doubleword) | |
391 | * | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) | |
392 | * | HSUB_S.W | Vector Signed Horizontal Subtract (word) | |
393 | * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) | |
394 | * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) | |
395 | * | HSUB_U.W | Vector Unigned Horizontal Subtract (word) | |
396 | * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) | |
397 | * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) | |
398 | * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) | |
399 | * | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) | |
400 | * | SUBS_S.D | Vector Signed Saturated Subtract (of Signed) (doubleword)| |
401 | * | SUBS_U.B | Vector Unsigned Saturated Subtract (of Uns.) (byte) | |
402 | * | SUBS_U.H | Vector Unsigned Saturated Subtract (of Uns.) (halfword) | |
403 | * | SUBS_U.W | Vector Unsigned Saturated Subtract (of Uns.) (word) | |
404 | * | SUBS_U.D | Vector Unsigned Saturated Subtract (of Uns.) (doubleword)| |
405 | * | SUBSUS_U.B | Vector Uns. Sat. Subtract (of S. from Uns.) (byte) | |
406 | * | SUBSUS_U.H | Vector Uns. Sat. Subtract (of S. from Uns.) (halfword) | |
407 | * | SUBSUS_U.W | Vector Uns. Sat. Subtract (of S. from Uns.) (word) | |
408 | * | SUBSUS_U.D | Vector Uns. Sat. Subtract (of S. from Uns.) (doubleword) | |
409 | * | SUBSUU_S.B | Vector Signed Saturated Subtract (of Uns.) (byte) | |
410 | * | SUBSUU_S.H | Vector Signed Saturated Subtract (of Uns.) (halfword) | |
411 | * | SUBSUU_S.W | Vector Signed Saturated Subtract (of Uns.) (word) | |
412 | * | SUBSUU_S.D | Vector Signed Saturated Subtract (of Uns.) (doubleword) | |
413 | * | SUBV.B | Vector Subtract (byte) | |
414 | * | SUBV.H | Vector Subtract (halfword) | |
415 | * | SUBV.W | Vector Subtract (word) | |
416 | * | SUBV.D | Vector Subtract (doubleword) | |
417 | * +---------------+----------------------------------------------------------+ |
418 | */ |
419 | |
420 | /* TODO: insert Int Subtract group helpers here */ |
421 | |
422 | |
423 | /* |
424 | * Interleave |
425 | * ---------- |
426 | * |
427 | * +---------------+----------------------------------------------------------+ |
428 | * | ILVEV.B | Vector Interleave Even (byte) | |
429 | * | ILVEV.H | Vector Interleave Even (halfword) | |
430 | * | ILVEV.W | Vector Interleave Even (word) | |
431 | * | ILVEV.D | Vector Interleave Even (doubleword) | |
432 | * | ILVOD.B | Vector Interleave Odd (byte) | |
433 | * | ILVOD.H | Vector Interleave Odd (halfword) | |
434 | * | ILVOD.W | Vector Interleave Odd (word) | |
435 | * | ILVOD.D | Vector Interleave Odd (doubleword) | |
436 | * | ILVL.B | Vector Interleave Left (byte) | |
437 | * | ILVL.H | Vector Interleave Left (halfword) | |
438 | * | ILVL.W | Vector Interleave Left (word) | |
439 | * | ILVL.D | Vector Interleave Left (doubleword) | |
440 | * | ILVR.B | Vector Interleave Right (byte) | |
441 | * | ILVR.H | Vector Interleave Right (halfword) | |
442 | * | ILVR.W | Vector Interleave Right (word) | |
443 | * | ILVR.D | Vector Interleave Right (doubleword) | |
444 | * +---------------+----------------------------------------------------------+ |
445 | */ |
446 | |
447 | /* TODO: insert Interleave group helpers here */ |
448 | |
449 | |
450 | /* |
451 | * Logic |
452 | * ----- |
453 | * |
454 | * +---------------+----------------------------------------------------------+ |
455 | * | AND.V | Vector Logical And | |
456 | * | NOR.V | Vector Logical Negated Or | |
457 | * | OR.V | Vector Logical Or | |
458 | * | XOR.V | Vector Logical Exclusive Or | |
459 | * +---------------+----------------------------------------------------------+ |
460 | */ |
461 | |
462 | /* TODO: insert Logic group helpers here */ |
463 | |
464 | |
465 | /* |
466 | * Move |
467 | * ---- |
468 | * |
469 | * +---------------+----------------------------------------------------------+ |
470 | * | MOVE.V | Vector Move | |
471 | * +---------------+----------------------------------------------------------+ |
472 | */ |
473 | |
474 | /* TODO: insert Move group helpers here */ |
475 | |
476 | |
477 | /* |
478 | * Pack |
479 | * ---- |
480 | * |
481 | * +---------------+----------------------------------------------------------+ |
482 | * | PCKEV.B | Vector Pack Even (byte) | |
483 | * | PCKEV.H | Vector Pack Even (halfword) | |
484 | * | PCKEV.W | Vector Pack Even (word) | |
485 | * | PCKEV.D | Vector Pack Even (doubleword) | |
486 | * | PCKOD.B | Vector Pack Odd (byte) | |
487 | * | PCKOD.H | Vector Pack Odd (halfword) | |
488 | * | PCKOD.W | Vector Pack Odd (word) | |
489 | * | PCKOD.D | Vector Pack Odd (doubleword) | |
490 | * | VSHF.B | Vector Data Preserving Shuffle (byte) | |
491 | * | VSHF.H | Vector Data Preserving Shuffle (halfword) | |
492 | * | VSHF.W | Vector Data Preserving Shuffle (word) | |
493 | * | VSHF.D | Vector Data Preserving Shuffle (doubleword) | |
494 | * +---------------+----------------------------------------------------------+ |
495 | */ |
496 | |
497 | /* TODO: insert Pack group helpers here */ |
498 | |
499 | |
500 | /* |
501 | * Shift |
502 | * ----- |
503 | * |
504 | * +---------------+----------------------------------------------------------+ |
505 | * | SLL.B | Vector Shift Left (byte) | |
506 | * | SLL.H | Vector Shift Left (halfword) | |
507 | * | SLL.W | Vector Shift Left (word) | |
508 | * | SLL.D | Vector Shift Left (doubleword) | |
509 | * | SRA.B | Vector Shift Right Arithmetic (byte) | |
510 | * | SRA.H | Vector Shift Right Arithmetic (halfword) | |
511 | * | SRA.W | Vector Shift Right Arithmetic (word) | |
512 | * | SRA.D | Vector Shift Right Arithmetic (doubleword) | |
513 | * | SRAR.B | Vector Shift Right Arithmetic Rounded (byte) | |
514 | * | SRAR.H | Vector Shift Right Arithmetic Rounded (halfword) | |
515 | * | SRAR.W | Vector Shift Right Arithmetic Rounded (word) | |
516 | * | SRAR.D | Vector Shift Right Arithmetic Rounded (doubleword) | |
517 | * | SRL.B | Vector Shift Right Logical (byte) | |
518 | * | SRL.H | Vector Shift Right Logical (halfword) | |
519 | * | SRL.W | Vector Shift Right Logical (word) | |
520 | * | SRL.D | Vector Shift Right Logical (doubleword) | |
521 | * | SRLR.B | Vector Shift Right Logical Rounded (byte) | |
522 | * | SRLR.H | Vector Shift Right Logical Rounded (halfword) | |
523 | * | SRLR.W | Vector Shift Right Logical Rounded (word) | |
524 | * | SRLR.D | Vector Shift Right Logical Rounded (doubleword) | |
525 | * +---------------+----------------------------------------------------------+ |
526 | */ |
527 | |
528 | /* TODO: insert Shift group helpers here */ |
529 | |
530 | |
531 | static inline void msa_move_v(wr_t *pwd, wr_t *pws) |
532 | { |
533 | uint32_t i; |
534 | |
535 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
536 | pwd->d[i] = pws->d[i]; |
537 | } |
538 | } |
539 | |
540 | #define MSA_FN_IMM8(FUNC, DEST, OPERATION) \ |
541 | void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ |
542 | uint32_t i8) \ |
543 | { \ |
544 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
545 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
546 | uint32_t i; \ |
547 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \ |
548 | DEST = OPERATION; \ |
549 | } \ |
550 | } |
551 | |
552 | MSA_FN_IMM8(andi_b, pwd->b[i], pws->b[i] & i8) |
553 | MSA_FN_IMM8(ori_b, pwd->b[i], pws->b[i] | i8) |
554 | MSA_FN_IMM8(nori_b, pwd->b[i], ~(pws->b[i] | i8)) |
555 | MSA_FN_IMM8(xori_b, pwd->b[i], pws->b[i] ^ i8) |
556 | |
557 | #define BIT_MOVE_IF_NOT_ZERO(dest, arg1, arg2, df) \ |
558 | UNSIGNED(((dest & (~arg2)) | (arg1 & arg2)), df) |
559 | MSA_FN_IMM8(bmnzi_b, pwd->b[i], |
560 | BIT_MOVE_IF_NOT_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE)) |
561 | |
562 | #define BIT_MOVE_IF_ZERO(dest, arg1, arg2, df) \ |
563 | UNSIGNED((dest & arg2) | (arg1 & (~arg2)), df) |
564 | MSA_FN_IMM8(bmzi_b, pwd->b[i], |
565 | BIT_MOVE_IF_ZERO(pwd->b[i], pws->b[i], i8, DF_BYTE)) |
566 | |
567 | #define BIT_SELECT(dest, arg1, arg2, df) \ |
568 | UNSIGNED((arg1 & (~dest)) | (arg2 & dest), df) |
569 | MSA_FN_IMM8(bseli_b, pwd->b[i], |
570 | BIT_SELECT(pwd->b[i], pws->b[i], i8, DF_BYTE)) |
571 | |
572 | #undef MSA_FN_IMM8 |
573 | |
574 | #define SHF_POS(i, imm) (((i) & 0xfc) + (((imm) >> (2 * ((i) & 0x03))) & 0x03)) |
575 | |
576 | void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
577 | uint32_t ws, uint32_t imm) |
578 | { |
579 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
580 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
581 | wr_t wx, *pwx = &wx; |
582 | uint32_t i; |
583 | |
584 | switch (df) { |
585 | case DF_BYTE: |
586 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { |
587 | pwx->b[i] = pws->b[SHF_POS(i, imm)]; |
588 | } |
589 | break; |
590 | case DF_HALF: |
591 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { |
592 | pwx->h[i] = pws->h[SHF_POS(i, imm)]; |
593 | } |
594 | break; |
595 | case DF_WORD: |
596 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
597 | pwx->w[i] = pws->w[SHF_POS(i, imm)]; |
598 | } |
599 | break; |
600 | default: |
601 | assert(0); |
602 | } |
603 | msa_move_v(pwd, pwx); |
604 | } |
605 | |
606 | #define MSA_FN_VECTOR(FUNC, DEST, OPERATION) \ |
607 | void helper_msa_ ## FUNC(CPUMIPSState *env, uint32_t wd, uint32_t ws, \ |
608 | uint32_t wt) \ |
609 | { \ |
610 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
611 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
612 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \ |
613 | uint32_t i; \ |
614 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ |
615 | DEST = OPERATION; \ |
616 | } \ |
617 | } |
618 | |
619 | MSA_FN_VECTOR(bmnz_v, pwd->d[i], |
620 | BIT_MOVE_IF_NOT_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) |
621 | MSA_FN_VECTOR(bmz_v, pwd->d[i], |
622 | BIT_MOVE_IF_ZERO(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) |
623 | MSA_FN_VECTOR(bsel_v, pwd->d[i], |
624 | BIT_SELECT(pwd->d[i], pws->d[i], pwt->d[i], DF_DOUBLE)) |
625 | #undef BIT_MOVE_IF_NOT_ZERO |
626 | #undef BIT_MOVE_IF_ZERO |
627 | #undef BIT_SELECT |
628 | #undef MSA_FN_VECTOR |
629 | |
630 | void helper_msa_and_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) |
631 | { |
632 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
633 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
634 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
635 | |
636 | pwd->d[0] = pws->d[0] & pwt->d[0]; |
637 | pwd->d[1] = pws->d[1] & pwt->d[1]; |
638 | } |
639 | |
640 | void helper_msa_or_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) |
641 | { |
642 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
643 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
644 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
645 | |
646 | pwd->d[0] = pws->d[0] | pwt->d[0]; |
647 | pwd->d[1] = pws->d[1] | pwt->d[1]; |
648 | } |
649 | |
650 | void helper_msa_nor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) |
651 | { |
652 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
653 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
654 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
655 | |
656 | pwd->d[0] = ~(pws->d[0] | pwt->d[0]); |
657 | pwd->d[1] = ~(pws->d[1] | pwt->d[1]); |
658 | } |
659 | |
660 | void helper_msa_xor_v(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) |
661 | { |
662 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
663 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
664 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
665 | |
666 | pwd->d[0] = pws->d[0] ^ pwt->d[0]; |
667 | pwd->d[1] = pws->d[1] ^ pwt->d[1]; |
668 | } |
669 | |
670 | static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2) |
671 | { |
672 | return arg1 + arg2; |
673 | } |
674 | |
675 | static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2) |
676 | { |
677 | return arg1 - arg2; |
678 | } |
679 | |
680 | static inline int64_t msa_ceq_df(uint32_t df, int64_t arg1, int64_t arg2) |
681 | { |
682 | return arg1 == arg2 ? -1 : 0; |
683 | } |
684 | |
685 | static inline int64_t msa_cle_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
686 | { |
687 | return arg1 <= arg2 ? -1 : 0; |
688 | } |
689 | |
690 | static inline int64_t msa_cle_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
691 | { |
692 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
693 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
694 | return u_arg1 <= u_arg2 ? -1 : 0; |
695 | } |
696 | |
697 | static inline int64_t msa_clt_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
698 | { |
699 | return arg1 < arg2 ? -1 : 0; |
700 | } |
701 | |
702 | static inline int64_t msa_clt_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
703 | { |
704 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
705 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
706 | return u_arg1 < u_arg2 ? -1 : 0; |
707 | } |
708 | |
709 | static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
710 | { |
711 | return arg1 > arg2 ? arg1 : arg2; |
712 | } |
713 | |
714 | static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
715 | { |
716 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
717 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
718 | return u_arg1 > u_arg2 ? arg1 : arg2; |
719 | } |
720 | |
721 | static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
722 | { |
723 | return arg1 < arg2 ? arg1 : arg2; |
724 | } |
725 | |
726 | static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
727 | { |
728 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
729 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
730 | return u_arg1 < u_arg2 ? arg1 : arg2; |
731 | } |
732 | |
733 | #define MSA_BINOP_IMM_DF(helper, func) \ |
734 | void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ |
735 | uint32_t wd, uint32_t ws, int32_t u5) \ |
736 | { \ |
737 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
738 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
739 | uint32_t i; \ |
740 | \ |
741 | switch (df) { \ |
742 | case DF_BYTE: \ |
743 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \ |
744 | pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \ |
745 | } \ |
746 | break; \ |
747 | case DF_HALF: \ |
748 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \ |
749 | pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \ |
750 | } \ |
751 | break; \ |
752 | case DF_WORD: \ |
753 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \ |
754 | pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \ |
755 | } \ |
756 | break; \ |
757 | case DF_DOUBLE: \ |
758 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ |
759 | pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \ |
760 | } \ |
761 | break; \ |
762 | default: \ |
763 | assert(0); \ |
764 | } \ |
765 | } |
766 | |
767 | MSA_BINOP_IMM_DF(addvi, addv) |
768 | MSA_BINOP_IMM_DF(subvi, subv) |
769 | MSA_BINOP_IMM_DF(ceqi, ceq) |
770 | MSA_BINOP_IMM_DF(clei_s, cle_s) |
771 | MSA_BINOP_IMM_DF(clei_u, cle_u) |
772 | MSA_BINOP_IMM_DF(clti_s, clt_s) |
773 | MSA_BINOP_IMM_DF(clti_u, clt_u) |
774 | MSA_BINOP_IMM_DF(maxi_s, max_s) |
775 | MSA_BINOP_IMM_DF(maxi_u, max_u) |
776 | MSA_BINOP_IMM_DF(mini_s, min_s) |
777 | MSA_BINOP_IMM_DF(mini_u, min_u) |
778 | #undef MSA_BINOP_IMM_DF |
779 | |
780 | void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
781 | int32_t s10) |
782 | { |
783 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
784 | uint32_t i; |
785 | |
786 | switch (df) { |
787 | case DF_BYTE: |
788 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { |
789 | pwd->b[i] = (int8_t)s10; |
790 | } |
791 | break; |
792 | case DF_HALF: |
793 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { |
794 | pwd->h[i] = (int16_t)s10; |
795 | } |
796 | break; |
797 | case DF_WORD: |
798 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
799 | pwd->w[i] = (int32_t)s10; |
800 | } |
801 | break; |
802 | case DF_DOUBLE: |
803 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
804 | pwd->d[i] = (int64_t)s10; |
805 | } |
806 | break; |
807 | default: |
808 | assert(0); |
809 | } |
810 | } |
811 | |
812 | /* Data format bit position and unsigned values */ |
813 | #define BIT_POSITION(x, df) ((uint64_t)(x) % DF_BITS(df)) |
814 | |
815 | static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2) |
816 | { |
817 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
818 | return arg1 << b_arg2; |
819 | } |
820 | |
821 | static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2) |
822 | { |
823 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
824 | return arg1 >> b_arg2; |
825 | } |
826 | |
827 | static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2) |
828 | { |
829 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
830 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
831 | return u_arg1 >> b_arg2; |
832 | } |
833 | |
834 | static inline int64_t msa_bclr_df(uint32_t df, int64_t arg1, int64_t arg2) |
835 | { |
836 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
837 | return UNSIGNED(arg1 & (~(1LL << b_arg2)), df); |
838 | } |
839 | |
840 | static inline int64_t msa_bset_df(uint32_t df, int64_t arg1, |
841 | int64_t arg2) |
842 | { |
843 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
844 | return UNSIGNED(arg1 | (1LL << b_arg2), df); |
845 | } |
846 | |
847 | static inline int64_t msa_bneg_df(uint32_t df, int64_t arg1, int64_t arg2) |
848 | { |
849 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
850 | return UNSIGNED(arg1 ^ (1LL << b_arg2), df); |
851 | } |
852 | |
853 | static inline int64_t msa_binsl_df(uint32_t df, int64_t dest, int64_t arg1, |
854 | int64_t arg2) |
855 | { |
856 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
857 | uint64_t u_dest = UNSIGNED(dest, df); |
858 | int32_t sh_d = BIT_POSITION(arg2, df) + 1; |
859 | int32_t sh_a = DF_BITS(df) - sh_d; |
860 | if (sh_d == DF_BITS(df)) { |
861 | return u_arg1; |
862 | } else { |
863 | return UNSIGNED(UNSIGNED(u_dest << sh_d, df) >> sh_d, df) | |
864 | UNSIGNED(UNSIGNED(u_arg1 >> sh_a, df) << sh_a, df); |
865 | } |
866 | } |
867 | |
868 | static inline int64_t msa_binsr_df(uint32_t df, int64_t dest, int64_t arg1, |
869 | int64_t arg2) |
870 | { |
871 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
872 | uint64_t u_dest = UNSIGNED(dest, df); |
873 | int32_t sh_d = BIT_POSITION(arg2, df) + 1; |
874 | int32_t sh_a = DF_BITS(df) - sh_d; |
875 | if (sh_d == DF_BITS(df)) { |
876 | return u_arg1; |
877 | } else { |
878 | return UNSIGNED(UNSIGNED(u_dest >> sh_d, df) << sh_d, df) | |
879 | UNSIGNED(UNSIGNED(u_arg1 << sh_a, df) >> sh_a, df); |
880 | } |
881 | } |
882 | |
883 | static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m) |
884 | { |
885 | return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) : |
886 | arg > M_MAX_INT(m + 1) ? M_MAX_INT(m + 1) : |
887 | arg; |
888 | } |
889 | |
890 | static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m) |
891 | { |
892 | uint64_t u_arg = UNSIGNED(arg, df); |
893 | return u_arg < M_MAX_UINT(m + 1) ? u_arg : |
894 | M_MAX_UINT(m + 1); |
895 | } |
896 | |
897 | static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2) |
898 | { |
899 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
900 | if (b_arg2 == 0) { |
901 | return arg1; |
902 | } else { |
903 | int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1; |
904 | return (arg1 >> b_arg2) + r_bit; |
905 | } |
906 | } |
907 | |
908 | static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2) |
909 | { |
910 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
911 | int32_t b_arg2 = BIT_POSITION(arg2, df); |
912 | if (b_arg2 == 0) { |
913 | return u_arg1; |
914 | } else { |
915 | uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1; |
916 | return (u_arg1 >> b_arg2) + r_bit; |
917 | } |
918 | } |
919 | |
920 | #define MSA_BINOP_IMMU_DF(helper, func) \ |
921 | void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \ |
922 | uint32_t ws, uint32_t u5) \ |
923 | { \ |
924 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
925 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
926 | uint32_t i; \ |
927 | \ |
928 | switch (df) { \ |
929 | case DF_BYTE: \ |
930 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \ |
931 | pwd->b[i] = msa_ ## func ## _df(df, pws->b[i], u5); \ |
932 | } \ |
933 | break; \ |
934 | case DF_HALF: \ |
935 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \ |
936 | pwd->h[i] = msa_ ## func ## _df(df, pws->h[i], u5); \ |
937 | } \ |
938 | break; \ |
939 | case DF_WORD: \ |
940 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \ |
941 | pwd->w[i] = msa_ ## func ## _df(df, pws->w[i], u5); \ |
942 | } \ |
943 | break; \ |
944 | case DF_DOUBLE: \ |
945 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ |
946 | pwd->d[i] = msa_ ## func ## _df(df, pws->d[i], u5); \ |
947 | } \ |
948 | break; \ |
949 | default: \ |
950 | assert(0); \ |
951 | } \ |
952 | } |
953 | |
954 | MSA_BINOP_IMMU_DF(slli, sll) |
955 | MSA_BINOP_IMMU_DF(srai, sra) |
956 | MSA_BINOP_IMMU_DF(srli, srl) |
957 | MSA_BINOP_IMMU_DF(bclri, bclr) |
958 | MSA_BINOP_IMMU_DF(bseti, bset) |
959 | MSA_BINOP_IMMU_DF(bnegi, bneg) |
960 | MSA_BINOP_IMMU_DF(sat_s, sat_s) |
961 | MSA_BINOP_IMMU_DF(sat_u, sat_u) |
962 | MSA_BINOP_IMMU_DF(srari, srar) |
963 | MSA_BINOP_IMMU_DF(srlri, srlr) |
964 | #undef MSA_BINOP_IMMU_DF |
965 | |
966 | #define MSA_TEROP_IMMU_DF(helper, func) \ |
967 | void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \ |
968 | uint32_t wd, uint32_t ws, uint32_t u5) \ |
969 | { \ |
970 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
971 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
972 | uint32_t i; \ |
973 | \ |
974 | switch (df) { \ |
975 | case DF_BYTE: \ |
976 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { \ |
977 | pwd->b[i] = msa_ ## func ## _df(df, pwd->b[i], pws->b[i], \ |
978 | u5); \ |
979 | } \ |
980 | break; \ |
981 | case DF_HALF: \ |
982 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { \ |
983 | pwd->h[i] = msa_ ## func ## _df(df, pwd->h[i], pws->h[i], \ |
984 | u5); \ |
985 | } \ |
986 | break; \ |
987 | case DF_WORD: \ |
988 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { \ |
989 | pwd->w[i] = msa_ ## func ## _df(df, pwd->w[i], pws->w[i], \ |
990 | u5); \ |
991 | } \ |
992 | break; \ |
993 | case DF_DOUBLE: \ |
994 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { \ |
995 | pwd->d[i] = msa_ ## func ## _df(df, pwd->d[i], pws->d[i], \ |
996 | u5); \ |
997 | } \ |
998 | break; \ |
999 | default: \ |
1000 | assert(0); \ |
1001 | } \ |
1002 | } |
1003 | |
1004 | MSA_TEROP_IMMU_DF(binsli, binsl) |
1005 | MSA_TEROP_IMMU_DF(binsri, binsr) |
1006 | #undef MSA_TEROP_IMMU_DF |
1007 | |
1008 | static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2) |
1009 | { |
1010 | uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; |
1011 | uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; |
1012 | return abs_arg1 > abs_arg2 ? arg1 : arg2; |
1013 | } |
1014 | |
1015 | static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2) |
1016 | { |
1017 | uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; |
1018 | uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; |
1019 | return abs_arg1 < abs_arg2 ? arg1 : arg2; |
1020 | } |
1021 | |
1022 | static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2) |
1023 | { |
1024 | uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; |
1025 | uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; |
1026 | return abs_arg1 + abs_arg2; |
1027 | } |
1028 | |
1029 | static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2) |
1030 | { |
1031 | uint64_t max_int = (uint64_t)DF_MAX_INT(df); |
1032 | uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1; |
1033 | uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2; |
1034 | if (abs_arg1 > max_int || abs_arg2 > max_int) { |
1035 | return (int64_t)max_int; |
1036 | } else { |
1037 | return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int; |
1038 | } |
1039 | } |
1040 | |
1041 | static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1042 | { |
1043 | int64_t max_int = DF_MAX_INT(df); |
1044 | int64_t min_int = DF_MIN_INT(df); |
1045 | if (arg1 < 0) { |
1046 | return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int; |
1047 | } else { |
1048 | return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int; |
1049 | } |
1050 | } |
1051 | |
1052 | static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) |
1053 | { |
1054 | uint64_t max_uint = DF_MAX_UINT(df); |
1055 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1056 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1057 | return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint; |
1058 | } |
1059 | |
1060 | static inline int64_t msa_ave_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1061 | { |
1062 | /* signed shift */ |
1063 | return (arg1 >> 1) + (arg2 >> 1) + (arg1 & arg2 & 1); |
1064 | } |
1065 | |
1066 | static inline uint64_t msa_ave_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) |
1067 | { |
1068 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1069 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1070 | /* unsigned shift */ |
1071 | return (u_arg1 >> 1) + (u_arg2 >> 1) + (u_arg1 & u_arg2 & 1); |
1072 | } |
1073 | |
1074 | static inline int64_t msa_aver_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1075 | { |
1076 | /* signed shift */ |
1077 | return (arg1 >> 1) + (arg2 >> 1) + ((arg1 | arg2) & 1); |
1078 | } |
1079 | |
1080 | static inline uint64_t msa_aver_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) |
1081 | { |
1082 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1083 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1084 | /* unsigned shift */ |
1085 | return (u_arg1 >> 1) + (u_arg2 >> 1) + ((u_arg1 | u_arg2) & 1); |
1086 | } |
1087 | |
1088 | static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1089 | { |
1090 | int64_t max_int = DF_MAX_INT(df); |
1091 | int64_t min_int = DF_MIN_INT(df); |
1092 | if (arg2 > 0) { |
1093 | return (min_int + arg2 < arg1) ? arg1 - arg2 : min_int; |
1094 | } else { |
1095 | return (arg1 < max_int + arg2) ? arg1 - arg2 : max_int; |
1096 | } |
1097 | } |
1098 | |
1099 | static inline int64_t msa_subs_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1100 | { |
1101 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1102 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1103 | return (u_arg1 > u_arg2) ? u_arg1 - u_arg2 : 0; |
1104 | } |
1105 | |
1106 | static inline int64_t msa_subsus_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1107 | { |
1108 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1109 | uint64_t max_uint = DF_MAX_UINT(df); |
1110 | if (arg2 >= 0) { |
1111 | uint64_t u_arg2 = (uint64_t)arg2; |
1112 | return (u_arg1 > u_arg2) ? |
1113 | (int64_t)(u_arg1 - u_arg2) : |
1114 | 0; |
1115 | } else { |
1116 | uint64_t u_arg2 = (uint64_t)(-arg2); |
1117 | return (u_arg1 < max_uint - u_arg2) ? |
1118 | (int64_t)(u_arg1 + u_arg2) : |
1119 | (int64_t)max_uint; |
1120 | } |
1121 | } |
1122 | |
1123 | static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1124 | { |
1125 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1126 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1127 | int64_t max_int = DF_MAX_INT(df); |
1128 | int64_t min_int = DF_MIN_INT(df); |
1129 | if (u_arg1 > u_arg2) { |
1130 | return u_arg1 - u_arg2 < (uint64_t)max_int ? |
1131 | (int64_t)(u_arg1 - u_arg2) : |
1132 | max_int; |
1133 | } else { |
1134 | return u_arg2 - u_arg1 < (uint64_t)(-min_int) ? |
1135 | (int64_t)(u_arg1 - u_arg2) : |
1136 | min_int; |
1137 | } |
1138 | } |
1139 | |
1140 | static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1141 | { |
1142 | /* signed compare */ |
1143 | return (arg1 < arg2) ? |
1144 | (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2); |
1145 | } |
1146 | |
1147 | static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2) |
1148 | { |
1149 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1150 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1151 | /* unsigned compare */ |
1152 | return (u_arg1 < u_arg2) ? |
1153 | (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2); |
1154 | } |
1155 | |
1156 | static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2) |
1157 | { |
1158 | return arg1 * arg2; |
1159 | } |
1160 | |
1161 | static inline int64_t msa_div_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1162 | { |
1163 | if (arg1 == DF_MIN_INT(df) && arg2 == -1) { |
1164 | return DF_MIN_INT(df); |
1165 | } |
1166 | return arg2 ? arg1 / arg2 |
1167 | : arg1 >= 0 ? -1 : 1; |
1168 | } |
1169 | |
1170 | static inline int64_t msa_div_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1171 | { |
1172 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1173 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1174 | return arg2 ? u_arg1 / u_arg2 : -1; |
1175 | } |
1176 | |
1177 | static inline int64_t msa_mod_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1178 | { |
1179 | if (arg1 == DF_MIN_INT(df) && arg2 == -1) { |
1180 | return 0; |
1181 | } |
1182 | return arg2 ? arg1 % arg2 : arg1; |
1183 | } |
1184 | |
1185 | static inline int64_t msa_mod_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1186 | { |
1187 | uint64_t u_arg1 = UNSIGNED(arg1, df); |
1188 | uint64_t u_arg2 = UNSIGNED(arg2, df); |
1189 | return u_arg2 ? u_arg1 % u_arg2 : u_arg1; |
1190 | } |
1191 | |
1192 | #define SIGNED_EVEN(a, df) \ |
1193 | ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2)) |
1194 | |
1195 | #define UNSIGNED_EVEN(a, df) \ |
1196 | ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2)) |
1197 | |
1198 | #define SIGNED_ODD(a, df) \ |
1199 | ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) |
1200 | |
1201 | #define UNSIGNED_ODD(a, df) \ |
1202 | ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2)) |
1203 | |
1204 | #define (e, o, a, df) \ |
1205 | do { \ |
1206 | e = SIGNED_EVEN(a, df); \ |
1207 | o = SIGNED_ODD(a, df); \ |
1208 | } while (0) |
1209 | |
1210 | #define (e, o, a, df) \ |
1211 | do { \ |
1212 | e = UNSIGNED_EVEN(a, df); \ |
1213 | o = UNSIGNED_ODD(a, df); \ |
1214 | } while (0) |
1215 | |
1216 | static inline int64_t msa_dotp_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1217 | { |
1218 | int64_t even_arg1; |
1219 | int64_t even_arg2; |
1220 | int64_t odd_arg1; |
1221 | int64_t odd_arg2; |
1222 | SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df); |
1223 | SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df); |
1224 | return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2); |
1225 | } |
1226 | |
1227 | static inline int64_t msa_dotp_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1228 | { |
1229 | int64_t even_arg1; |
1230 | int64_t even_arg2; |
1231 | int64_t odd_arg1; |
1232 | int64_t odd_arg2; |
1233 | UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df); |
1234 | UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df); |
1235 | return (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2); |
1236 | } |
1237 | |
1238 | #define CONCATENATE_AND_SLIDE(s, k) \ |
1239 | do { \ |
1240 | for (i = 0; i < s; i++) { \ |
1241 | v[i] = pws->b[s * k + i]; \ |
1242 | v[i + s] = pwd->b[s * k + i]; \ |
1243 | } \ |
1244 | for (i = 0; i < s; i++) { \ |
1245 | pwd->b[s * k + i] = v[i + n]; \ |
1246 | } \ |
1247 | } while (0) |
1248 | |
1249 | static inline void msa_sld_df(uint32_t df, wr_t *pwd, |
1250 | wr_t *pws, target_ulong rt) |
1251 | { |
1252 | uint32_t n = rt % DF_ELEMENTS(df); |
1253 | uint8_t v[64]; |
1254 | uint32_t i, k; |
1255 | |
1256 | switch (df) { |
1257 | case DF_BYTE: |
1258 | CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_BYTE), 0); |
1259 | break; |
1260 | case DF_HALF: |
1261 | for (k = 0; k < 2; k++) { |
1262 | CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_HALF), k); |
1263 | } |
1264 | break; |
1265 | case DF_WORD: |
1266 | for (k = 0; k < 4; k++) { |
1267 | CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_WORD), k); |
1268 | } |
1269 | break; |
1270 | case DF_DOUBLE: |
1271 | for (k = 0; k < 8; k++) { |
1272 | CONCATENATE_AND_SLIDE(DF_ELEMENTS(DF_DOUBLE), k); |
1273 | } |
1274 | break; |
1275 | default: |
1276 | assert(0); |
1277 | } |
1278 | } |
1279 | |
1280 | static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1281 | { |
1282 | return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df); |
1283 | } |
1284 | |
1285 | static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1286 | { |
1287 | return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df); |
1288 | } |
1289 | |
1290 | static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2) |
1291 | { |
1292 | return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df); |
1293 | } |
1294 | |
1295 | static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2) |
1296 | { |
1297 | return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df); |
1298 | } |
1299 | |
1300 | static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2) |
1301 | { |
1302 | int64_t q_min = DF_MIN_INT(df); |
1303 | int64_t q_max = DF_MAX_INT(df); |
1304 | |
1305 | if (arg1 == q_min && arg2 == q_min) { |
1306 | return q_max; |
1307 | } |
1308 | return (arg1 * arg2) >> (DF_BITS(df) - 1); |
1309 | } |
1310 | |
1311 | static inline int64_t msa_mulr_q_df(uint32_t df, int64_t arg1, int64_t arg2) |
1312 | { |
1313 | int64_t q_min = DF_MIN_INT(df); |
1314 | int64_t q_max = DF_MAX_INT(df); |
1315 | int64_t r_bit = 1 << (DF_BITS(df) - 2); |
1316 | |
1317 | if (arg1 == q_min && arg2 == q_min) { |
1318 | return q_max; |
1319 | } |
1320 | return (arg1 * arg2 + r_bit) >> (DF_BITS(df) - 1); |
1321 | } |
1322 | |
1323 | #define MSA_BINOP_DF(func) \ |
1324 | void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \ |
1325 | uint32_t wd, uint32_t ws, uint32_t wt) \ |
1326 | { \ |
1327 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
1328 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
1329 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \ |
1330 | \ |
1331 | switch (df) { \ |
1332 | case DF_BYTE: \ |
1333 | pwd->b[0] = msa_ ## func ## _df(df, pws->b[0], pwt->b[0]); \ |
1334 | pwd->b[1] = msa_ ## func ## _df(df, pws->b[1], pwt->b[1]); \ |
1335 | pwd->b[2] = msa_ ## func ## _df(df, pws->b[2], pwt->b[2]); \ |
1336 | pwd->b[3] = msa_ ## func ## _df(df, pws->b[3], pwt->b[3]); \ |
1337 | pwd->b[4] = msa_ ## func ## _df(df, pws->b[4], pwt->b[4]); \ |
1338 | pwd->b[5] = msa_ ## func ## _df(df, pws->b[5], pwt->b[5]); \ |
1339 | pwd->b[6] = msa_ ## func ## _df(df, pws->b[6], pwt->b[6]); \ |
1340 | pwd->b[7] = msa_ ## func ## _df(df, pws->b[7], pwt->b[7]); \ |
1341 | pwd->b[8] = msa_ ## func ## _df(df, pws->b[8], pwt->b[8]); \ |
1342 | pwd->b[9] = msa_ ## func ## _df(df, pws->b[9], pwt->b[9]); \ |
1343 | pwd->b[10] = msa_ ## func ## _df(df, pws->b[10], pwt->b[10]); \ |
1344 | pwd->b[11] = msa_ ## func ## _df(df, pws->b[11], pwt->b[11]); \ |
1345 | pwd->b[12] = msa_ ## func ## _df(df, pws->b[12], pwt->b[12]); \ |
1346 | pwd->b[13] = msa_ ## func ## _df(df, pws->b[13], pwt->b[13]); \ |
1347 | pwd->b[14] = msa_ ## func ## _df(df, pws->b[14], pwt->b[14]); \ |
1348 | pwd->b[15] = msa_ ## func ## _df(df, pws->b[15], pwt->b[15]); \ |
1349 | break; \ |
1350 | case DF_HALF: \ |
1351 | pwd->h[0] = msa_ ## func ## _df(df, pws->h[0], pwt->h[0]); \ |
1352 | pwd->h[1] = msa_ ## func ## _df(df, pws->h[1], pwt->h[1]); \ |
1353 | pwd->h[2] = msa_ ## func ## _df(df, pws->h[2], pwt->h[2]); \ |
1354 | pwd->h[3] = msa_ ## func ## _df(df, pws->h[3], pwt->h[3]); \ |
1355 | pwd->h[4] = msa_ ## func ## _df(df, pws->h[4], pwt->h[4]); \ |
1356 | pwd->h[5] = msa_ ## func ## _df(df, pws->h[5], pwt->h[5]); \ |
1357 | pwd->h[6] = msa_ ## func ## _df(df, pws->h[6], pwt->h[6]); \ |
1358 | pwd->h[7] = msa_ ## func ## _df(df, pws->h[7], pwt->h[7]); \ |
1359 | break; \ |
1360 | case DF_WORD: \ |
1361 | pwd->w[0] = msa_ ## func ## _df(df, pws->w[0], pwt->w[0]); \ |
1362 | pwd->w[1] = msa_ ## func ## _df(df, pws->w[1], pwt->w[1]); \ |
1363 | pwd->w[2] = msa_ ## func ## _df(df, pws->w[2], pwt->w[2]); \ |
1364 | pwd->w[3] = msa_ ## func ## _df(df, pws->w[3], pwt->w[3]); \ |
1365 | break; \ |
1366 | case DF_DOUBLE: \ |
1367 | pwd->d[0] = msa_ ## func ## _df(df, pws->d[0], pwt->d[0]); \ |
1368 | pwd->d[1] = msa_ ## func ## _df(df, pws->d[1], pwt->d[1]); \ |
1369 | break; \ |
1370 | default: \ |
1371 | assert(0); \ |
1372 | } \ |
1373 | } |
1374 | |
1375 | MSA_BINOP_DF(sll) |
1376 | MSA_BINOP_DF(sra) |
1377 | MSA_BINOP_DF(srl) |
1378 | MSA_BINOP_DF(bclr) |
1379 | MSA_BINOP_DF(bset) |
1380 | MSA_BINOP_DF(bneg) |
1381 | MSA_BINOP_DF(addv) |
1382 | MSA_BINOP_DF(subv) |
1383 | MSA_BINOP_DF(max_s) |
1384 | MSA_BINOP_DF(max_u) |
1385 | MSA_BINOP_DF(min_s) |
1386 | MSA_BINOP_DF(min_u) |
1387 | MSA_BINOP_DF(max_a) |
1388 | MSA_BINOP_DF(min_a) |
1389 | MSA_BINOP_DF(ceq) |
1390 | MSA_BINOP_DF(clt_s) |
1391 | MSA_BINOP_DF(clt_u) |
1392 | MSA_BINOP_DF(cle_s) |
1393 | MSA_BINOP_DF(cle_u) |
1394 | MSA_BINOP_DF(add_a) |
1395 | MSA_BINOP_DF(adds_a) |
1396 | MSA_BINOP_DF(adds_s) |
1397 | MSA_BINOP_DF(adds_u) |
1398 | MSA_BINOP_DF(ave_s) |
1399 | MSA_BINOP_DF(ave_u) |
1400 | MSA_BINOP_DF(aver_s) |
1401 | MSA_BINOP_DF(aver_u) |
1402 | MSA_BINOP_DF(subs_s) |
1403 | MSA_BINOP_DF(subs_u) |
1404 | MSA_BINOP_DF(subsus_u) |
1405 | MSA_BINOP_DF(subsuu_s) |
1406 | MSA_BINOP_DF(asub_s) |
1407 | MSA_BINOP_DF(asub_u) |
1408 | MSA_BINOP_DF(mulv) |
1409 | MSA_BINOP_DF(div_s) |
1410 | MSA_BINOP_DF(div_u) |
1411 | MSA_BINOP_DF(mod_s) |
1412 | MSA_BINOP_DF(mod_u) |
1413 | MSA_BINOP_DF(dotp_s) |
1414 | MSA_BINOP_DF(dotp_u) |
1415 | MSA_BINOP_DF(srar) |
1416 | MSA_BINOP_DF(srlr) |
1417 | MSA_BINOP_DF(hadd_s) |
1418 | MSA_BINOP_DF(hadd_u) |
1419 | MSA_BINOP_DF(hsub_s) |
1420 | MSA_BINOP_DF(hsub_u) |
1421 | |
1422 | MSA_BINOP_DF(mul_q) |
1423 | MSA_BINOP_DF(mulr_q) |
1424 | #undef MSA_BINOP_DF |
1425 | |
1426 | void helper_msa_sld_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
1427 | uint32_t ws, uint32_t rt) |
1428 | { |
1429 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
1430 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
1431 | |
1432 | msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]); |
1433 | } |
1434 | |
1435 | static inline int64_t msa_maddv_df(uint32_t df, int64_t dest, int64_t arg1, |
1436 | int64_t arg2) |
1437 | { |
1438 | return dest + arg1 * arg2; |
1439 | } |
1440 | |
1441 | static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1, |
1442 | int64_t arg2) |
1443 | { |
1444 | return dest - arg1 * arg2; |
1445 | } |
1446 | |
1447 | static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t arg1, |
1448 | int64_t arg2) |
1449 | { |
1450 | int64_t even_arg1; |
1451 | int64_t even_arg2; |
1452 | int64_t odd_arg1; |
1453 | int64_t odd_arg2; |
1454 | SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df); |
1455 | SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df); |
1456 | return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2); |
1457 | } |
1458 | |
1459 | static inline int64_t msa_dpadd_u_df(uint32_t df, int64_t dest, int64_t arg1, |
1460 | int64_t arg2) |
1461 | { |
1462 | int64_t even_arg1; |
1463 | int64_t even_arg2; |
1464 | int64_t odd_arg1; |
1465 | int64_t odd_arg2; |
1466 | UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df); |
1467 | UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df); |
1468 | return dest + (even_arg1 * even_arg2) + (odd_arg1 * odd_arg2); |
1469 | } |
1470 | |
1471 | static inline int64_t msa_dpsub_s_df(uint32_t df, int64_t dest, int64_t arg1, |
1472 | int64_t arg2) |
1473 | { |
1474 | int64_t even_arg1; |
1475 | int64_t even_arg2; |
1476 | int64_t odd_arg1; |
1477 | int64_t odd_arg2; |
1478 | SIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df); |
1479 | SIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df); |
1480 | return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2)); |
1481 | } |
1482 | |
1483 | static inline int64_t msa_dpsub_u_df(uint32_t df, int64_t dest, int64_t arg1, |
1484 | int64_t arg2) |
1485 | { |
1486 | int64_t even_arg1; |
1487 | int64_t even_arg2; |
1488 | int64_t odd_arg1; |
1489 | int64_t odd_arg2; |
1490 | UNSIGNED_EXTRACT(even_arg1, odd_arg1, arg1, df); |
1491 | UNSIGNED_EXTRACT(even_arg2, odd_arg2, arg2, df); |
1492 | return dest - ((even_arg1 * even_arg2) + (odd_arg1 * odd_arg2)); |
1493 | } |
1494 | |
1495 | static inline int64_t msa_madd_q_df(uint32_t df, int64_t dest, int64_t arg1, |
1496 | int64_t arg2) |
1497 | { |
1498 | int64_t q_prod, q_ret; |
1499 | |
1500 | int64_t q_max = DF_MAX_INT(df); |
1501 | int64_t q_min = DF_MIN_INT(df); |
1502 | |
1503 | q_prod = arg1 * arg2; |
1504 | q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod) >> (DF_BITS(df) - 1); |
1505 | |
1506 | return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret; |
1507 | } |
1508 | |
1509 | static inline int64_t msa_msub_q_df(uint32_t df, int64_t dest, int64_t arg1, |
1510 | int64_t arg2) |
1511 | { |
1512 | int64_t q_prod, q_ret; |
1513 | |
1514 | int64_t q_max = DF_MAX_INT(df); |
1515 | int64_t q_min = DF_MIN_INT(df); |
1516 | |
1517 | q_prod = arg1 * arg2; |
1518 | q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod) >> (DF_BITS(df) - 1); |
1519 | |
1520 | return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret; |
1521 | } |
1522 | |
1523 | static inline int64_t msa_maddr_q_df(uint32_t df, int64_t dest, int64_t arg1, |
1524 | int64_t arg2) |
1525 | { |
1526 | int64_t q_prod, q_ret; |
1527 | |
1528 | int64_t q_max = DF_MAX_INT(df); |
1529 | int64_t q_min = DF_MIN_INT(df); |
1530 | int64_t r_bit = 1 << (DF_BITS(df) - 2); |
1531 | |
1532 | q_prod = arg1 * arg2; |
1533 | q_ret = ((dest << (DF_BITS(df) - 1)) + q_prod + r_bit) >> (DF_BITS(df) - 1); |
1534 | |
1535 | return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret; |
1536 | } |
1537 | |
1538 | static inline int64_t msa_msubr_q_df(uint32_t df, int64_t dest, int64_t arg1, |
1539 | int64_t arg2) |
1540 | { |
1541 | int64_t q_prod, q_ret; |
1542 | |
1543 | int64_t q_max = DF_MAX_INT(df); |
1544 | int64_t q_min = DF_MIN_INT(df); |
1545 | int64_t r_bit = 1 << (DF_BITS(df) - 2); |
1546 | |
1547 | q_prod = arg1 * arg2; |
1548 | q_ret = ((dest << (DF_BITS(df) - 1)) - q_prod + r_bit) >> (DF_BITS(df) - 1); |
1549 | |
1550 | return (q_ret < q_min) ? q_min : (q_max < q_ret) ? q_max : q_ret; |
1551 | } |
1552 | |
1553 | #define MSA_TEROP_DF(func) \ |
1554 | void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \ |
1555 | uint32_t ws, uint32_t wt) \ |
1556 | { \ |
1557 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
1558 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
1559 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \ |
1560 | \ |
1561 | switch (df) { \ |
1562 | case DF_BYTE: \ |
1563 | pwd->b[0] = msa_ ## func ## _df(df, pwd->b[0], pws->b[0], \ |
1564 | pwt->b[0]); \ |
1565 | pwd->b[1] = msa_ ## func ## _df(df, pwd->b[1], pws->b[1], \ |
1566 | pwt->b[1]); \ |
1567 | pwd->b[2] = msa_ ## func ## _df(df, pwd->b[2], pws->b[2], \ |
1568 | pwt->b[2]); \ |
1569 | pwd->b[3] = msa_ ## func ## _df(df, pwd->b[3], pws->b[3], \ |
1570 | pwt->b[3]); \ |
1571 | pwd->b[4] = msa_ ## func ## _df(df, pwd->b[4], pws->b[4], \ |
1572 | pwt->b[4]); \ |
1573 | pwd->b[5] = msa_ ## func ## _df(df, pwd->b[5], pws->b[5], \ |
1574 | pwt->b[5]); \ |
1575 | pwd->b[6] = msa_ ## func ## _df(df, pwd->b[6], pws->b[6], \ |
1576 | pwt->b[6]); \ |
1577 | pwd->b[7] = msa_ ## func ## _df(df, pwd->b[7], pws->b[7], \ |
1578 | pwt->b[7]); \ |
1579 | pwd->b[8] = msa_ ## func ## _df(df, pwd->b[8], pws->b[8], \ |
1580 | pwt->b[8]); \ |
1581 | pwd->b[9] = msa_ ## func ## _df(df, pwd->b[9], pws->b[9], \ |
1582 | pwt->b[9]); \ |
1583 | pwd->b[10] = msa_ ## func ## _df(df, pwd->b[10], pws->b[10], \ |
1584 | pwt->b[10]); \ |
1585 | pwd->b[11] = msa_ ## func ## _df(df, pwd->b[11], pws->b[11], \ |
1586 | pwt->b[11]); \ |
1587 | pwd->b[12] = msa_ ## func ## _df(df, pwd->b[12], pws->b[12], \ |
1588 | pwt->b[12]); \ |
1589 | pwd->b[13] = msa_ ## func ## _df(df, pwd->b[13], pws->b[13], \ |
1590 | pwt->b[13]); \ |
1591 | pwd->b[14] = msa_ ## func ## _df(df, pwd->b[14], pws->b[14], \ |
1592 | pwt->b[14]); \ |
1593 | pwd->b[15] = msa_ ## func ## _df(df, pwd->b[15], pws->b[15], \ |
1594 | pwt->b[15]); \ |
1595 | break; \ |
1596 | case DF_HALF: \ |
1597 | pwd->h[0] = msa_ ## func ## _df(df, pwd->h[0], pws->h[0], pwt->h[0]); \ |
1598 | pwd->h[1] = msa_ ## func ## _df(df, pwd->h[1], pws->h[1], pwt->h[1]); \ |
1599 | pwd->h[2] = msa_ ## func ## _df(df, pwd->h[2], pws->h[2], pwt->h[2]); \ |
1600 | pwd->h[3] = msa_ ## func ## _df(df, pwd->h[3], pws->h[3], pwt->h[3]); \ |
1601 | pwd->h[4] = msa_ ## func ## _df(df, pwd->h[4], pws->h[4], pwt->h[4]); \ |
1602 | pwd->h[5] = msa_ ## func ## _df(df, pwd->h[5], pws->h[5], pwt->h[5]); \ |
1603 | pwd->h[6] = msa_ ## func ## _df(df, pwd->h[6], pws->h[6], pwt->h[6]); \ |
1604 | pwd->h[7] = msa_ ## func ## _df(df, pwd->h[7], pws->h[7], pwt->h[7]); \ |
1605 | break; \ |
1606 | case DF_WORD: \ |
1607 | pwd->w[0] = msa_ ## func ## _df(df, pwd->w[0], pws->w[0], pwt->w[0]); \ |
1608 | pwd->w[1] = msa_ ## func ## _df(df, pwd->w[1], pws->w[1], pwt->w[1]); \ |
1609 | pwd->w[2] = msa_ ## func ## _df(df, pwd->w[2], pws->w[2], pwt->w[2]); \ |
1610 | pwd->w[3] = msa_ ## func ## _df(df, pwd->w[3], pws->w[3], pwt->w[3]); \ |
1611 | break; \ |
1612 | case DF_DOUBLE: \ |
1613 | pwd->d[0] = msa_ ## func ## _df(df, pwd->d[0], pws->d[0], pwt->d[0]); \ |
1614 | pwd->d[1] = msa_ ## func ## _df(df, pwd->d[1], pws->d[1], pwt->d[1]); \ |
1615 | break; \ |
1616 | default: \ |
1617 | assert(0); \ |
1618 | } \ |
1619 | } |
1620 | |
1621 | MSA_TEROP_DF(maddv) |
1622 | MSA_TEROP_DF(msubv) |
1623 | MSA_TEROP_DF(dpadd_s) |
1624 | MSA_TEROP_DF(dpadd_u) |
1625 | MSA_TEROP_DF(dpsub_s) |
1626 | MSA_TEROP_DF(dpsub_u) |
1627 | MSA_TEROP_DF(binsl) |
1628 | MSA_TEROP_DF(binsr) |
1629 | MSA_TEROP_DF(madd_q) |
1630 | MSA_TEROP_DF(msub_q) |
1631 | MSA_TEROP_DF(maddr_q) |
1632 | MSA_TEROP_DF(msubr_q) |
1633 | #undef MSA_TEROP_DF |
1634 | |
1635 | static inline void msa_splat_df(uint32_t df, wr_t *pwd, |
1636 | wr_t *pws, target_ulong rt) |
1637 | { |
1638 | uint32_t n = rt % DF_ELEMENTS(df); |
1639 | uint32_t i; |
1640 | |
1641 | switch (df) { |
1642 | case DF_BYTE: |
1643 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { |
1644 | pwd->b[i] = pws->b[n]; |
1645 | } |
1646 | break; |
1647 | case DF_HALF: |
1648 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { |
1649 | pwd->h[i] = pws->h[n]; |
1650 | } |
1651 | break; |
1652 | case DF_WORD: |
1653 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
1654 | pwd->w[i] = pws->w[n]; |
1655 | } |
1656 | break; |
1657 | case DF_DOUBLE: |
1658 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
1659 | pwd->d[i] = pws->d[n]; |
1660 | } |
1661 | break; |
1662 | default: |
1663 | assert(0); |
1664 | } |
1665 | } |
1666 | |
1667 | void helper_msa_splat_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
1668 | uint32_t ws, uint32_t rt) |
1669 | { |
1670 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
1671 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
1672 | |
1673 | msa_splat_df(df, pwd, pws, env->active_tc.gpr[rt]); |
1674 | } |
1675 | |
1676 | #define MSA_DO_B MSA_DO(b) |
1677 | #define MSA_DO_H MSA_DO(h) |
1678 | #define MSA_DO_W MSA_DO(w) |
1679 | #define MSA_DO_D MSA_DO(d) |
1680 | |
1681 | #define MSA_LOOP_B MSA_LOOP(B) |
1682 | #define MSA_LOOP_H MSA_LOOP(H) |
1683 | #define MSA_LOOP_W MSA_LOOP(W) |
1684 | #define MSA_LOOP_D MSA_LOOP(D) |
1685 | |
1686 | #define MSA_LOOP_COND_B MSA_LOOP_COND(DF_BYTE) |
1687 | #define MSA_LOOP_COND_H MSA_LOOP_COND(DF_HALF) |
1688 | #define MSA_LOOP_COND_W MSA_LOOP_COND(DF_WORD) |
1689 | #define MSA_LOOP_COND_D MSA_LOOP_COND(DF_DOUBLE) |
1690 | |
1691 | #define MSA_LOOP(DF) \ |
1692 | do { \ |
1693 | for (i = 0; i < (MSA_LOOP_COND_ ## DF) ; i++) { \ |
1694 | MSA_DO_ ## DF; \ |
1695 | } \ |
1696 | } while (0) |
1697 | |
1698 | #define MSA_FN_DF(FUNC) \ |
1699 | void helper_msa_##FUNC(CPUMIPSState *env, uint32_t df, uint32_t wd, \ |
1700 | uint32_t ws, uint32_t wt) \ |
1701 | { \ |
1702 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
1703 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
1704 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); \ |
1705 | wr_t wx, *pwx = &wx; \ |
1706 | uint32_t i; \ |
1707 | switch (df) { \ |
1708 | case DF_BYTE: \ |
1709 | MSA_LOOP_B; \ |
1710 | break; \ |
1711 | case DF_HALF: \ |
1712 | MSA_LOOP_H; \ |
1713 | break; \ |
1714 | case DF_WORD: \ |
1715 | MSA_LOOP_W; \ |
1716 | break; \ |
1717 | case DF_DOUBLE: \ |
1718 | MSA_LOOP_D; \ |
1719 | break; \ |
1720 | default: \ |
1721 | assert(0); \ |
1722 | } \ |
1723 | msa_move_v(pwd, pwx); \ |
1724 | } |
1725 | |
1726 | #define MSA_LOOP_COND(DF) \ |
1727 | (DF_ELEMENTS(DF) / 2) |
1728 | |
1729 | #define Rb(pwr, i) (pwr->b[i]) |
1730 | #define Lb(pwr, i) (pwr->b[i + DF_ELEMENTS(DF_BYTE) / 2]) |
1731 | #define Rh(pwr, i) (pwr->h[i]) |
1732 | #define Lh(pwr, i) (pwr->h[i + DF_ELEMENTS(DF_HALF) / 2]) |
1733 | #define Rw(pwr, i) (pwr->w[i]) |
1734 | #define Lw(pwr, i) (pwr->w[i + DF_ELEMENTS(DF_WORD) / 2]) |
1735 | #define Rd(pwr, i) (pwr->d[i]) |
1736 | #define Ld(pwr, i) (pwr->d[i + DF_ELEMENTS(DF_DOUBLE) / 2]) |
1737 | |
1738 | #undef MSA_LOOP_COND |
1739 | |
1740 | #define MSA_LOOP_COND(DF) \ |
1741 | (DF_ELEMENTS(DF)) |
1742 | |
1743 | #define MSA_DO(DF) \ |
1744 | do { \ |
1745 | uint32_t n = DF_ELEMENTS(df); \ |
1746 | uint32_t k = (pwd->DF[i] & 0x3f) % (2 * n); \ |
1747 | pwx->DF[i] = \ |
1748 | (pwd->DF[i] & 0xc0) ? 0 : k < n ? pwt->DF[k] : pws->DF[k - n]; \ |
1749 | } while (0) |
1750 | MSA_FN_DF(vshf_df) |
1751 | #undef MSA_DO |
1752 | #undef MSA_LOOP_COND |
1753 | #undef MSA_FN_DF |
1754 | |
1755 | |
1756 | void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
1757 | uint32_t ws, uint32_t wt) |
1758 | { |
1759 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
1760 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
1761 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
1762 | |
1763 | switch (df) { |
1764 | case DF_BYTE: |
1765 | #if defined(HOST_WORDS_BIGENDIAN) |
1766 | pwd->b[8] = pws->b[9]; |
1767 | pwd->b[9] = pwt->b[9]; |
1768 | pwd->b[10] = pws->b[11]; |
1769 | pwd->b[11] = pwt->b[11]; |
1770 | pwd->b[12] = pws->b[13]; |
1771 | pwd->b[13] = pwt->b[13]; |
1772 | pwd->b[14] = pws->b[15]; |
1773 | pwd->b[15] = pwt->b[15]; |
1774 | pwd->b[0] = pws->b[1]; |
1775 | pwd->b[1] = pwt->b[1]; |
1776 | pwd->b[2] = pws->b[3]; |
1777 | pwd->b[3] = pwt->b[3]; |
1778 | pwd->b[4] = pws->b[5]; |
1779 | pwd->b[5] = pwt->b[5]; |
1780 | pwd->b[6] = pws->b[7]; |
1781 | pwd->b[7] = pwt->b[7]; |
1782 | #else |
1783 | pwd->b[15] = pws->b[14]; |
1784 | pwd->b[14] = pwt->b[14]; |
1785 | pwd->b[13] = pws->b[12]; |
1786 | pwd->b[12] = pwt->b[12]; |
1787 | pwd->b[11] = pws->b[10]; |
1788 | pwd->b[10] = pwt->b[10]; |
1789 | pwd->b[9] = pws->b[8]; |
1790 | pwd->b[8] = pwt->b[8]; |
1791 | pwd->b[7] = pws->b[6]; |
1792 | pwd->b[6] = pwt->b[6]; |
1793 | pwd->b[5] = pws->b[4]; |
1794 | pwd->b[4] = pwt->b[4]; |
1795 | pwd->b[3] = pws->b[2]; |
1796 | pwd->b[2] = pwt->b[2]; |
1797 | pwd->b[1] = pws->b[0]; |
1798 | pwd->b[0] = pwt->b[0]; |
1799 | #endif |
1800 | break; |
1801 | case DF_HALF: |
1802 | #if defined(HOST_WORDS_BIGENDIAN) |
1803 | pwd->h[4] = pws->h[5]; |
1804 | pwd->h[5] = pwt->h[5]; |
1805 | pwd->h[6] = pws->h[7]; |
1806 | pwd->h[7] = pwt->h[7]; |
1807 | pwd->h[0] = pws->h[1]; |
1808 | pwd->h[1] = pwt->h[1]; |
1809 | pwd->h[2] = pws->h[3]; |
1810 | pwd->h[3] = pwt->h[3]; |
1811 | #else |
1812 | pwd->h[7] = pws->h[6]; |
1813 | pwd->h[6] = pwt->h[6]; |
1814 | pwd->h[5] = pws->h[4]; |
1815 | pwd->h[4] = pwt->h[4]; |
1816 | pwd->h[3] = pws->h[2]; |
1817 | pwd->h[2] = pwt->h[2]; |
1818 | pwd->h[1] = pws->h[0]; |
1819 | pwd->h[0] = pwt->h[0]; |
1820 | #endif |
1821 | break; |
1822 | case DF_WORD: |
1823 | #if defined(HOST_WORDS_BIGENDIAN) |
1824 | pwd->w[2] = pws->w[3]; |
1825 | pwd->w[3] = pwt->w[3]; |
1826 | pwd->w[0] = pws->w[1]; |
1827 | pwd->w[1] = pwt->w[1]; |
1828 | #else |
1829 | pwd->w[3] = pws->w[2]; |
1830 | pwd->w[2] = pwt->w[2]; |
1831 | pwd->w[1] = pws->w[0]; |
1832 | pwd->w[0] = pwt->w[0]; |
1833 | #endif |
1834 | break; |
1835 | case DF_DOUBLE: |
1836 | pwd->d[1] = pws->d[0]; |
1837 | pwd->d[0] = pwt->d[0]; |
1838 | break; |
1839 | default: |
1840 | assert(0); |
1841 | } |
1842 | } |
1843 | |
1844 | void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
1845 | uint32_t ws, uint32_t wt) |
1846 | { |
1847 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
1848 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
1849 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
1850 | |
1851 | switch (df) { |
1852 | case DF_BYTE: |
1853 | #if defined(HOST_WORDS_BIGENDIAN) |
1854 | pwd->b[7] = pwt->b[6]; |
1855 | pwd->b[6] = pws->b[6]; |
1856 | pwd->b[5] = pwt->b[4]; |
1857 | pwd->b[4] = pws->b[4]; |
1858 | pwd->b[3] = pwt->b[2]; |
1859 | pwd->b[2] = pws->b[2]; |
1860 | pwd->b[1] = pwt->b[0]; |
1861 | pwd->b[0] = pws->b[0]; |
1862 | pwd->b[15] = pwt->b[14]; |
1863 | pwd->b[14] = pws->b[14]; |
1864 | pwd->b[13] = pwt->b[12]; |
1865 | pwd->b[12] = pws->b[12]; |
1866 | pwd->b[11] = pwt->b[10]; |
1867 | pwd->b[10] = pws->b[10]; |
1868 | pwd->b[9] = pwt->b[8]; |
1869 | pwd->b[8] = pws->b[8]; |
1870 | #else |
1871 | pwd->b[0] = pwt->b[1]; |
1872 | pwd->b[1] = pws->b[1]; |
1873 | pwd->b[2] = pwt->b[3]; |
1874 | pwd->b[3] = pws->b[3]; |
1875 | pwd->b[4] = pwt->b[5]; |
1876 | pwd->b[5] = pws->b[5]; |
1877 | pwd->b[6] = pwt->b[7]; |
1878 | pwd->b[7] = pws->b[7]; |
1879 | pwd->b[8] = pwt->b[9]; |
1880 | pwd->b[9] = pws->b[9]; |
1881 | pwd->b[10] = pwt->b[11]; |
1882 | pwd->b[11] = pws->b[11]; |
1883 | pwd->b[12] = pwt->b[13]; |
1884 | pwd->b[13] = pws->b[13]; |
1885 | pwd->b[14] = pwt->b[15]; |
1886 | pwd->b[15] = pws->b[15]; |
1887 | #endif |
1888 | break; |
1889 | case DF_HALF: |
1890 | #if defined(HOST_WORDS_BIGENDIAN) |
1891 | pwd->h[3] = pwt->h[2]; |
1892 | pwd->h[2] = pws->h[2]; |
1893 | pwd->h[1] = pwt->h[0]; |
1894 | pwd->h[0] = pws->h[0]; |
1895 | pwd->h[7] = pwt->h[6]; |
1896 | pwd->h[6] = pws->h[6]; |
1897 | pwd->h[5] = pwt->h[4]; |
1898 | pwd->h[4] = pws->h[4]; |
1899 | #else |
1900 | pwd->h[0] = pwt->h[1]; |
1901 | pwd->h[1] = pws->h[1]; |
1902 | pwd->h[2] = pwt->h[3]; |
1903 | pwd->h[3] = pws->h[3]; |
1904 | pwd->h[4] = pwt->h[5]; |
1905 | pwd->h[5] = pws->h[5]; |
1906 | pwd->h[6] = pwt->h[7]; |
1907 | pwd->h[7] = pws->h[7]; |
1908 | #endif |
1909 | break; |
1910 | case DF_WORD: |
1911 | #if defined(HOST_WORDS_BIGENDIAN) |
1912 | pwd->w[1] = pwt->w[0]; |
1913 | pwd->w[0] = pws->w[0]; |
1914 | pwd->w[3] = pwt->w[2]; |
1915 | pwd->w[2] = pws->w[2]; |
1916 | #else |
1917 | pwd->w[0] = pwt->w[1]; |
1918 | pwd->w[1] = pws->w[1]; |
1919 | pwd->w[2] = pwt->w[3]; |
1920 | pwd->w[3] = pws->w[3]; |
1921 | #endif |
1922 | break; |
1923 | case DF_DOUBLE: |
1924 | pwd->d[0] = pwt->d[1]; |
1925 | pwd->d[1] = pws->d[1]; |
1926 | break; |
1927 | default: |
1928 | assert(0); |
1929 | } |
1930 | } |
1931 | |
1932 | void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
1933 | uint32_t ws, uint32_t wt) |
1934 | { |
1935 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
1936 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
1937 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
1938 | |
1939 | switch (df) { |
1940 | case DF_BYTE: |
1941 | #if defined(HOST_WORDS_BIGENDIAN) |
1942 | pwd->b[7] = pwt->b[15]; |
1943 | pwd->b[6] = pws->b[15]; |
1944 | pwd->b[5] = pwt->b[14]; |
1945 | pwd->b[4] = pws->b[14]; |
1946 | pwd->b[3] = pwt->b[13]; |
1947 | pwd->b[2] = pws->b[13]; |
1948 | pwd->b[1] = pwt->b[12]; |
1949 | pwd->b[0] = pws->b[12]; |
1950 | pwd->b[15] = pwt->b[11]; |
1951 | pwd->b[14] = pws->b[11]; |
1952 | pwd->b[13] = pwt->b[10]; |
1953 | pwd->b[12] = pws->b[10]; |
1954 | pwd->b[11] = pwt->b[9]; |
1955 | pwd->b[10] = pws->b[9]; |
1956 | pwd->b[9] = pwt->b[8]; |
1957 | pwd->b[8] = pws->b[8]; |
1958 | #else |
1959 | pwd->b[0] = pwt->b[8]; |
1960 | pwd->b[1] = pws->b[8]; |
1961 | pwd->b[2] = pwt->b[9]; |
1962 | pwd->b[3] = pws->b[9]; |
1963 | pwd->b[4] = pwt->b[10]; |
1964 | pwd->b[5] = pws->b[10]; |
1965 | pwd->b[6] = pwt->b[11]; |
1966 | pwd->b[7] = pws->b[11]; |
1967 | pwd->b[8] = pwt->b[12]; |
1968 | pwd->b[9] = pws->b[12]; |
1969 | pwd->b[10] = pwt->b[13]; |
1970 | pwd->b[11] = pws->b[13]; |
1971 | pwd->b[12] = pwt->b[14]; |
1972 | pwd->b[13] = pws->b[14]; |
1973 | pwd->b[14] = pwt->b[15]; |
1974 | pwd->b[15] = pws->b[15]; |
1975 | #endif |
1976 | break; |
1977 | case DF_HALF: |
1978 | #if defined(HOST_WORDS_BIGENDIAN) |
1979 | pwd->h[3] = pwt->h[7]; |
1980 | pwd->h[2] = pws->h[7]; |
1981 | pwd->h[1] = pwt->h[6]; |
1982 | pwd->h[0] = pws->h[6]; |
1983 | pwd->h[7] = pwt->h[5]; |
1984 | pwd->h[6] = pws->h[5]; |
1985 | pwd->h[5] = pwt->h[4]; |
1986 | pwd->h[4] = pws->h[4]; |
1987 | #else |
1988 | pwd->h[0] = pwt->h[4]; |
1989 | pwd->h[1] = pws->h[4]; |
1990 | pwd->h[2] = pwt->h[5]; |
1991 | pwd->h[3] = pws->h[5]; |
1992 | pwd->h[4] = pwt->h[6]; |
1993 | pwd->h[5] = pws->h[6]; |
1994 | pwd->h[6] = pwt->h[7]; |
1995 | pwd->h[7] = pws->h[7]; |
1996 | #endif |
1997 | break; |
1998 | case DF_WORD: |
1999 | #if defined(HOST_WORDS_BIGENDIAN) |
2000 | pwd->w[1] = pwt->w[3]; |
2001 | pwd->w[0] = pws->w[3]; |
2002 | pwd->w[3] = pwt->w[2]; |
2003 | pwd->w[2] = pws->w[2]; |
2004 | #else |
2005 | pwd->w[0] = pwt->w[2]; |
2006 | pwd->w[1] = pws->w[2]; |
2007 | pwd->w[2] = pwt->w[3]; |
2008 | pwd->w[3] = pws->w[3]; |
2009 | #endif |
2010 | break; |
2011 | case DF_DOUBLE: |
2012 | pwd->d[0] = pwt->d[1]; |
2013 | pwd->d[1] = pws->d[1]; |
2014 | break; |
2015 | default: |
2016 | assert(0); |
2017 | } |
2018 | } |
2019 | |
2020 | void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2021 | uint32_t ws, uint32_t wt) |
2022 | { |
2023 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2024 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2025 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
2026 | |
2027 | switch (df) { |
2028 | case DF_BYTE: |
2029 | #if defined(HOST_WORDS_BIGENDIAN) |
2030 | pwd->b[8] = pws->b[0]; |
2031 | pwd->b[9] = pwt->b[0]; |
2032 | pwd->b[10] = pws->b[1]; |
2033 | pwd->b[11] = pwt->b[1]; |
2034 | pwd->b[12] = pws->b[2]; |
2035 | pwd->b[13] = pwt->b[2]; |
2036 | pwd->b[14] = pws->b[3]; |
2037 | pwd->b[15] = pwt->b[3]; |
2038 | pwd->b[0] = pws->b[4]; |
2039 | pwd->b[1] = pwt->b[4]; |
2040 | pwd->b[2] = pws->b[5]; |
2041 | pwd->b[3] = pwt->b[5]; |
2042 | pwd->b[4] = pws->b[6]; |
2043 | pwd->b[5] = pwt->b[6]; |
2044 | pwd->b[6] = pws->b[7]; |
2045 | pwd->b[7] = pwt->b[7]; |
2046 | #else |
2047 | pwd->b[15] = pws->b[7]; |
2048 | pwd->b[14] = pwt->b[7]; |
2049 | pwd->b[13] = pws->b[6]; |
2050 | pwd->b[12] = pwt->b[6]; |
2051 | pwd->b[11] = pws->b[5]; |
2052 | pwd->b[10] = pwt->b[5]; |
2053 | pwd->b[9] = pws->b[4]; |
2054 | pwd->b[8] = pwt->b[4]; |
2055 | pwd->b[7] = pws->b[3]; |
2056 | pwd->b[6] = pwt->b[3]; |
2057 | pwd->b[5] = pws->b[2]; |
2058 | pwd->b[4] = pwt->b[2]; |
2059 | pwd->b[3] = pws->b[1]; |
2060 | pwd->b[2] = pwt->b[1]; |
2061 | pwd->b[1] = pws->b[0]; |
2062 | pwd->b[0] = pwt->b[0]; |
2063 | #endif |
2064 | break; |
2065 | case DF_HALF: |
2066 | #if defined(HOST_WORDS_BIGENDIAN) |
2067 | pwd->h[4] = pws->h[0]; |
2068 | pwd->h[5] = pwt->h[0]; |
2069 | pwd->h[6] = pws->h[1]; |
2070 | pwd->h[7] = pwt->h[1]; |
2071 | pwd->h[0] = pws->h[2]; |
2072 | pwd->h[1] = pwt->h[2]; |
2073 | pwd->h[2] = pws->h[3]; |
2074 | pwd->h[3] = pwt->h[3]; |
2075 | #else |
2076 | pwd->h[7] = pws->h[3]; |
2077 | pwd->h[6] = pwt->h[3]; |
2078 | pwd->h[5] = pws->h[2]; |
2079 | pwd->h[4] = pwt->h[2]; |
2080 | pwd->h[3] = pws->h[1]; |
2081 | pwd->h[2] = pwt->h[1]; |
2082 | pwd->h[1] = pws->h[0]; |
2083 | pwd->h[0] = pwt->h[0]; |
2084 | #endif |
2085 | break; |
2086 | case DF_WORD: |
2087 | #if defined(HOST_WORDS_BIGENDIAN) |
2088 | pwd->w[2] = pws->w[0]; |
2089 | pwd->w[3] = pwt->w[0]; |
2090 | pwd->w[0] = pws->w[1]; |
2091 | pwd->w[1] = pwt->w[1]; |
2092 | #else |
2093 | pwd->w[3] = pws->w[1]; |
2094 | pwd->w[2] = pwt->w[1]; |
2095 | pwd->w[1] = pws->w[0]; |
2096 | pwd->w[0] = pwt->w[0]; |
2097 | #endif |
2098 | break; |
2099 | case DF_DOUBLE: |
2100 | pwd->d[1] = pws->d[0]; |
2101 | pwd->d[0] = pwt->d[0]; |
2102 | break; |
2103 | default: |
2104 | assert(0); |
2105 | } |
2106 | } |
2107 | |
2108 | void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2109 | uint32_t ws, uint32_t wt) |
2110 | { |
2111 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2112 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2113 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
2114 | |
2115 | switch (df) { |
2116 | case DF_BYTE: |
2117 | #if defined(HOST_WORDS_BIGENDIAN) |
2118 | pwd->b[8] = pws->b[9]; |
2119 | pwd->b[10] = pws->b[13]; |
2120 | pwd->b[12] = pws->b[1]; |
2121 | pwd->b[14] = pws->b[5]; |
2122 | pwd->b[0] = pwt->b[9]; |
2123 | pwd->b[2] = pwt->b[13]; |
2124 | pwd->b[4] = pwt->b[1]; |
2125 | pwd->b[6] = pwt->b[5]; |
2126 | pwd->b[9] = pws->b[11]; |
2127 | pwd->b[13] = pws->b[3]; |
2128 | pwd->b[1] = pwt->b[11]; |
2129 | pwd->b[5] = pwt->b[3]; |
2130 | pwd->b[11] = pws->b[15]; |
2131 | pwd->b[3] = pwt->b[15]; |
2132 | pwd->b[15] = pws->b[7]; |
2133 | pwd->b[7] = pwt->b[7]; |
2134 | #else |
2135 | pwd->b[15] = pws->b[14]; |
2136 | pwd->b[13] = pws->b[10]; |
2137 | pwd->b[11] = pws->b[6]; |
2138 | pwd->b[9] = pws->b[2]; |
2139 | pwd->b[7] = pwt->b[14]; |
2140 | pwd->b[5] = pwt->b[10]; |
2141 | pwd->b[3] = pwt->b[6]; |
2142 | pwd->b[1] = pwt->b[2]; |
2143 | pwd->b[14] = pws->b[12]; |
2144 | pwd->b[10] = pws->b[4]; |
2145 | pwd->b[6] = pwt->b[12]; |
2146 | pwd->b[2] = pwt->b[4]; |
2147 | pwd->b[12] = pws->b[8]; |
2148 | pwd->b[4] = pwt->b[8]; |
2149 | pwd->b[8] = pws->b[0]; |
2150 | pwd->b[0] = pwt->b[0]; |
2151 | #endif |
2152 | break; |
2153 | case DF_HALF: |
2154 | #if defined(HOST_WORDS_BIGENDIAN) |
2155 | pwd->h[4] = pws->h[5]; |
2156 | pwd->h[6] = pws->h[1]; |
2157 | pwd->h[0] = pwt->h[5]; |
2158 | pwd->h[2] = pwt->h[1]; |
2159 | pwd->h[5] = pws->h[7]; |
2160 | pwd->h[1] = pwt->h[7]; |
2161 | pwd->h[7] = pws->h[3]; |
2162 | pwd->h[3] = pwt->h[3]; |
2163 | #else |
2164 | pwd->h[7] = pws->h[6]; |
2165 | pwd->h[5] = pws->h[2]; |
2166 | pwd->h[3] = pwt->h[6]; |
2167 | pwd->h[1] = pwt->h[2]; |
2168 | pwd->h[6] = pws->h[4]; |
2169 | pwd->h[2] = pwt->h[4]; |
2170 | pwd->h[4] = pws->h[0]; |
2171 | pwd->h[0] = pwt->h[0]; |
2172 | #endif |
2173 | break; |
2174 | case DF_WORD: |
2175 | #if defined(HOST_WORDS_BIGENDIAN) |
2176 | pwd->w[2] = pws->w[3]; |
2177 | pwd->w[0] = pwt->w[3]; |
2178 | pwd->w[3] = pws->w[1]; |
2179 | pwd->w[1] = pwt->w[1]; |
2180 | #else |
2181 | pwd->w[3] = pws->w[2]; |
2182 | pwd->w[1] = pwt->w[2]; |
2183 | pwd->w[2] = pws->w[0]; |
2184 | pwd->w[0] = pwt->w[0]; |
2185 | #endif |
2186 | break; |
2187 | case DF_DOUBLE: |
2188 | pwd->d[1] = pws->d[0]; |
2189 | pwd->d[0] = pwt->d[0]; |
2190 | break; |
2191 | default: |
2192 | assert(0); |
2193 | } |
2194 | } |
2195 | |
2196 | void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2197 | uint32_t ws, uint32_t wt) |
2198 | { |
2199 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2200 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2201 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
2202 | |
2203 | switch (df) { |
2204 | case DF_BYTE: |
2205 | #if defined(HOST_WORDS_BIGENDIAN) |
2206 | pwd->b[7] = pwt->b[6]; |
2207 | pwd->b[5] = pwt->b[2]; |
2208 | pwd->b[3] = pwt->b[14]; |
2209 | pwd->b[1] = pwt->b[10]; |
2210 | pwd->b[15] = pws->b[6]; |
2211 | pwd->b[13] = pws->b[2]; |
2212 | pwd->b[11] = pws->b[14]; |
2213 | pwd->b[9] = pws->b[10]; |
2214 | pwd->b[6] = pwt->b[4]; |
2215 | pwd->b[2] = pwt->b[12]; |
2216 | pwd->b[14] = pws->b[4]; |
2217 | pwd->b[10] = pws->b[12]; |
2218 | pwd->b[4] = pwt->b[0]; |
2219 | pwd->b[12] = pws->b[0]; |
2220 | pwd->b[0] = pwt->b[8]; |
2221 | pwd->b[8] = pws->b[8]; |
2222 | #else |
2223 | pwd->b[0] = pwt->b[1]; |
2224 | pwd->b[2] = pwt->b[5]; |
2225 | pwd->b[4] = pwt->b[9]; |
2226 | pwd->b[6] = pwt->b[13]; |
2227 | pwd->b[8] = pws->b[1]; |
2228 | pwd->b[10] = pws->b[5]; |
2229 | pwd->b[12] = pws->b[9]; |
2230 | pwd->b[14] = pws->b[13]; |
2231 | pwd->b[1] = pwt->b[3]; |
2232 | pwd->b[5] = pwt->b[11]; |
2233 | pwd->b[9] = pws->b[3]; |
2234 | pwd->b[13] = pws->b[11]; |
2235 | pwd->b[3] = pwt->b[7]; |
2236 | pwd->b[11] = pws->b[7]; |
2237 | pwd->b[7] = pwt->b[15]; |
2238 | pwd->b[15] = pws->b[15]; |
2239 | #endif |
2240 | break; |
2241 | case DF_HALF: |
2242 | #if defined(HOST_WORDS_BIGENDIAN) |
2243 | pwd->h[3] = pwt->h[2]; |
2244 | pwd->h[1] = pwt->h[6]; |
2245 | pwd->h[7] = pws->h[2]; |
2246 | pwd->h[5] = pws->h[6]; |
2247 | pwd->h[2] = pwt->h[0]; |
2248 | pwd->h[6] = pws->h[0]; |
2249 | pwd->h[0] = pwt->h[4]; |
2250 | pwd->h[4] = pws->h[4]; |
2251 | #else |
2252 | pwd->h[0] = pwt->h[1]; |
2253 | pwd->h[2] = pwt->h[5]; |
2254 | pwd->h[4] = pws->h[1]; |
2255 | pwd->h[6] = pws->h[5]; |
2256 | pwd->h[1] = pwt->h[3]; |
2257 | pwd->h[5] = pws->h[3]; |
2258 | pwd->h[3] = pwt->h[7]; |
2259 | pwd->h[7] = pws->h[7]; |
2260 | #endif |
2261 | break; |
2262 | case DF_WORD: |
2263 | #if defined(HOST_WORDS_BIGENDIAN) |
2264 | pwd->w[1] = pwt->w[0]; |
2265 | pwd->w[3] = pws->w[0]; |
2266 | pwd->w[0] = pwt->w[2]; |
2267 | pwd->w[2] = pws->w[2]; |
2268 | #else |
2269 | pwd->w[0] = pwt->w[1]; |
2270 | pwd->w[2] = pws->w[1]; |
2271 | pwd->w[1] = pwt->w[3]; |
2272 | pwd->w[3] = pws->w[3]; |
2273 | #endif |
2274 | break; |
2275 | case DF_DOUBLE: |
2276 | pwd->d[0] = pwt->d[1]; |
2277 | pwd->d[1] = pws->d[1]; |
2278 | break; |
2279 | default: |
2280 | assert(0); |
2281 | } |
2282 | } |
2283 | |
2284 | |
2285 | void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2286 | uint32_t ws, uint32_t n) |
2287 | { |
2288 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2289 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2290 | |
2291 | msa_sld_df(df, pwd, pws, n); |
2292 | } |
2293 | |
2294 | void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2295 | uint32_t ws, uint32_t n) |
2296 | { |
2297 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2298 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2299 | |
2300 | msa_splat_df(df, pwd, pws, n); |
2301 | } |
2302 | |
2303 | void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd, |
2304 | uint32_t ws, uint32_t n) |
2305 | { |
2306 | n %= 16; |
2307 | #if defined(HOST_WORDS_BIGENDIAN) |
2308 | if (n < 8) { |
2309 | n = 8 - n - 1; |
2310 | } else { |
2311 | n = 24 - n - 1; |
2312 | } |
2313 | #endif |
2314 | env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n]; |
2315 | } |
2316 | |
2317 | void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd, |
2318 | uint32_t ws, uint32_t n) |
2319 | { |
2320 | n %= 8; |
2321 | #if defined(HOST_WORDS_BIGENDIAN) |
2322 | if (n < 4) { |
2323 | n = 4 - n - 1; |
2324 | } else { |
2325 | n = 12 - n - 1; |
2326 | } |
2327 | #endif |
2328 | env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n]; |
2329 | } |
2330 | |
2331 | void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd, |
2332 | uint32_t ws, uint32_t n) |
2333 | { |
2334 | n %= 4; |
2335 | #if defined(HOST_WORDS_BIGENDIAN) |
2336 | if (n < 2) { |
2337 | n = 2 - n - 1; |
2338 | } else { |
2339 | n = 6 - n - 1; |
2340 | } |
2341 | #endif |
2342 | env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n]; |
2343 | } |
2344 | |
2345 | void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd, |
2346 | uint32_t ws, uint32_t n) |
2347 | { |
2348 | n %= 2; |
2349 | env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n]; |
2350 | } |
2351 | |
2352 | void helper_msa_copy_u_b(CPUMIPSState *env, uint32_t rd, |
2353 | uint32_t ws, uint32_t n) |
2354 | { |
2355 | n %= 16; |
2356 | #if defined(HOST_WORDS_BIGENDIAN) |
2357 | if (n < 8) { |
2358 | n = 8 - n - 1; |
2359 | } else { |
2360 | n = 24 - n - 1; |
2361 | } |
2362 | #endif |
2363 | env->active_tc.gpr[rd] = (uint8_t)env->active_fpu.fpr[ws].wr.b[n]; |
2364 | } |
2365 | |
2366 | void helper_msa_copy_u_h(CPUMIPSState *env, uint32_t rd, |
2367 | uint32_t ws, uint32_t n) |
2368 | { |
2369 | n %= 8; |
2370 | #if defined(HOST_WORDS_BIGENDIAN) |
2371 | if (n < 4) { |
2372 | n = 4 - n - 1; |
2373 | } else { |
2374 | n = 12 - n - 1; |
2375 | } |
2376 | #endif |
2377 | env->active_tc.gpr[rd] = (uint16_t)env->active_fpu.fpr[ws].wr.h[n]; |
2378 | } |
2379 | |
2380 | void helper_msa_copy_u_w(CPUMIPSState *env, uint32_t rd, |
2381 | uint32_t ws, uint32_t n) |
2382 | { |
2383 | n %= 4; |
2384 | #if defined(HOST_WORDS_BIGENDIAN) |
2385 | if (n < 2) { |
2386 | n = 2 - n - 1; |
2387 | } else { |
2388 | n = 6 - n - 1; |
2389 | } |
2390 | #endif |
2391 | env->active_tc.gpr[rd] = (uint32_t)env->active_fpu.fpr[ws].wr.w[n]; |
2392 | } |
2393 | |
2394 | void helper_msa_insert_b(CPUMIPSState *env, uint32_t wd, |
2395 | uint32_t rs_num, uint32_t n) |
2396 | { |
2397 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2398 | target_ulong rs = env->active_tc.gpr[rs_num]; |
2399 | n %= 16; |
2400 | #if defined(HOST_WORDS_BIGENDIAN) |
2401 | if (n < 8) { |
2402 | n = 8 - n - 1; |
2403 | } else { |
2404 | n = 24 - n - 1; |
2405 | } |
2406 | #endif |
2407 | pwd->b[n] = (int8_t)rs; |
2408 | } |
2409 | |
2410 | void helper_msa_insert_h(CPUMIPSState *env, uint32_t wd, |
2411 | uint32_t rs_num, uint32_t n) |
2412 | { |
2413 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2414 | target_ulong rs = env->active_tc.gpr[rs_num]; |
2415 | n %= 8; |
2416 | #if defined(HOST_WORDS_BIGENDIAN) |
2417 | if (n < 4) { |
2418 | n = 4 - n - 1; |
2419 | } else { |
2420 | n = 12 - n - 1; |
2421 | } |
2422 | #endif |
2423 | pwd->h[n] = (int16_t)rs; |
2424 | } |
2425 | |
2426 | void helper_msa_insert_w(CPUMIPSState *env, uint32_t wd, |
2427 | uint32_t rs_num, uint32_t n) |
2428 | { |
2429 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2430 | target_ulong rs = env->active_tc.gpr[rs_num]; |
2431 | n %= 4; |
2432 | #if defined(HOST_WORDS_BIGENDIAN) |
2433 | if (n < 2) { |
2434 | n = 2 - n - 1; |
2435 | } else { |
2436 | n = 6 - n - 1; |
2437 | } |
2438 | #endif |
2439 | pwd->w[n] = (int32_t)rs; |
2440 | } |
2441 | |
2442 | void helper_msa_insert_d(CPUMIPSState *env, uint32_t wd, |
2443 | uint32_t rs_num, uint32_t n) |
2444 | { |
2445 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2446 | target_ulong rs = env->active_tc.gpr[rs_num]; |
2447 | n %= 2; |
2448 | pwd->d[n] = (int64_t)rs; |
2449 | } |
2450 | |
2451 | void helper_msa_insve_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2452 | uint32_t ws, uint32_t n) |
2453 | { |
2454 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2455 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2456 | |
2457 | switch (df) { |
2458 | case DF_BYTE: |
2459 | pwd->b[n] = (int8_t)pws->b[0]; |
2460 | break; |
2461 | case DF_HALF: |
2462 | pwd->h[n] = (int16_t)pws->h[0]; |
2463 | break; |
2464 | case DF_WORD: |
2465 | pwd->w[n] = (int32_t)pws->w[0]; |
2466 | break; |
2467 | case DF_DOUBLE: |
2468 | pwd->d[n] = (int64_t)pws->d[0]; |
2469 | break; |
2470 | default: |
2471 | assert(0); |
2472 | } |
2473 | } |
2474 | |
2475 | void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd) |
2476 | { |
2477 | switch (cd) { |
2478 | case 0: |
2479 | break; |
2480 | case 1: |
2481 | env->active_tc.msacsr = (int32_t)elm & MSACSR_MASK; |
2482 | restore_msa_fp_status(env); |
2483 | /* check exception */ |
2484 | if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED) |
2485 | & GET_FP_CAUSE(env->active_tc.msacsr)) { |
2486 | do_raise_exception(env, EXCP_MSAFPE, GETPC()); |
2487 | } |
2488 | break; |
2489 | } |
2490 | } |
2491 | |
2492 | target_ulong helper_msa_cfcmsa(CPUMIPSState *env, uint32_t cs) |
2493 | { |
2494 | switch (cs) { |
2495 | case 0: |
2496 | return env->msair; |
2497 | case 1: |
2498 | return env->active_tc.msacsr & MSACSR_MASK; |
2499 | } |
2500 | return 0; |
2501 | } |
2502 | |
2503 | void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws) |
2504 | { |
2505 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2506 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
2507 | |
2508 | msa_move_v(pwd, pws); |
2509 | } |
2510 | |
2511 | static inline int64_t msa_pcnt_df(uint32_t df, int64_t arg) |
2512 | { |
2513 | uint64_t x; |
2514 | |
2515 | x = UNSIGNED(arg, df); |
2516 | |
2517 | x = (x & 0x5555555555555555ULL) + ((x >> 1) & 0x5555555555555555ULL); |
2518 | x = (x & 0x3333333333333333ULL) + ((x >> 2) & 0x3333333333333333ULL); |
2519 | x = (x & 0x0F0F0F0F0F0F0F0FULL) + ((x >> 4) & 0x0F0F0F0F0F0F0F0FULL); |
2520 | x = (x & 0x00FF00FF00FF00FFULL) + ((x >> 8) & 0x00FF00FF00FF00FFULL); |
2521 | x = (x & 0x0000FFFF0000FFFFULL) + ((x >> 16) & 0x0000FFFF0000FFFFULL); |
2522 | x = (x & 0x00000000FFFFFFFFULL) + ((x >> 32)); |
2523 | |
2524 | return x; |
2525 | } |
2526 | |
2527 | static inline int64_t msa_nlzc_df(uint32_t df, int64_t arg) |
2528 | { |
2529 | uint64_t x, y; |
2530 | int n, c; |
2531 | |
2532 | x = UNSIGNED(arg, df); |
2533 | n = DF_BITS(df); |
2534 | c = DF_BITS(df) / 2; |
2535 | |
2536 | do { |
2537 | y = x >> c; |
2538 | if (y != 0) { |
2539 | n = n - c; |
2540 | x = y; |
2541 | } |
2542 | c = c >> 1; |
2543 | } while (c != 0); |
2544 | |
2545 | return n - x; |
2546 | } |
2547 | |
2548 | static inline int64_t msa_nloc_df(uint32_t df, int64_t arg) |
2549 | { |
2550 | return msa_nlzc_df(df, UNSIGNED((~arg), df)); |
2551 | } |
2552 | |
2553 | void helper_msa_fill_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
2554 | uint32_t rs) |
2555 | { |
2556 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
2557 | uint32_t i; |
2558 | |
2559 | switch (df) { |
2560 | case DF_BYTE: |
2561 | for (i = 0; i < DF_ELEMENTS(DF_BYTE); i++) { |
2562 | pwd->b[i] = (int8_t)env->active_tc.gpr[rs]; |
2563 | } |
2564 | break; |
2565 | case DF_HALF: |
2566 | for (i = 0; i < DF_ELEMENTS(DF_HALF); i++) { |
2567 | pwd->h[i] = (int16_t)env->active_tc.gpr[rs]; |
2568 | } |
2569 | break; |
2570 | case DF_WORD: |
2571 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
2572 | pwd->w[i] = (int32_t)env->active_tc.gpr[rs]; |
2573 | } |
2574 | break; |
2575 | case DF_DOUBLE: |
2576 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
2577 | pwd->d[i] = (int64_t)env->active_tc.gpr[rs]; |
2578 | } |
2579 | break; |
2580 | default: |
2581 | assert(0); |
2582 | } |
2583 | } |
2584 | |
2585 | #define MSA_UNOP_DF(func) \ |
2586 | void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \ |
2587 | uint32_t wd, uint32_t ws) \ |
2588 | { \ |
2589 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); \ |
2590 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); \ |
2591 | \ |
2592 | switch (df) { \ |
2593 | case DF_BYTE: \ |
2594 | pwd->b[0] = msa_ ## func ## _df(df, pws->b[0]); \ |
2595 | pwd->b[1] = msa_ ## func ## _df(df, pws->b[1]); \ |
2596 | pwd->b[2] = msa_ ## func ## _df(df, pws->b[2]); \ |
2597 | pwd->b[3] = msa_ ## func ## _df(df, pws->b[3]); \ |
2598 | pwd->b[4] = msa_ ## func ## _df(df, pws->b[4]); \ |
2599 | pwd->b[5] = msa_ ## func ## _df(df, pws->b[5]); \ |
2600 | pwd->b[6] = msa_ ## func ## _df(df, pws->b[6]); \ |
2601 | pwd->b[7] = msa_ ## func ## _df(df, pws->b[7]); \ |
2602 | pwd->b[8] = msa_ ## func ## _df(df, pws->b[8]); \ |
2603 | pwd->b[9] = msa_ ## func ## _df(df, pws->b[9]); \ |
2604 | pwd->b[10] = msa_ ## func ## _df(df, pws->b[10]); \ |
2605 | pwd->b[11] = msa_ ## func ## _df(df, pws->b[11]); \ |
2606 | pwd->b[12] = msa_ ## func ## _df(df, pws->b[12]); \ |
2607 | pwd->b[13] = msa_ ## func ## _df(df, pws->b[13]); \ |
2608 | pwd->b[14] = msa_ ## func ## _df(df, pws->b[14]); \ |
2609 | pwd->b[15] = msa_ ## func ## _df(df, pws->b[15]); \ |
2610 | break; \ |
2611 | case DF_HALF: \ |
2612 | pwd->h[0] = msa_ ## func ## _df(df, pws->h[0]); \ |
2613 | pwd->h[1] = msa_ ## func ## _df(df, pws->h[1]); \ |
2614 | pwd->h[2] = msa_ ## func ## _df(df, pws->h[2]); \ |
2615 | pwd->h[3] = msa_ ## func ## _df(df, pws->h[3]); \ |
2616 | pwd->h[4] = msa_ ## func ## _df(df, pws->h[4]); \ |
2617 | pwd->h[5] = msa_ ## func ## _df(df, pws->h[5]); \ |
2618 | pwd->h[6] = msa_ ## func ## _df(df, pws->h[6]); \ |
2619 | pwd->h[7] = msa_ ## func ## _df(df, pws->h[7]); \ |
2620 | break; \ |
2621 | case DF_WORD: \ |
2622 | pwd->w[0] = msa_ ## func ## _df(df, pws->w[0]); \ |
2623 | pwd->w[1] = msa_ ## func ## _df(df, pws->w[1]); \ |
2624 | pwd->w[2] = msa_ ## func ## _df(df, pws->w[2]); \ |
2625 | pwd->w[3] = msa_ ## func ## _df(df, pws->w[3]); \ |
2626 | break; \ |
2627 | case DF_DOUBLE: \ |
2628 | pwd->d[0] = msa_ ## func ## _df(df, pws->d[0]); \ |
2629 | pwd->d[1] = msa_ ## func ## _df(df, pws->d[1]); \ |
2630 | break; \ |
2631 | default: \ |
2632 | assert(0); \ |
2633 | } \ |
2634 | } |
2635 | |
2636 | MSA_UNOP_DF(nlzc) |
2637 | MSA_UNOP_DF(nloc) |
2638 | MSA_UNOP_DF(pcnt) |
2639 | #undef MSA_UNOP_DF |
2640 | |
2641 | #define FLOAT_ONE32 make_float32(0x3f8 << 20) |
2642 | #define FLOAT_ONE64 make_float64(0x3ffULL << 52) |
2643 | |
2644 | #define FLOAT_SNAN16(s) (float16_default_nan(s) ^ 0x0220) |
2645 | /* 0x7c20 */ |
2646 | #define FLOAT_SNAN32(s) (float32_default_nan(s) ^ 0x00400020) |
2647 | /* 0x7f800020 */ |
2648 | #define FLOAT_SNAN64(s) (float64_default_nan(s) ^ 0x0008000000000020ULL) |
2649 | /* 0x7ff0000000000020 */ |
2650 | |
2651 | static inline void clear_msacsr_cause(CPUMIPSState *env) |
2652 | { |
2653 | SET_FP_CAUSE(env->active_tc.msacsr, 0); |
2654 | } |
2655 | |
2656 | static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr) |
2657 | { |
2658 | if ((GET_FP_CAUSE(env->active_tc.msacsr) & |
2659 | (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) { |
2660 | UPDATE_FP_FLAGS(env->active_tc.msacsr, |
2661 | GET_FP_CAUSE(env->active_tc.msacsr)); |
2662 | } else { |
2663 | do_raise_exception(env, EXCP_MSAFPE, retaddr); |
2664 | } |
2665 | } |
2666 | |
2667 | /* Flush-to-zero use cases for update_msacsr() */ |
2668 | #define CLEAR_FS_UNDERFLOW 1 |
2669 | #define CLEAR_IS_INEXACT 2 |
2670 | #define RECIPROCAL_INEXACT 4 |
2671 | |
2672 | static inline int update_msacsr(CPUMIPSState *env, int action, int denormal) |
2673 | { |
2674 | int ieee_ex; |
2675 | |
2676 | int c; |
2677 | int cause; |
2678 | int enable; |
2679 | |
2680 | ieee_ex = get_float_exception_flags(&env->active_tc.msa_fp_status); |
2681 | |
2682 | /* QEMU softfloat does not signal all underflow cases */ |
2683 | if (denormal) { |
2684 | ieee_ex |= float_flag_underflow; |
2685 | } |
2686 | |
2687 | c = ieee_ex_to_mips(ieee_ex); |
2688 | enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED; |
2689 | |
2690 | /* Set Inexact (I) when flushing inputs to zero */ |
2691 | if ((ieee_ex & float_flag_input_denormal) && |
2692 | (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { |
2693 | if (action & CLEAR_IS_INEXACT) { |
2694 | c &= ~FP_INEXACT; |
2695 | } else { |
2696 | c |= FP_INEXACT; |
2697 | } |
2698 | } |
2699 | |
2700 | /* Set Inexact (I) and Underflow (U) when flushing outputs to zero */ |
2701 | if ((ieee_ex & float_flag_output_denormal) && |
2702 | (env->active_tc.msacsr & MSACSR_FS_MASK) != 0) { |
2703 | c |= FP_INEXACT; |
2704 | if (action & CLEAR_FS_UNDERFLOW) { |
2705 | c &= ~FP_UNDERFLOW; |
2706 | } else { |
2707 | c |= FP_UNDERFLOW; |
2708 | } |
2709 | } |
2710 | |
2711 | /* Set Inexact (I) when Overflow (O) is not enabled */ |
2712 | if ((c & FP_OVERFLOW) != 0 && (enable & FP_OVERFLOW) == 0) { |
2713 | c |= FP_INEXACT; |
2714 | } |
2715 | |
2716 | /* Clear Exact Underflow when Underflow (U) is not enabled */ |
2717 | if ((c & FP_UNDERFLOW) != 0 && (enable & FP_UNDERFLOW) == 0 && |
2718 | (c & FP_INEXACT) == 0) { |
2719 | c &= ~FP_UNDERFLOW; |
2720 | } |
2721 | |
2722 | /* |
2723 | * Reciprocal operations set only Inexact when valid and not |
2724 | * divide by zero |
2725 | */ |
2726 | if ((action & RECIPROCAL_INEXACT) && |
2727 | (c & (FP_INVALID | FP_DIV0)) == 0) { |
2728 | c = FP_INEXACT; |
2729 | } |
2730 | |
2731 | cause = c & enable; /* all current enabled exceptions */ |
2732 | |
2733 | if (cause == 0) { |
2734 | /* |
2735 | * No enabled exception, update the MSACSR Cause |
2736 | * with all current exceptions |
2737 | */ |
2738 | SET_FP_CAUSE(env->active_tc.msacsr, |
2739 | (GET_FP_CAUSE(env->active_tc.msacsr) | c)); |
2740 | } else { |
2741 | /* Current exceptions are enabled */ |
2742 | if ((env->active_tc.msacsr & MSACSR_NX_MASK) == 0) { |
2743 | /* |
2744 | * Exception(s) will trap, update MSACSR Cause |
2745 | * with all enabled exceptions |
2746 | */ |
2747 | SET_FP_CAUSE(env->active_tc.msacsr, |
2748 | (GET_FP_CAUSE(env->active_tc.msacsr) | c)); |
2749 | } |
2750 | } |
2751 | |
2752 | return c; |
2753 | } |
2754 | |
2755 | static inline int get_enabled_exceptions(const CPUMIPSState *env, int c) |
2756 | { |
2757 | int enable = GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED; |
2758 | return c & enable; |
2759 | } |
2760 | |
2761 | static inline float16 float16_from_float32(int32_t a, flag ieee, |
2762 | float_status *status) |
2763 | { |
2764 | float16 f_val; |
2765 | |
2766 | f_val = float32_to_float16((float32)a, ieee, status); |
2767 | |
2768 | return a < 0 ? (f_val | (1 << 15)) : f_val; |
2769 | } |
2770 | |
2771 | static inline float32 float32_from_float64(int64_t a, float_status *status) |
2772 | { |
2773 | float32 f_val; |
2774 | |
2775 | f_val = float64_to_float32((float64)a, status); |
2776 | |
2777 | return a < 0 ? (f_val | (1 << 31)) : f_val; |
2778 | } |
2779 | |
2780 | static inline float32 float32_from_float16(int16_t a, flag ieee, |
2781 | float_status *status) |
2782 | { |
2783 | float32 f_val; |
2784 | |
2785 | f_val = float16_to_float32((float16)a, ieee, status); |
2786 | |
2787 | return a < 0 ? (f_val | (1 << 31)) : f_val; |
2788 | } |
2789 | |
2790 | static inline float64 float64_from_float32(int32_t a, float_status *status) |
2791 | { |
2792 | float64 f_val; |
2793 | |
2794 | f_val = float32_to_float64((float64)a, status); |
2795 | |
2796 | return a < 0 ? (f_val | (1ULL << 63)) : f_val; |
2797 | } |
2798 | |
2799 | static inline float32 float32_from_q16(int16_t a, float_status *status) |
2800 | { |
2801 | float32 f_val; |
2802 | |
2803 | /* conversion as integer and scaling */ |
2804 | f_val = int32_to_float32(a, status); |
2805 | f_val = float32_scalbn(f_val, -15, status); |
2806 | |
2807 | return f_val; |
2808 | } |
2809 | |
2810 | static inline float64 float64_from_q32(int32_t a, float_status *status) |
2811 | { |
2812 | float64 f_val; |
2813 | |
2814 | /* conversion as integer and scaling */ |
2815 | f_val = int32_to_float64(a, status); |
2816 | f_val = float64_scalbn(f_val, -31, status); |
2817 | |
2818 | return f_val; |
2819 | } |
2820 | |
2821 | static inline int16_t float32_to_q16(float32 a, float_status *status) |
2822 | { |
2823 | int32_t q_val; |
2824 | int32_t q_min = 0xffff8000; |
2825 | int32_t q_max = 0x00007fff; |
2826 | |
2827 | int ieee_ex; |
2828 | |
2829 | if (float32_is_any_nan(a)) { |
2830 | float_raise(float_flag_invalid, status); |
2831 | return 0; |
2832 | } |
2833 | |
2834 | /* scaling */ |
2835 | a = float32_scalbn(a, 15, status); |
2836 | |
2837 | ieee_ex = get_float_exception_flags(status); |
2838 | set_float_exception_flags(ieee_ex & (~float_flag_underflow) |
2839 | , status); |
2840 | |
2841 | if (ieee_ex & float_flag_overflow) { |
2842 | float_raise(float_flag_inexact, status); |
2843 | return (int32_t)a < 0 ? q_min : q_max; |
2844 | } |
2845 | |
2846 | /* conversion to int */ |
2847 | q_val = float32_to_int32(a, status); |
2848 | |
2849 | ieee_ex = get_float_exception_flags(status); |
2850 | set_float_exception_flags(ieee_ex & (~float_flag_underflow) |
2851 | , status); |
2852 | |
2853 | if (ieee_ex & float_flag_invalid) { |
2854 | set_float_exception_flags(ieee_ex & (~float_flag_invalid) |
2855 | , status); |
2856 | float_raise(float_flag_overflow | float_flag_inexact, status); |
2857 | return (int32_t)a < 0 ? q_min : q_max; |
2858 | } |
2859 | |
2860 | if (q_val < q_min) { |
2861 | float_raise(float_flag_overflow | float_flag_inexact, status); |
2862 | return (int16_t)q_min; |
2863 | } |
2864 | |
2865 | if (q_max < q_val) { |
2866 | float_raise(float_flag_overflow | float_flag_inexact, status); |
2867 | return (int16_t)q_max; |
2868 | } |
2869 | |
2870 | return (int16_t)q_val; |
2871 | } |
2872 | |
2873 | static inline int32_t float64_to_q32(float64 a, float_status *status) |
2874 | { |
2875 | int64_t q_val; |
2876 | int64_t q_min = 0xffffffff80000000LL; |
2877 | int64_t q_max = 0x000000007fffffffLL; |
2878 | |
2879 | int ieee_ex; |
2880 | |
2881 | if (float64_is_any_nan(a)) { |
2882 | float_raise(float_flag_invalid, status); |
2883 | return 0; |
2884 | } |
2885 | |
2886 | /* scaling */ |
2887 | a = float64_scalbn(a, 31, status); |
2888 | |
2889 | ieee_ex = get_float_exception_flags(status); |
2890 | set_float_exception_flags(ieee_ex & (~float_flag_underflow) |
2891 | , status); |
2892 | |
2893 | if (ieee_ex & float_flag_overflow) { |
2894 | float_raise(float_flag_inexact, status); |
2895 | return (int64_t)a < 0 ? q_min : q_max; |
2896 | } |
2897 | |
2898 | /* conversion to integer */ |
2899 | q_val = float64_to_int64(a, status); |
2900 | |
2901 | ieee_ex = get_float_exception_flags(status); |
2902 | set_float_exception_flags(ieee_ex & (~float_flag_underflow) |
2903 | , status); |
2904 | |
2905 | if (ieee_ex & float_flag_invalid) { |
2906 | set_float_exception_flags(ieee_ex & (~float_flag_invalid) |
2907 | , status); |
2908 | float_raise(float_flag_overflow | float_flag_inexact, status); |
2909 | return (int64_t)a < 0 ? q_min : q_max; |
2910 | } |
2911 | |
2912 | if (q_val < q_min) { |
2913 | float_raise(float_flag_overflow | float_flag_inexact, status); |
2914 | return (int32_t)q_min; |
2915 | } |
2916 | |
2917 | if (q_max < q_val) { |
2918 | float_raise(float_flag_overflow | float_flag_inexact, status); |
2919 | return (int32_t)q_max; |
2920 | } |
2921 | |
2922 | return (int32_t)q_val; |
2923 | } |
2924 | |
2925 | #define MSA_FLOAT_COND(DEST, OP, ARG1, ARG2, BITS, QUIET) \ |
2926 | do { \ |
2927 | float_status *status = &env->active_tc.msa_fp_status; \ |
2928 | int c; \ |
2929 | int64_t cond; \ |
2930 | set_float_exception_flags(0, status); \ |
2931 | if (!QUIET) { \ |
2932 | cond = float ## BITS ## _ ## OP(ARG1, ARG2, status); \ |
2933 | } else { \ |
2934 | cond = float ## BITS ## _ ## OP ## _quiet(ARG1, ARG2, status); \ |
2935 | } \ |
2936 | DEST = cond ? M_MAX_UINT(BITS) : 0; \ |
2937 | c = update_msacsr(env, CLEAR_IS_INEXACT, 0); \ |
2938 | \ |
2939 | if (get_enabled_exceptions(env, c)) { \ |
2940 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
2941 | } \ |
2942 | } while (0) |
2943 | |
2944 | #define MSA_FLOAT_AF(DEST, ARG1, ARG2, BITS, QUIET) \ |
2945 | do { \ |
2946 | MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \ |
2947 | if ((DEST & M_MAX_UINT(BITS)) == M_MAX_UINT(BITS)) { \ |
2948 | DEST = 0; \ |
2949 | } \ |
2950 | } while (0) |
2951 | |
2952 | #define MSA_FLOAT_UEQ(DEST, ARG1, ARG2, BITS, QUIET) \ |
2953 | do { \ |
2954 | MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \ |
2955 | if (DEST == 0) { \ |
2956 | MSA_FLOAT_COND(DEST, eq, ARG1, ARG2, BITS, QUIET); \ |
2957 | } \ |
2958 | } while (0) |
2959 | |
2960 | #define MSA_FLOAT_NE(DEST, ARG1, ARG2, BITS, QUIET) \ |
2961 | do { \ |
2962 | MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \ |
2963 | if (DEST == 0) { \ |
2964 | MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \ |
2965 | } \ |
2966 | } while (0) |
2967 | |
2968 | #define MSA_FLOAT_UNE(DEST, ARG1, ARG2, BITS, QUIET) \ |
2969 | do { \ |
2970 | MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \ |
2971 | if (DEST == 0) { \ |
2972 | MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \ |
2973 | if (DEST == 0) { \ |
2974 | MSA_FLOAT_COND(DEST, lt, ARG2, ARG1, BITS, QUIET); \ |
2975 | } \ |
2976 | } \ |
2977 | } while (0) |
2978 | |
2979 | #define MSA_FLOAT_ULE(DEST, ARG1, ARG2, BITS, QUIET) \ |
2980 | do { \ |
2981 | MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \ |
2982 | if (DEST == 0) { \ |
2983 | MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \ |
2984 | } \ |
2985 | } while (0) |
2986 | |
2987 | #define MSA_FLOAT_ULT(DEST, ARG1, ARG2, BITS, QUIET) \ |
2988 | do { \ |
2989 | MSA_FLOAT_COND(DEST, unordered, ARG1, ARG2, BITS, QUIET); \ |
2990 | if (DEST == 0) { \ |
2991 | MSA_FLOAT_COND(DEST, lt, ARG1, ARG2, BITS, QUIET); \ |
2992 | } \ |
2993 | } while (0) |
2994 | |
2995 | #define MSA_FLOAT_OR(DEST, ARG1, ARG2, BITS, QUIET) \ |
2996 | do { \ |
2997 | MSA_FLOAT_COND(DEST, le, ARG1, ARG2, BITS, QUIET); \ |
2998 | if (DEST == 0) { \ |
2999 | MSA_FLOAT_COND(DEST, le, ARG2, ARG1, BITS, QUIET); \ |
3000 | } \ |
3001 | } while (0) |
3002 | |
3003 | static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3004 | wr_t *pwt, uint32_t df, int quiet, |
3005 | uintptr_t retaddr) |
3006 | { |
3007 | wr_t wx, *pwx = &wx; |
3008 | uint32_t i; |
3009 | |
3010 | clear_msacsr_cause(env); |
3011 | |
3012 | switch (df) { |
3013 | case DF_WORD: |
3014 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3015 | MSA_FLOAT_AF(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3016 | } |
3017 | break; |
3018 | case DF_DOUBLE: |
3019 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3020 | MSA_FLOAT_AF(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3021 | } |
3022 | break; |
3023 | default: |
3024 | assert(0); |
3025 | } |
3026 | |
3027 | check_msacsr_cause(env, retaddr); |
3028 | |
3029 | msa_move_v(pwd, pwx); |
3030 | } |
3031 | |
3032 | static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3033 | wr_t *pwt, uint32_t df, int quiet, |
3034 | uintptr_t retaddr) |
3035 | { |
3036 | wr_t wx, *pwx = &wx; |
3037 | uint32_t i; |
3038 | |
3039 | clear_msacsr_cause(env); |
3040 | |
3041 | switch (df) { |
3042 | case DF_WORD: |
3043 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3044 | MSA_FLOAT_COND(pwx->w[i], unordered, pws->w[i], pwt->w[i], 32, |
3045 | quiet); |
3046 | } |
3047 | break; |
3048 | case DF_DOUBLE: |
3049 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3050 | MSA_FLOAT_COND(pwx->d[i], unordered, pws->d[i], pwt->d[i], 64, |
3051 | quiet); |
3052 | } |
3053 | break; |
3054 | default: |
3055 | assert(0); |
3056 | } |
3057 | |
3058 | check_msacsr_cause(env, retaddr); |
3059 | |
3060 | msa_move_v(pwd, pwx); |
3061 | } |
3062 | |
3063 | static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3064 | wr_t *pwt, uint32_t df, int quiet, |
3065 | uintptr_t retaddr) |
3066 | { |
3067 | wr_t wx, *pwx = &wx; |
3068 | uint32_t i; |
3069 | |
3070 | clear_msacsr_cause(env); |
3071 | |
3072 | switch (df) { |
3073 | case DF_WORD: |
3074 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3075 | MSA_FLOAT_COND(pwx->w[i], eq, pws->w[i], pwt->w[i], 32, quiet); |
3076 | } |
3077 | break; |
3078 | case DF_DOUBLE: |
3079 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3080 | MSA_FLOAT_COND(pwx->d[i], eq, pws->d[i], pwt->d[i], 64, quiet); |
3081 | } |
3082 | break; |
3083 | default: |
3084 | assert(0); |
3085 | } |
3086 | |
3087 | check_msacsr_cause(env, retaddr); |
3088 | |
3089 | msa_move_v(pwd, pwx); |
3090 | } |
3091 | |
3092 | static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3093 | wr_t *pwt, uint32_t df, int quiet, |
3094 | uintptr_t retaddr) |
3095 | { |
3096 | wr_t wx, *pwx = &wx; |
3097 | uint32_t i; |
3098 | |
3099 | clear_msacsr_cause(env); |
3100 | |
3101 | switch (df) { |
3102 | case DF_WORD: |
3103 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3104 | MSA_FLOAT_UEQ(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3105 | } |
3106 | break; |
3107 | case DF_DOUBLE: |
3108 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3109 | MSA_FLOAT_UEQ(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3110 | } |
3111 | break; |
3112 | default: |
3113 | assert(0); |
3114 | } |
3115 | |
3116 | check_msacsr_cause(env, retaddr); |
3117 | |
3118 | msa_move_v(pwd, pwx); |
3119 | } |
3120 | |
3121 | static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3122 | wr_t *pwt, uint32_t df, int quiet, |
3123 | uintptr_t retaddr) |
3124 | { |
3125 | wr_t wx, *pwx = &wx; |
3126 | uint32_t i; |
3127 | |
3128 | clear_msacsr_cause(env); |
3129 | |
3130 | switch (df) { |
3131 | case DF_WORD: |
3132 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3133 | MSA_FLOAT_COND(pwx->w[i], lt, pws->w[i], pwt->w[i], 32, quiet); |
3134 | } |
3135 | break; |
3136 | case DF_DOUBLE: |
3137 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3138 | MSA_FLOAT_COND(pwx->d[i], lt, pws->d[i], pwt->d[i], 64, quiet); |
3139 | } |
3140 | break; |
3141 | default: |
3142 | assert(0); |
3143 | } |
3144 | |
3145 | check_msacsr_cause(env, retaddr); |
3146 | |
3147 | msa_move_v(pwd, pwx); |
3148 | } |
3149 | |
3150 | static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3151 | wr_t *pwt, uint32_t df, int quiet, |
3152 | uintptr_t retaddr) |
3153 | { |
3154 | wr_t wx, *pwx = &wx; |
3155 | uint32_t i; |
3156 | |
3157 | clear_msacsr_cause(env); |
3158 | |
3159 | switch (df) { |
3160 | case DF_WORD: |
3161 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3162 | MSA_FLOAT_ULT(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3163 | } |
3164 | break; |
3165 | case DF_DOUBLE: |
3166 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3167 | MSA_FLOAT_ULT(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3168 | } |
3169 | break; |
3170 | default: |
3171 | assert(0); |
3172 | } |
3173 | |
3174 | check_msacsr_cause(env, retaddr); |
3175 | |
3176 | msa_move_v(pwd, pwx); |
3177 | } |
3178 | |
3179 | static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3180 | wr_t *pwt, uint32_t df, int quiet, |
3181 | uintptr_t retaddr) |
3182 | { |
3183 | wr_t wx, *pwx = &wx; |
3184 | uint32_t i; |
3185 | |
3186 | clear_msacsr_cause(env); |
3187 | |
3188 | switch (df) { |
3189 | case DF_WORD: |
3190 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3191 | MSA_FLOAT_COND(pwx->w[i], le, pws->w[i], pwt->w[i], 32, quiet); |
3192 | } |
3193 | break; |
3194 | case DF_DOUBLE: |
3195 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3196 | MSA_FLOAT_COND(pwx->d[i], le, pws->d[i], pwt->d[i], 64, quiet); |
3197 | } |
3198 | break; |
3199 | default: |
3200 | assert(0); |
3201 | } |
3202 | |
3203 | check_msacsr_cause(env, retaddr); |
3204 | |
3205 | msa_move_v(pwd, pwx); |
3206 | } |
3207 | |
3208 | static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3209 | wr_t *pwt, uint32_t df, int quiet, |
3210 | uintptr_t retaddr) |
3211 | { |
3212 | wr_t wx, *pwx = &wx; |
3213 | uint32_t i; |
3214 | |
3215 | clear_msacsr_cause(env); |
3216 | |
3217 | switch (df) { |
3218 | case DF_WORD: |
3219 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3220 | MSA_FLOAT_ULE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3221 | } |
3222 | break; |
3223 | case DF_DOUBLE: |
3224 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3225 | MSA_FLOAT_ULE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3226 | } |
3227 | break; |
3228 | default: |
3229 | assert(0); |
3230 | } |
3231 | |
3232 | check_msacsr_cause(env, retaddr); |
3233 | |
3234 | msa_move_v(pwd, pwx); |
3235 | } |
3236 | |
3237 | static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3238 | wr_t *pwt, uint32_t df, int quiet, |
3239 | uintptr_t retaddr) |
3240 | { |
3241 | wr_t wx, *pwx = &wx; |
3242 | uint32_t i; |
3243 | |
3244 | clear_msacsr_cause(env); |
3245 | |
3246 | switch (df) { |
3247 | case DF_WORD: |
3248 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3249 | MSA_FLOAT_OR(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3250 | } |
3251 | break; |
3252 | case DF_DOUBLE: |
3253 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3254 | MSA_FLOAT_OR(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3255 | } |
3256 | break; |
3257 | default: |
3258 | assert(0); |
3259 | } |
3260 | |
3261 | check_msacsr_cause(env, retaddr); |
3262 | |
3263 | msa_move_v(pwd, pwx); |
3264 | } |
3265 | |
3266 | static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3267 | wr_t *pwt, uint32_t df, int quiet, |
3268 | uintptr_t retaddr) |
3269 | { |
3270 | wr_t wx, *pwx = &wx; |
3271 | uint32_t i; |
3272 | |
3273 | clear_msacsr_cause(env); |
3274 | |
3275 | switch (df) { |
3276 | case DF_WORD: |
3277 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3278 | MSA_FLOAT_UNE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3279 | } |
3280 | break; |
3281 | case DF_DOUBLE: |
3282 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3283 | MSA_FLOAT_UNE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3284 | } |
3285 | break; |
3286 | default: |
3287 | assert(0); |
3288 | } |
3289 | |
3290 | check_msacsr_cause(env, retaddr); |
3291 | |
3292 | msa_move_v(pwd, pwx); |
3293 | } |
3294 | |
3295 | static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws, |
3296 | wr_t *pwt, uint32_t df, int quiet, |
3297 | uintptr_t retaddr) |
3298 | { |
3299 | wr_t wx, *pwx = &wx; |
3300 | uint32_t i; |
3301 | |
3302 | clear_msacsr_cause(env); |
3303 | |
3304 | switch (df) { |
3305 | case DF_WORD: |
3306 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3307 | MSA_FLOAT_NE(pwx->w[i], pws->w[i], pwt->w[i], 32, quiet); |
3308 | } |
3309 | break; |
3310 | case DF_DOUBLE: |
3311 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3312 | MSA_FLOAT_NE(pwx->d[i], pws->d[i], pwt->d[i], 64, quiet); |
3313 | } |
3314 | break; |
3315 | default: |
3316 | assert(0); |
3317 | } |
3318 | |
3319 | check_msacsr_cause(env, retaddr); |
3320 | |
3321 | msa_move_v(pwd, pwx); |
3322 | } |
3323 | |
3324 | void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3325 | uint32_t ws, uint32_t wt) |
3326 | { |
3327 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3328 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3329 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3330 | compare_af(env, pwd, pws, pwt, df, 1, GETPC()); |
3331 | } |
3332 | |
3333 | void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3334 | uint32_t ws, uint32_t wt) |
3335 | { |
3336 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3337 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3338 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3339 | compare_un(env, pwd, pws, pwt, df, 1, GETPC()); |
3340 | } |
3341 | |
3342 | void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3343 | uint32_t ws, uint32_t wt) |
3344 | { |
3345 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3346 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3347 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3348 | compare_eq(env, pwd, pws, pwt, df, 1, GETPC()); |
3349 | } |
3350 | |
3351 | void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3352 | uint32_t ws, uint32_t wt) |
3353 | { |
3354 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3355 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3356 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3357 | compare_ueq(env, pwd, pws, pwt, df, 1, GETPC()); |
3358 | } |
3359 | |
3360 | void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3361 | uint32_t ws, uint32_t wt) |
3362 | { |
3363 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3364 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3365 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3366 | compare_lt(env, pwd, pws, pwt, df, 1, GETPC()); |
3367 | } |
3368 | |
3369 | void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3370 | uint32_t ws, uint32_t wt) |
3371 | { |
3372 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3373 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3374 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3375 | compare_ult(env, pwd, pws, pwt, df, 1, GETPC()); |
3376 | } |
3377 | |
3378 | void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3379 | uint32_t ws, uint32_t wt) |
3380 | { |
3381 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3382 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3383 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3384 | compare_le(env, pwd, pws, pwt, df, 1, GETPC()); |
3385 | } |
3386 | |
3387 | void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3388 | uint32_t ws, uint32_t wt) |
3389 | { |
3390 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3391 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3392 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3393 | compare_ule(env, pwd, pws, pwt, df, 1, GETPC()); |
3394 | } |
3395 | |
3396 | void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3397 | uint32_t ws, uint32_t wt) |
3398 | { |
3399 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3400 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3401 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3402 | compare_af(env, pwd, pws, pwt, df, 0, GETPC()); |
3403 | } |
3404 | |
3405 | void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3406 | uint32_t ws, uint32_t wt) |
3407 | { |
3408 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3409 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3410 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3411 | compare_un(env, pwd, pws, pwt, df, 0, GETPC()); |
3412 | } |
3413 | |
3414 | void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3415 | uint32_t ws, uint32_t wt) |
3416 | { |
3417 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3418 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3419 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3420 | compare_eq(env, pwd, pws, pwt, df, 0, GETPC()); |
3421 | } |
3422 | |
3423 | void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3424 | uint32_t ws, uint32_t wt) |
3425 | { |
3426 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3427 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3428 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3429 | compare_ueq(env, pwd, pws, pwt, df, 0, GETPC()); |
3430 | } |
3431 | |
3432 | void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3433 | uint32_t ws, uint32_t wt) |
3434 | { |
3435 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3436 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3437 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3438 | compare_lt(env, pwd, pws, pwt, df, 0, GETPC()); |
3439 | } |
3440 | |
3441 | void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3442 | uint32_t ws, uint32_t wt) |
3443 | { |
3444 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3445 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3446 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3447 | compare_ult(env, pwd, pws, pwt, df, 0, GETPC()); |
3448 | } |
3449 | |
3450 | void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3451 | uint32_t ws, uint32_t wt) |
3452 | { |
3453 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3454 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3455 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3456 | compare_le(env, pwd, pws, pwt, df, 0, GETPC()); |
3457 | } |
3458 | |
3459 | void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3460 | uint32_t ws, uint32_t wt) |
3461 | { |
3462 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3463 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3464 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3465 | compare_ule(env, pwd, pws, pwt, df, 0, GETPC()); |
3466 | } |
3467 | |
3468 | void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3469 | uint32_t ws, uint32_t wt) |
3470 | { |
3471 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3472 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3473 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3474 | compare_or(env, pwd, pws, pwt, df, 1, GETPC()); |
3475 | } |
3476 | |
3477 | void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3478 | uint32_t ws, uint32_t wt) |
3479 | { |
3480 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3481 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3482 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3483 | compare_une(env, pwd, pws, pwt, df, 1, GETPC()); |
3484 | } |
3485 | |
3486 | void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3487 | uint32_t ws, uint32_t wt) |
3488 | { |
3489 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3490 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3491 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3492 | compare_ne(env, pwd, pws, pwt, df, 1, GETPC()); |
3493 | } |
3494 | |
3495 | void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3496 | uint32_t ws, uint32_t wt) |
3497 | { |
3498 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3499 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3500 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3501 | compare_or(env, pwd, pws, pwt, df, 0, GETPC()); |
3502 | } |
3503 | |
3504 | void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3505 | uint32_t ws, uint32_t wt) |
3506 | { |
3507 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3508 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3509 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3510 | compare_une(env, pwd, pws, pwt, df, 0, GETPC()); |
3511 | } |
3512 | |
3513 | void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3514 | uint32_t ws, uint32_t wt) |
3515 | { |
3516 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3517 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3518 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3519 | compare_ne(env, pwd, pws, pwt, df, 0, GETPC()); |
3520 | } |
3521 | |
3522 | #define float16_is_zero(ARG) 0 |
3523 | #define float16_is_zero_or_denormal(ARG) 0 |
3524 | |
3525 | #define IS_DENORMAL(ARG, BITS) \ |
3526 | (!float ## BITS ## _is_zero(ARG) \ |
3527 | && float ## BITS ## _is_zero_or_denormal(ARG)) |
3528 | |
3529 | #define MSA_FLOAT_BINOP(DEST, OP, ARG1, ARG2, BITS) \ |
3530 | do { \ |
3531 | float_status *status = &env->active_tc.msa_fp_status; \ |
3532 | int c; \ |
3533 | \ |
3534 | set_float_exception_flags(0, status); \ |
3535 | DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \ |
3536 | c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \ |
3537 | \ |
3538 | if (get_enabled_exceptions(env, c)) { \ |
3539 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
3540 | } \ |
3541 | } while (0) |
3542 | |
3543 | void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3544 | uint32_t ws, uint32_t wt) |
3545 | { |
3546 | wr_t wx, *pwx = &wx; |
3547 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3548 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3549 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3550 | uint32_t i; |
3551 | |
3552 | clear_msacsr_cause(env); |
3553 | |
3554 | switch (df) { |
3555 | case DF_WORD: |
3556 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3557 | MSA_FLOAT_BINOP(pwx->w[i], add, pws->w[i], pwt->w[i], 32); |
3558 | } |
3559 | break; |
3560 | case DF_DOUBLE: |
3561 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3562 | MSA_FLOAT_BINOP(pwx->d[i], add, pws->d[i], pwt->d[i], 64); |
3563 | } |
3564 | break; |
3565 | default: |
3566 | assert(0); |
3567 | } |
3568 | |
3569 | check_msacsr_cause(env, GETPC()); |
3570 | msa_move_v(pwd, pwx); |
3571 | } |
3572 | |
3573 | void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3574 | uint32_t ws, uint32_t wt) |
3575 | { |
3576 | wr_t wx, *pwx = &wx; |
3577 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3578 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3579 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3580 | uint32_t i; |
3581 | |
3582 | clear_msacsr_cause(env); |
3583 | |
3584 | switch (df) { |
3585 | case DF_WORD: |
3586 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3587 | MSA_FLOAT_BINOP(pwx->w[i], sub, pws->w[i], pwt->w[i], 32); |
3588 | } |
3589 | break; |
3590 | case DF_DOUBLE: |
3591 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3592 | MSA_FLOAT_BINOP(pwx->d[i], sub, pws->d[i], pwt->d[i], 64); |
3593 | } |
3594 | break; |
3595 | default: |
3596 | assert(0); |
3597 | } |
3598 | |
3599 | check_msacsr_cause(env, GETPC()); |
3600 | msa_move_v(pwd, pwx); |
3601 | } |
3602 | |
3603 | void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3604 | uint32_t ws, uint32_t wt) |
3605 | { |
3606 | wr_t wx, *pwx = &wx; |
3607 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3608 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3609 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3610 | uint32_t i; |
3611 | |
3612 | clear_msacsr_cause(env); |
3613 | |
3614 | switch (df) { |
3615 | case DF_WORD: |
3616 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3617 | MSA_FLOAT_BINOP(pwx->w[i], mul, pws->w[i], pwt->w[i], 32); |
3618 | } |
3619 | break; |
3620 | case DF_DOUBLE: |
3621 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3622 | MSA_FLOAT_BINOP(pwx->d[i], mul, pws->d[i], pwt->d[i], 64); |
3623 | } |
3624 | break; |
3625 | default: |
3626 | assert(0); |
3627 | } |
3628 | |
3629 | check_msacsr_cause(env, GETPC()); |
3630 | |
3631 | msa_move_v(pwd, pwx); |
3632 | } |
3633 | |
3634 | void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3635 | uint32_t ws, uint32_t wt) |
3636 | { |
3637 | wr_t wx, *pwx = &wx; |
3638 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3639 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3640 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3641 | uint32_t i; |
3642 | |
3643 | clear_msacsr_cause(env); |
3644 | |
3645 | switch (df) { |
3646 | case DF_WORD: |
3647 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3648 | MSA_FLOAT_BINOP(pwx->w[i], div, pws->w[i], pwt->w[i], 32); |
3649 | } |
3650 | break; |
3651 | case DF_DOUBLE: |
3652 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3653 | MSA_FLOAT_BINOP(pwx->d[i], div, pws->d[i], pwt->d[i], 64); |
3654 | } |
3655 | break; |
3656 | default: |
3657 | assert(0); |
3658 | } |
3659 | |
3660 | check_msacsr_cause(env, GETPC()); |
3661 | |
3662 | msa_move_v(pwd, pwx); |
3663 | } |
3664 | |
3665 | #define MSA_FLOAT_MULADD(DEST, ARG1, ARG2, ARG3, NEGATE, BITS) \ |
3666 | do { \ |
3667 | float_status *status = &env->active_tc.msa_fp_status; \ |
3668 | int c; \ |
3669 | \ |
3670 | set_float_exception_flags(0, status); \ |
3671 | DEST = float ## BITS ## _muladd(ARG2, ARG3, ARG1, NEGATE, status); \ |
3672 | c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \ |
3673 | \ |
3674 | if (get_enabled_exceptions(env, c)) { \ |
3675 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
3676 | } \ |
3677 | } while (0) |
3678 | |
3679 | void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3680 | uint32_t ws, uint32_t wt) |
3681 | { |
3682 | wr_t wx, *pwx = &wx; |
3683 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3684 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3685 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3686 | uint32_t i; |
3687 | |
3688 | clear_msacsr_cause(env); |
3689 | |
3690 | switch (df) { |
3691 | case DF_WORD: |
3692 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3693 | MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i], |
3694 | pws->w[i], pwt->w[i], 0, 32); |
3695 | } |
3696 | break; |
3697 | case DF_DOUBLE: |
3698 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3699 | MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i], |
3700 | pws->d[i], pwt->d[i], 0, 64); |
3701 | } |
3702 | break; |
3703 | default: |
3704 | assert(0); |
3705 | } |
3706 | |
3707 | check_msacsr_cause(env, GETPC()); |
3708 | |
3709 | msa_move_v(pwd, pwx); |
3710 | } |
3711 | |
3712 | void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3713 | uint32_t ws, uint32_t wt) |
3714 | { |
3715 | wr_t wx, *pwx = &wx; |
3716 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3717 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3718 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3719 | uint32_t i; |
3720 | |
3721 | clear_msacsr_cause(env); |
3722 | |
3723 | switch (df) { |
3724 | case DF_WORD: |
3725 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3726 | MSA_FLOAT_MULADD(pwx->w[i], pwd->w[i], |
3727 | pws->w[i], pwt->w[i], |
3728 | float_muladd_negate_product, 32); |
3729 | } |
3730 | break; |
3731 | case DF_DOUBLE: |
3732 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3733 | MSA_FLOAT_MULADD(pwx->d[i], pwd->d[i], |
3734 | pws->d[i], pwt->d[i], |
3735 | float_muladd_negate_product, 64); |
3736 | } |
3737 | break; |
3738 | default: |
3739 | assert(0); |
3740 | } |
3741 | |
3742 | check_msacsr_cause(env, GETPC()); |
3743 | |
3744 | msa_move_v(pwd, pwx); |
3745 | } |
3746 | |
3747 | void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3748 | uint32_t ws, uint32_t wt) |
3749 | { |
3750 | wr_t wx, *pwx = &wx; |
3751 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3752 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3753 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3754 | uint32_t i; |
3755 | |
3756 | clear_msacsr_cause(env); |
3757 | |
3758 | switch (df) { |
3759 | case DF_WORD: |
3760 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3761 | MSA_FLOAT_BINOP(pwx->w[i], scalbn, pws->w[i], |
3762 | pwt->w[i] > 0x200 ? 0x200 : |
3763 | pwt->w[i] < -0x200 ? -0x200 : pwt->w[i], |
3764 | 32); |
3765 | } |
3766 | break; |
3767 | case DF_DOUBLE: |
3768 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3769 | MSA_FLOAT_BINOP(pwx->d[i], scalbn, pws->d[i], |
3770 | pwt->d[i] > 0x1000 ? 0x1000 : |
3771 | pwt->d[i] < -0x1000 ? -0x1000 : pwt->d[i], |
3772 | 64); |
3773 | } |
3774 | break; |
3775 | default: |
3776 | assert(0); |
3777 | } |
3778 | |
3779 | check_msacsr_cause(env, GETPC()); |
3780 | |
3781 | msa_move_v(pwd, pwx); |
3782 | } |
3783 | |
3784 | #define MSA_FLOAT_UNOP(DEST, OP, ARG, BITS) \ |
3785 | do { \ |
3786 | float_status *status = &env->active_tc.msa_fp_status; \ |
3787 | int c; \ |
3788 | \ |
3789 | set_float_exception_flags(0, status); \ |
3790 | DEST = float ## BITS ## _ ## OP(ARG, status); \ |
3791 | c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \ |
3792 | \ |
3793 | if (get_enabled_exceptions(env, c)) { \ |
3794 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
3795 | } \ |
3796 | } while (0) |
3797 | |
3798 | void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3799 | uint32_t ws, uint32_t wt) |
3800 | { |
3801 | wr_t wx, *pwx = &wx; |
3802 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3803 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3804 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3805 | uint32_t i; |
3806 | |
3807 | clear_msacsr_cause(env); |
3808 | |
3809 | switch (df) { |
3810 | case DF_WORD: |
3811 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3812 | /* |
3813 | * Half precision floats come in two formats: standard |
3814 | * IEEE and "ARM" format. The latter gains extra exponent |
3815 | * range by omitting the NaN/Inf encodings. |
3816 | */ |
3817 | flag ieee = 1; |
3818 | |
3819 | MSA_FLOAT_BINOP(Lh(pwx, i), from_float32, pws->w[i], ieee, 16); |
3820 | MSA_FLOAT_BINOP(Rh(pwx, i), from_float32, pwt->w[i], ieee, 16); |
3821 | } |
3822 | break; |
3823 | case DF_DOUBLE: |
3824 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3825 | MSA_FLOAT_UNOP(Lw(pwx, i), from_float64, pws->d[i], 32); |
3826 | MSA_FLOAT_UNOP(Rw(pwx, i), from_float64, pwt->d[i], 32); |
3827 | } |
3828 | break; |
3829 | default: |
3830 | assert(0); |
3831 | } |
3832 | |
3833 | check_msacsr_cause(env, GETPC()); |
3834 | msa_move_v(pwd, pwx); |
3835 | } |
3836 | |
3837 | #define MSA_FLOAT_UNOP_XD(DEST, OP, ARG, BITS, XBITS) \ |
3838 | do { \ |
3839 | float_status *status = &env->active_tc.msa_fp_status; \ |
3840 | int c; \ |
3841 | \ |
3842 | set_float_exception_flags(0, status); \ |
3843 | DEST = float ## BITS ## _ ## OP(ARG, status); \ |
3844 | c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \ |
3845 | \ |
3846 | if (get_enabled_exceptions(env, c)) { \ |
3847 | DEST = ((FLOAT_SNAN ## XBITS(status) >> 6) << 6) | c; \ |
3848 | } \ |
3849 | } while (0) |
3850 | |
3851 | void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3852 | uint32_t ws, uint32_t wt) |
3853 | { |
3854 | wr_t wx, *pwx = &wx; |
3855 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3856 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3857 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3858 | uint32_t i; |
3859 | |
3860 | clear_msacsr_cause(env); |
3861 | |
3862 | switch (df) { |
3863 | case DF_WORD: |
3864 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
3865 | MSA_FLOAT_UNOP_XD(Lh(pwx, i), to_q16, pws->w[i], 32, 16); |
3866 | MSA_FLOAT_UNOP_XD(Rh(pwx, i), to_q16, pwt->w[i], 32, 16); |
3867 | } |
3868 | break; |
3869 | case DF_DOUBLE: |
3870 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
3871 | MSA_FLOAT_UNOP_XD(Lw(pwx, i), to_q32, pws->d[i], 64, 32); |
3872 | MSA_FLOAT_UNOP_XD(Rw(pwx, i), to_q32, pwt->d[i], 64, 32); |
3873 | } |
3874 | break; |
3875 | default: |
3876 | assert(0); |
3877 | } |
3878 | |
3879 | check_msacsr_cause(env, GETPC()); |
3880 | |
3881 | msa_move_v(pwd, pwx); |
3882 | } |
3883 | |
3884 | #define NUMBER_QNAN_PAIR(ARG1, ARG2, BITS, STATUS) \ |
3885 | !float ## BITS ## _is_any_nan(ARG1) \ |
3886 | && float ## BITS ## _is_quiet_nan(ARG2, STATUS) |
3887 | |
3888 | #define MSA_FLOAT_MAXOP(DEST, OP, ARG1, ARG2, BITS) \ |
3889 | do { \ |
3890 | float_status *status = &env->active_tc.msa_fp_status; \ |
3891 | int c; \ |
3892 | \ |
3893 | set_float_exception_flags(0, status); \ |
3894 | DEST = float ## BITS ## _ ## OP(ARG1, ARG2, status); \ |
3895 | c = update_msacsr(env, 0, 0); \ |
3896 | \ |
3897 | if (get_enabled_exceptions(env, c)) { \ |
3898 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
3899 | } \ |
3900 | } while (0) |
3901 | |
3902 | #define FMAXMIN_A(F, G, X, _S, _T, BITS, STATUS) \ |
3903 | do { \ |
3904 | uint## BITS ##_t S = _S, T = _T; \ |
3905 | uint## BITS ##_t as, at, xs, xt, xd; \ |
3906 | if (NUMBER_QNAN_PAIR(S, T, BITS, STATUS)) { \ |
3907 | T = S; \ |
3908 | } \ |
3909 | else if (NUMBER_QNAN_PAIR(T, S, BITS, STATUS)) { \ |
3910 | S = T; \ |
3911 | } \ |
3912 | as = float## BITS ##_abs(S); \ |
3913 | at = float## BITS ##_abs(T); \ |
3914 | MSA_FLOAT_MAXOP(xs, F, S, T, BITS); \ |
3915 | MSA_FLOAT_MAXOP(xt, G, S, T, BITS); \ |
3916 | MSA_FLOAT_MAXOP(xd, F, as, at, BITS); \ |
3917 | X = (as == at || xd == float## BITS ##_abs(xs)) ? xs : xt; \ |
3918 | } while (0) |
3919 | |
3920 | void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3921 | uint32_t ws, uint32_t wt) |
3922 | { |
3923 | float_status *status = &env->active_tc.msa_fp_status; |
3924 | wr_t wx, *pwx = &wx; |
3925 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
3926 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
3927 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
3928 | |
3929 | clear_msacsr_cause(env); |
3930 | |
3931 | if (df == DF_WORD) { |
3932 | |
3933 | if (NUMBER_QNAN_PAIR(pws->w[0], pwt->w[0], 32, status)) { |
3934 | MSA_FLOAT_MAXOP(pwx->w[0], min, pws->w[0], pws->w[0], 32); |
3935 | } else if (NUMBER_QNAN_PAIR(pwt->w[0], pws->w[0], 32, status)) { |
3936 | MSA_FLOAT_MAXOP(pwx->w[0], min, pwt->w[0], pwt->w[0], 32); |
3937 | } else { |
3938 | MSA_FLOAT_MAXOP(pwx->w[0], min, pws->w[0], pwt->w[0], 32); |
3939 | } |
3940 | |
3941 | if (NUMBER_QNAN_PAIR(pws->w[1], pwt->w[1], 32, status)) { |
3942 | MSA_FLOAT_MAXOP(pwx->w[1], min, pws->w[1], pws->w[1], 32); |
3943 | } else if (NUMBER_QNAN_PAIR(pwt->w[1], pws->w[1], 32, status)) { |
3944 | MSA_FLOAT_MAXOP(pwx->w[1], min, pwt->w[1], pwt->w[1], 32); |
3945 | } else { |
3946 | MSA_FLOAT_MAXOP(pwx->w[1], min, pws->w[1], pwt->w[1], 32); |
3947 | } |
3948 | |
3949 | if (NUMBER_QNAN_PAIR(pws->w[2], pwt->w[2], 32, status)) { |
3950 | MSA_FLOAT_MAXOP(pwx->w[2], min, pws->w[2], pws->w[2], 32); |
3951 | } else if (NUMBER_QNAN_PAIR(pwt->w[2], pws->w[2], 32, status)) { |
3952 | MSA_FLOAT_MAXOP(pwx->w[2], min, pwt->w[2], pwt->w[2], 32); |
3953 | } else { |
3954 | MSA_FLOAT_MAXOP(pwx->w[2], min, pws->w[2], pwt->w[2], 32); |
3955 | } |
3956 | |
3957 | if (NUMBER_QNAN_PAIR(pws->w[3], pwt->w[3], 32, status)) { |
3958 | MSA_FLOAT_MAXOP(pwx->w[3], min, pws->w[3], pws->w[3], 32); |
3959 | } else if (NUMBER_QNAN_PAIR(pwt->w[3], pws->w[3], 32, status)) { |
3960 | MSA_FLOAT_MAXOP(pwx->w[3], min, pwt->w[3], pwt->w[3], 32); |
3961 | } else { |
3962 | MSA_FLOAT_MAXOP(pwx->w[3], min, pws->w[3], pwt->w[3], 32); |
3963 | } |
3964 | |
3965 | } else if (df == DF_DOUBLE) { |
3966 | |
3967 | if (NUMBER_QNAN_PAIR(pws->d[0], pwt->d[0], 64, status)) { |
3968 | MSA_FLOAT_MAXOP(pwx->d[0], min, pws->d[0], pws->d[0], 64); |
3969 | } else if (NUMBER_QNAN_PAIR(pwt->d[0], pws->d[0], 64, status)) { |
3970 | MSA_FLOAT_MAXOP(pwx->d[0], min, pwt->d[0], pwt->d[0], 64); |
3971 | } else { |
3972 | MSA_FLOAT_MAXOP(pwx->d[0], min, pws->d[0], pwt->d[0], 64); |
3973 | } |
3974 | |
3975 | if (NUMBER_QNAN_PAIR(pws->d[1], pwt->d[1], 64, status)) { |
3976 | MSA_FLOAT_MAXOP(pwx->d[1], min, pws->d[1], pws->d[1], 64); |
3977 | } else if (NUMBER_QNAN_PAIR(pwt->d[1], pws->d[1], 64, status)) { |
3978 | MSA_FLOAT_MAXOP(pwx->d[1], min, pwt->d[1], pwt->d[1], 64); |
3979 | } else { |
3980 | MSA_FLOAT_MAXOP(pwx->d[1], min, pws->d[1], pwt->d[1], 64); |
3981 | } |
3982 | |
3983 | } else { |
3984 | |
3985 | assert(0); |
3986 | |
3987 | } |
3988 | |
3989 | check_msacsr_cause(env, GETPC()); |
3990 | |
3991 | msa_move_v(pwd, pwx); |
3992 | } |
3993 | |
3994 | void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
3995 | uint32_t ws, uint32_t wt) |
3996 | { |
3997 | float_status *status = &env->active_tc.msa_fp_status; |
3998 | wr_t wx, *pwx = &wx; |
3999 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4000 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4001 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
4002 | |
4003 | clear_msacsr_cause(env); |
4004 | |
4005 | if (df == DF_WORD) { |
4006 | FMAXMIN_A(min, max, pwx->w[0], pws->w[0], pwt->w[0], 32, status); |
4007 | FMAXMIN_A(min, max, pwx->w[1], pws->w[1], pwt->w[1], 32, status); |
4008 | FMAXMIN_A(min, max, pwx->w[2], pws->w[2], pwt->w[2], 32, status); |
4009 | FMAXMIN_A(min, max, pwx->w[3], pws->w[3], pwt->w[3], 32, status); |
4010 | } else if (df == DF_DOUBLE) { |
4011 | FMAXMIN_A(min, max, pwx->d[0], pws->d[0], pwt->d[0], 64, status); |
4012 | FMAXMIN_A(min, max, pwx->d[1], pws->d[1], pwt->d[1], 64, status); |
4013 | } else { |
4014 | assert(0); |
4015 | } |
4016 | |
4017 | check_msacsr_cause(env, GETPC()); |
4018 | |
4019 | msa_move_v(pwd, pwx); |
4020 | } |
4021 | |
4022 | void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4023 | uint32_t ws, uint32_t wt) |
4024 | { |
4025 | float_status *status = &env->active_tc.msa_fp_status; |
4026 | wr_t wx, *pwx = &wx; |
4027 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4028 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4029 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
4030 | |
4031 | clear_msacsr_cause(env); |
4032 | |
4033 | if (df == DF_WORD) { |
4034 | |
4035 | if (NUMBER_QNAN_PAIR(pws->w[0], pwt->w[0], 32, status)) { |
4036 | MSA_FLOAT_MAXOP(pwx->w[0], max, pws->w[0], pws->w[0], 32); |
4037 | } else if (NUMBER_QNAN_PAIR(pwt->w[0], pws->w[0], 32, status)) { |
4038 | MSA_FLOAT_MAXOP(pwx->w[0], max, pwt->w[0], pwt->w[0], 32); |
4039 | } else { |
4040 | MSA_FLOAT_MAXOP(pwx->w[0], max, pws->w[0], pwt->w[0], 32); |
4041 | } |
4042 | |
4043 | if (NUMBER_QNAN_PAIR(pws->w[1], pwt->w[1], 32, status)) { |
4044 | MSA_FLOAT_MAXOP(pwx->w[1], max, pws->w[1], pws->w[1], 32); |
4045 | } else if (NUMBER_QNAN_PAIR(pwt->w[1], pws->w[1], 32, status)) { |
4046 | MSA_FLOAT_MAXOP(pwx->w[1], max, pwt->w[1], pwt->w[1], 32); |
4047 | } else { |
4048 | MSA_FLOAT_MAXOP(pwx->w[1], max, pws->w[1], pwt->w[1], 32); |
4049 | } |
4050 | |
4051 | if (NUMBER_QNAN_PAIR(pws->w[2], pwt->w[2], 32, status)) { |
4052 | MSA_FLOAT_MAXOP(pwx->w[2], max, pws->w[2], pws->w[2], 32); |
4053 | } else if (NUMBER_QNAN_PAIR(pwt->w[2], pws->w[2], 32, status)) { |
4054 | MSA_FLOAT_MAXOP(pwx->w[2], max, pwt->w[2], pwt->w[2], 32); |
4055 | } else { |
4056 | MSA_FLOAT_MAXOP(pwx->w[2], max, pws->w[2], pwt->w[2], 32); |
4057 | } |
4058 | |
4059 | if (NUMBER_QNAN_PAIR(pws->w[3], pwt->w[3], 32, status)) { |
4060 | MSA_FLOAT_MAXOP(pwx->w[3], max, pws->w[3], pws->w[3], 32); |
4061 | } else if (NUMBER_QNAN_PAIR(pwt->w[3], pws->w[3], 32, status)) { |
4062 | MSA_FLOAT_MAXOP(pwx->w[3], max, pwt->w[3], pwt->w[3], 32); |
4063 | } else { |
4064 | MSA_FLOAT_MAXOP(pwx->w[3], max, pws->w[3], pwt->w[3], 32); |
4065 | } |
4066 | |
4067 | } else if (df == DF_DOUBLE) { |
4068 | |
4069 | if (NUMBER_QNAN_PAIR(pws->d[0], pwt->d[0], 64, status)) { |
4070 | MSA_FLOAT_MAXOP(pwx->d[0], max, pws->d[0], pws->d[0], 64); |
4071 | } else if (NUMBER_QNAN_PAIR(pwt->d[0], pws->d[0], 64, status)) { |
4072 | MSA_FLOAT_MAXOP(pwx->d[0], max, pwt->d[0], pwt->d[0], 64); |
4073 | } else { |
4074 | MSA_FLOAT_MAXOP(pwx->d[0], max, pws->d[0], pwt->d[0], 64); |
4075 | } |
4076 | |
4077 | if (NUMBER_QNAN_PAIR(pws->d[1], pwt->d[1], 64, status)) { |
4078 | MSA_FLOAT_MAXOP(pwx->d[1], max, pws->d[1], pws->d[1], 64); |
4079 | } else if (NUMBER_QNAN_PAIR(pwt->d[1], pws->d[1], 64, status)) { |
4080 | MSA_FLOAT_MAXOP(pwx->d[1], max, pwt->d[1], pwt->d[1], 64); |
4081 | } else { |
4082 | MSA_FLOAT_MAXOP(pwx->d[1], max, pws->d[1], pwt->d[1], 64); |
4083 | } |
4084 | |
4085 | } else { |
4086 | |
4087 | assert(0); |
4088 | |
4089 | } |
4090 | |
4091 | check_msacsr_cause(env, GETPC()); |
4092 | |
4093 | msa_move_v(pwd, pwx); |
4094 | } |
4095 | |
4096 | void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4097 | uint32_t ws, uint32_t wt) |
4098 | { |
4099 | float_status *status = &env->active_tc.msa_fp_status; |
4100 | wr_t wx, *pwx = &wx; |
4101 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4102 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4103 | wr_t *pwt = &(env->active_fpu.fpr[wt].wr); |
4104 | |
4105 | clear_msacsr_cause(env); |
4106 | |
4107 | if (df == DF_WORD) { |
4108 | FMAXMIN_A(max, min, pwx->w[0], pws->w[0], pwt->w[0], 32, status); |
4109 | FMAXMIN_A(max, min, pwx->w[1], pws->w[1], pwt->w[1], 32, status); |
4110 | FMAXMIN_A(max, min, pwx->w[2], pws->w[2], pwt->w[2], 32, status); |
4111 | FMAXMIN_A(max, min, pwx->w[3], pws->w[3], pwt->w[3], 32, status); |
4112 | } else if (df == DF_DOUBLE) { |
4113 | FMAXMIN_A(max, min, pwx->d[0], pws->d[0], pwt->d[0], 64, status); |
4114 | FMAXMIN_A(max, min, pwx->d[1], pws->d[1], pwt->d[1], 64, status); |
4115 | } else { |
4116 | assert(0); |
4117 | } |
4118 | |
4119 | check_msacsr_cause(env, GETPC()); |
4120 | |
4121 | msa_move_v(pwd, pwx); |
4122 | } |
4123 | |
4124 | void helper_msa_fclass_df(CPUMIPSState *env, uint32_t df, |
4125 | uint32_t wd, uint32_t ws) |
4126 | { |
4127 | float_status *status = &env->active_tc.msa_fp_status; |
4128 | |
4129 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4130 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4131 | if (df == DF_WORD) { |
4132 | pwd->w[0] = float_class_s(pws->w[0], status); |
4133 | pwd->w[1] = float_class_s(pws->w[1], status); |
4134 | pwd->w[2] = float_class_s(pws->w[2], status); |
4135 | pwd->w[3] = float_class_s(pws->w[3], status); |
4136 | } else if (df == DF_DOUBLE) { |
4137 | pwd->d[0] = float_class_d(pws->d[0], status); |
4138 | pwd->d[1] = float_class_d(pws->d[1], status); |
4139 | } else { |
4140 | assert(0); |
4141 | } |
4142 | } |
4143 | |
4144 | #define MSA_FLOAT_UNOP0(DEST, OP, ARG, BITS) \ |
4145 | do { \ |
4146 | float_status *status = &env->active_tc.msa_fp_status; \ |
4147 | int c; \ |
4148 | \ |
4149 | set_float_exception_flags(0, status); \ |
4150 | DEST = float ## BITS ## _ ## OP(ARG, status); \ |
4151 | c = update_msacsr(env, CLEAR_FS_UNDERFLOW, 0); \ |
4152 | \ |
4153 | if (get_enabled_exceptions(env, c)) { \ |
4154 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
4155 | } else if (float ## BITS ## _is_any_nan(ARG)) { \ |
4156 | DEST = 0; \ |
4157 | } \ |
4158 | } while (0) |
4159 | |
4160 | void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4161 | uint32_t ws) |
4162 | { |
4163 | wr_t wx, *pwx = &wx; |
4164 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4165 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4166 | uint32_t i; |
4167 | |
4168 | clear_msacsr_cause(env); |
4169 | |
4170 | switch (df) { |
4171 | case DF_WORD: |
4172 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4173 | MSA_FLOAT_UNOP0(pwx->w[i], to_int32_round_to_zero, pws->w[i], 32); |
4174 | } |
4175 | break; |
4176 | case DF_DOUBLE: |
4177 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4178 | MSA_FLOAT_UNOP0(pwx->d[i], to_int64_round_to_zero, pws->d[i], 64); |
4179 | } |
4180 | break; |
4181 | default: |
4182 | assert(0); |
4183 | } |
4184 | |
4185 | check_msacsr_cause(env, GETPC()); |
4186 | |
4187 | msa_move_v(pwd, pwx); |
4188 | } |
4189 | |
4190 | void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4191 | uint32_t ws) |
4192 | { |
4193 | wr_t wx, *pwx = &wx; |
4194 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4195 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4196 | uint32_t i; |
4197 | |
4198 | clear_msacsr_cause(env); |
4199 | |
4200 | switch (df) { |
4201 | case DF_WORD: |
4202 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4203 | MSA_FLOAT_UNOP0(pwx->w[i], to_uint32_round_to_zero, pws->w[i], 32); |
4204 | } |
4205 | break; |
4206 | case DF_DOUBLE: |
4207 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4208 | MSA_FLOAT_UNOP0(pwx->d[i], to_uint64_round_to_zero, pws->d[i], 64); |
4209 | } |
4210 | break; |
4211 | default: |
4212 | assert(0); |
4213 | } |
4214 | |
4215 | check_msacsr_cause(env, GETPC()); |
4216 | |
4217 | msa_move_v(pwd, pwx); |
4218 | } |
4219 | |
4220 | void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4221 | uint32_t ws) |
4222 | { |
4223 | wr_t wx, *pwx = &wx; |
4224 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4225 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4226 | uint32_t i; |
4227 | |
4228 | clear_msacsr_cause(env); |
4229 | |
4230 | switch (df) { |
4231 | case DF_WORD: |
4232 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4233 | MSA_FLOAT_UNOP(pwx->w[i], sqrt, pws->w[i], 32); |
4234 | } |
4235 | break; |
4236 | case DF_DOUBLE: |
4237 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4238 | MSA_FLOAT_UNOP(pwx->d[i], sqrt, pws->d[i], 64); |
4239 | } |
4240 | break; |
4241 | default: |
4242 | assert(0); |
4243 | } |
4244 | |
4245 | check_msacsr_cause(env, GETPC()); |
4246 | |
4247 | msa_move_v(pwd, pwx); |
4248 | } |
4249 | |
4250 | #define MSA_FLOAT_RECIPROCAL(DEST, ARG, BITS) \ |
4251 | do { \ |
4252 | float_status *status = &env->active_tc.msa_fp_status; \ |
4253 | int c; \ |
4254 | \ |
4255 | set_float_exception_flags(0, status); \ |
4256 | DEST = float ## BITS ## _ ## div(FLOAT_ONE ## BITS, ARG, status); \ |
4257 | c = update_msacsr(env, float ## BITS ## _is_infinity(ARG) || \ |
4258 | float ## BITS ## _is_quiet_nan(DEST, status) ? \ |
4259 | 0 : RECIPROCAL_INEXACT, \ |
4260 | IS_DENORMAL(DEST, BITS)); \ |
4261 | \ |
4262 | if (get_enabled_exceptions(env, c)) { \ |
4263 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
4264 | } \ |
4265 | } while (0) |
4266 | |
4267 | void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4268 | uint32_t ws) |
4269 | { |
4270 | wr_t wx, *pwx = &wx; |
4271 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4272 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4273 | uint32_t i; |
4274 | |
4275 | clear_msacsr_cause(env); |
4276 | |
4277 | switch (df) { |
4278 | case DF_WORD: |
4279 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4280 | MSA_FLOAT_RECIPROCAL(pwx->w[i], float32_sqrt(pws->w[i], |
4281 | &env->active_tc.msa_fp_status), 32); |
4282 | } |
4283 | break; |
4284 | case DF_DOUBLE: |
4285 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4286 | MSA_FLOAT_RECIPROCAL(pwx->d[i], float64_sqrt(pws->d[i], |
4287 | &env->active_tc.msa_fp_status), 64); |
4288 | } |
4289 | break; |
4290 | default: |
4291 | assert(0); |
4292 | } |
4293 | |
4294 | check_msacsr_cause(env, GETPC()); |
4295 | |
4296 | msa_move_v(pwd, pwx); |
4297 | } |
4298 | |
4299 | void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4300 | uint32_t ws) |
4301 | { |
4302 | wr_t wx, *pwx = &wx; |
4303 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4304 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4305 | uint32_t i; |
4306 | |
4307 | clear_msacsr_cause(env); |
4308 | |
4309 | switch (df) { |
4310 | case DF_WORD: |
4311 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4312 | MSA_FLOAT_RECIPROCAL(pwx->w[i], pws->w[i], 32); |
4313 | } |
4314 | break; |
4315 | case DF_DOUBLE: |
4316 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4317 | MSA_FLOAT_RECIPROCAL(pwx->d[i], pws->d[i], 64); |
4318 | } |
4319 | break; |
4320 | default: |
4321 | assert(0); |
4322 | } |
4323 | |
4324 | check_msacsr_cause(env, GETPC()); |
4325 | |
4326 | msa_move_v(pwd, pwx); |
4327 | } |
4328 | |
4329 | void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4330 | uint32_t ws) |
4331 | { |
4332 | wr_t wx, *pwx = &wx; |
4333 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4334 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4335 | uint32_t i; |
4336 | |
4337 | clear_msacsr_cause(env); |
4338 | |
4339 | switch (df) { |
4340 | case DF_WORD: |
4341 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4342 | MSA_FLOAT_UNOP(pwx->w[i], round_to_int, pws->w[i], 32); |
4343 | } |
4344 | break; |
4345 | case DF_DOUBLE: |
4346 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4347 | MSA_FLOAT_UNOP(pwx->d[i], round_to_int, pws->d[i], 64); |
4348 | } |
4349 | break; |
4350 | default: |
4351 | assert(0); |
4352 | } |
4353 | |
4354 | check_msacsr_cause(env, GETPC()); |
4355 | |
4356 | msa_move_v(pwd, pwx); |
4357 | } |
4358 | |
4359 | #define MSA_FLOAT_LOGB(DEST, ARG, BITS) \ |
4360 | do { \ |
4361 | float_status *status = &env->active_tc.msa_fp_status; \ |
4362 | int c; \ |
4363 | \ |
4364 | set_float_exception_flags(0, status); \ |
4365 | set_float_rounding_mode(float_round_down, status); \ |
4366 | DEST = float ## BITS ## _ ## log2(ARG, status); \ |
4367 | DEST = float ## BITS ## _ ## round_to_int(DEST, status); \ |
4368 | set_float_rounding_mode(ieee_rm[(env->active_tc.msacsr & \ |
4369 | MSACSR_RM_MASK) >> MSACSR_RM], \ |
4370 | status); \ |
4371 | \ |
4372 | set_float_exception_flags(get_float_exception_flags(status) & \ |
4373 | (~float_flag_inexact), \ |
4374 | status); \ |
4375 | \ |
4376 | c = update_msacsr(env, 0, IS_DENORMAL(DEST, BITS)); \ |
4377 | \ |
4378 | if (get_enabled_exceptions(env, c)) { \ |
4379 | DEST = ((FLOAT_SNAN ## BITS(status) >> 6) << 6) | c; \ |
4380 | } \ |
4381 | } while (0) |
4382 | |
4383 | void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4384 | uint32_t ws) |
4385 | { |
4386 | wr_t wx, *pwx = &wx; |
4387 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4388 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4389 | uint32_t i; |
4390 | |
4391 | clear_msacsr_cause(env); |
4392 | |
4393 | switch (df) { |
4394 | case DF_WORD: |
4395 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4396 | MSA_FLOAT_LOGB(pwx->w[i], pws->w[i], 32); |
4397 | } |
4398 | break; |
4399 | case DF_DOUBLE: |
4400 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4401 | MSA_FLOAT_LOGB(pwx->d[i], pws->d[i], 64); |
4402 | } |
4403 | break; |
4404 | default: |
4405 | assert(0); |
4406 | } |
4407 | |
4408 | check_msacsr_cause(env, GETPC()); |
4409 | |
4410 | msa_move_v(pwd, pwx); |
4411 | } |
4412 | |
4413 | void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4414 | uint32_t ws) |
4415 | { |
4416 | wr_t wx, *pwx = &wx; |
4417 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4418 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4419 | uint32_t i; |
4420 | |
4421 | clear_msacsr_cause(env); |
4422 | |
4423 | switch (df) { |
4424 | case DF_WORD: |
4425 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4426 | /* |
4427 | * Half precision floats come in two formats: standard |
4428 | * IEEE and "ARM" format. The latter gains extra exponent |
4429 | * range by omitting the NaN/Inf encodings. |
4430 | */ |
4431 | flag ieee = 1; |
4432 | |
4433 | MSA_FLOAT_BINOP(pwx->w[i], from_float16, Lh(pws, i), ieee, 32); |
4434 | } |
4435 | break; |
4436 | case DF_DOUBLE: |
4437 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4438 | MSA_FLOAT_UNOP(pwx->d[i], from_float32, Lw(pws, i), 64); |
4439 | } |
4440 | break; |
4441 | default: |
4442 | assert(0); |
4443 | } |
4444 | |
4445 | check_msacsr_cause(env, GETPC()); |
4446 | msa_move_v(pwd, pwx); |
4447 | } |
4448 | |
4449 | void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4450 | uint32_t ws) |
4451 | { |
4452 | wr_t wx, *pwx = &wx; |
4453 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4454 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4455 | uint32_t i; |
4456 | |
4457 | clear_msacsr_cause(env); |
4458 | |
4459 | switch (df) { |
4460 | case DF_WORD: |
4461 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4462 | /* |
4463 | * Half precision floats come in two formats: standard |
4464 | * IEEE and "ARM" format. The latter gains extra exponent |
4465 | * range by omitting the NaN/Inf encodings. |
4466 | */ |
4467 | flag ieee = 1; |
4468 | |
4469 | MSA_FLOAT_BINOP(pwx->w[i], from_float16, Rh(pws, i), ieee, 32); |
4470 | } |
4471 | break; |
4472 | case DF_DOUBLE: |
4473 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4474 | MSA_FLOAT_UNOP(pwx->d[i], from_float32, Rw(pws, i), 64); |
4475 | } |
4476 | break; |
4477 | default: |
4478 | assert(0); |
4479 | } |
4480 | |
4481 | check_msacsr_cause(env, GETPC()); |
4482 | msa_move_v(pwd, pwx); |
4483 | } |
4484 | |
4485 | void helper_msa_ffql_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4486 | uint32_t ws) |
4487 | { |
4488 | wr_t wx, *pwx = &wx; |
4489 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4490 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4491 | uint32_t i; |
4492 | |
4493 | switch (df) { |
4494 | case DF_WORD: |
4495 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4496 | MSA_FLOAT_UNOP(pwx->w[i], from_q16, Lh(pws, i), 32); |
4497 | } |
4498 | break; |
4499 | case DF_DOUBLE: |
4500 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4501 | MSA_FLOAT_UNOP(pwx->d[i], from_q32, Lw(pws, i), 64); |
4502 | } |
4503 | break; |
4504 | default: |
4505 | assert(0); |
4506 | } |
4507 | |
4508 | msa_move_v(pwd, pwx); |
4509 | } |
4510 | |
4511 | void helper_msa_ffqr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4512 | uint32_t ws) |
4513 | { |
4514 | wr_t wx, *pwx = &wx; |
4515 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4516 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4517 | uint32_t i; |
4518 | |
4519 | switch (df) { |
4520 | case DF_WORD: |
4521 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4522 | MSA_FLOAT_UNOP(pwx->w[i], from_q16, Rh(pws, i), 32); |
4523 | } |
4524 | break; |
4525 | case DF_DOUBLE: |
4526 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4527 | MSA_FLOAT_UNOP(pwx->d[i], from_q32, Rw(pws, i), 64); |
4528 | } |
4529 | break; |
4530 | default: |
4531 | assert(0); |
4532 | } |
4533 | |
4534 | msa_move_v(pwd, pwx); |
4535 | } |
4536 | |
4537 | void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4538 | uint32_t ws) |
4539 | { |
4540 | wr_t wx, *pwx = &wx; |
4541 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4542 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4543 | uint32_t i; |
4544 | |
4545 | clear_msacsr_cause(env); |
4546 | |
4547 | switch (df) { |
4548 | case DF_WORD: |
4549 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4550 | MSA_FLOAT_UNOP0(pwx->w[i], to_int32, pws->w[i], 32); |
4551 | } |
4552 | break; |
4553 | case DF_DOUBLE: |
4554 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4555 | MSA_FLOAT_UNOP0(pwx->d[i], to_int64, pws->d[i], 64); |
4556 | } |
4557 | break; |
4558 | default: |
4559 | assert(0); |
4560 | } |
4561 | |
4562 | check_msacsr_cause(env, GETPC()); |
4563 | |
4564 | msa_move_v(pwd, pwx); |
4565 | } |
4566 | |
4567 | void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4568 | uint32_t ws) |
4569 | { |
4570 | wr_t wx, *pwx = &wx; |
4571 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4572 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4573 | uint32_t i; |
4574 | |
4575 | clear_msacsr_cause(env); |
4576 | |
4577 | switch (df) { |
4578 | case DF_WORD: |
4579 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4580 | MSA_FLOAT_UNOP0(pwx->w[i], to_uint32, pws->w[i], 32); |
4581 | } |
4582 | break; |
4583 | case DF_DOUBLE: |
4584 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4585 | MSA_FLOAT_UNOP0(pwx->d[i], to_uint64, pws->d[i], 64); |
4586 | } |
4587 | break; |
4588 | default: |
4589 | assert(0); |
4590 | } |
4591 | |
4592 | check_msacsr_cause(env, GETPC()); |
4593 | |
4594 | msa_move_v(pwd, pwx); |
4595 | } |
4596 | |
4597 | #define float32_from_int32 int32_to_float32 |
4598 | #define float32_from_uint32 uint32_to_float32 |
4599 | |
4600 | #define float64_from_int64 int64_to_float64 |
4601 | #define float64_from_uint64 uint64_to_float64 |
4602 | |
4603 | void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4604 | uint32_t ws) |
4605 | { |
4606 | wr_t wx, *pwx = &wx; |
4607 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4608 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4609 | uint32_t i; |
4610 | |
4611 | clear_msacsr_cause(env); |
4612 | |
4613 | switch (df) { |
4614 | case DF_WORD: |
4615 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4616 | MSA_FLOAT_UNOP(pwx->w[i], from_int32, pws->w[i], 32); |
4617 | } |
4618 | break; |
4619 | case DF_DOUBLE: |
4620 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4621 | MSA_FLOAT_UNOP(pwx->d[i], from_int64, pws->d[i], 64); |
4622 | } |
4623 | break; |
4624 | default: |
4625 | assert(0); |
4626 | } |
4627 | |
4628 | check_msacsr_cause(env, GETPC()); |
4629 | |
4630 | msa_move_v(pwd, pwx); |
4631 | } |
4632 | |
4633 | void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, |
4634 | uint32_t ws) |
4635 | { |
4636 | wr_t wx, *pwx = &wx; |
4637 | wr_t *pwd = &(env->active_fpu.fpr[wd].wr); |
4638 | wr_t *pws = &(env->active_fpu.fpr[ws].wr); |
4639 | uint32_t i; |
4640 | |
4641 | clear_msacsr_cause(env); |
4642 | |
4643 | switch (df) { |
4644 | case DF_WORD: |
4645 | for (i = 0; i < DF_ELEMENTS(DF_WORD); i++) { |
4646 | MSA_FLOAT_UNOP(pwx->w[i], from_uint32, pws->w[i], 32); |
4647 | } |
4648 | break; |
4649 | case DF_DOUBLE: |
4650 | for (i = 0; i < DF_ELEMENTS(DF_DOUBLE); i++) { |
4651 | MSA_FLOAT_UNOP(pwx->d[i], from_uint64, pws->d[i], 64); |
4652 | } |
4653 | break; |
4654 | default: |
4655 | assert(0); |
4656 | } |
4657 | |
4658 | check_msacsr_cause(env, GETPC()); |
4659 | |
4660 | msa_move_v(pwd, pwx); |
4661 | } |
4662 | |