1/*
2 * MIPS emulation helpers for qemu.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include "qemu/osdep.h"
20#include "qemu/main-loop.h"
21#include "cpu.h"
22#include "internal.h"
23#include "qemu/host-utils.h"
24#include "exec/helper-proto.h"
25#include "exec/exec-all.h"
26#include "exec/cpu_ldst.h"
27#include "exec/memop.h"
28#include "sysemu/kvm.h"
29#include "fpu/softfloat.h"
30
31/*****************************************************************************/
32/* Exceptions processing helpers */
33
34void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
35 int error_code)
36{
37 do_raise_exception_err(env, exception, error_code, 0);
38}
39
40void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
41{
42 do_raise_exception(env, exception, GETPC());
43}
44
45void helper_raise_exception_debug(CPUMIPSState *env)
46{
47 do_raise_exception(env, EXCP_DEBUG, 0);
48}
49
50static void raise_exception(CPUMIPSState *env, uint32_t exception)
51{
52 do_raise_exception(env, exception, 0);
53}
54
55#if defined(CONFIG_USER_ONLY)
56#define HELPER_LD(name, insn, type) \
57static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
58 int mem_idx, uintptr_t retaddr) \
59{ \
60 return (type) cpu_##insn##_data_ra(env, addr, retaddr); \
61}
62#else
63#define HELPER_LD(name, insn, type) \
64static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
65 int mem_idx, uintptr_t retaddr) \
66{ \
67 switch (mem_idx) \
68 { \
69 case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
70 case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
71 default: \
72 case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \
73 case 3: return (type) cpu_##insn##_error_ra(env, addr, retaddr); \
74 } \
75}
76#endif
77HELPER_LD(lw, ldl, int32_t)
78#if defined(TARGET_MIPS64)
79HELPER_LD(ld, ldq, int64_t)
80#endif
81#undef HELPER_LD
82
83#if defined(CONFIG_USER_ONLY)
84#define HELPER_ST(name, insn, type) \
85static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
86 type val, int mem_idx, uintptr_t retaddr) \
87{ \
88 cpu_##insn##_data_ra(env, addr, val, retaddr); \
89}
90#else
91#define HELPER_ST(name, insn, type) \
92static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
93 type val, int mem_idx, uintptr_t retaddr) \
94{ \
95 switch (mem_idx) \
96 { \
97 case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
98 case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
99 default: \
100 case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
101 case 3: \
102 cpu_##insn##_error_ra(env, addr, val, retaddr); \
103 break; \
104 } \
105}
106#endif
107HELPER_ST(sb, stb, uint8_t)
108HELPER_ST(sw, stl, uint32_t)
109#if defined(TARGET_MIPS64)
110HELPER_ST(sd, stq, uint64_t)
111#endif
112#undef HELPER_ST
113
114/* 64 bits arithmetic for 32 bits hosts */
115static inline uint64_t get_HILO(CPUMIPSState *env)
116{
117 return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
118}
119
120static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
121{
122 env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
123 return env->active_tc.HI[0] = (int32_t)(HILO >> 32);
124}
125
126static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
127{
128 target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
129 env->active_tc.HI[0] = (int32_t)(HILO >> 32);
130 return tmp;
131}
132
133/* Multiplication variants of the vr54xx. */
134target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
135 target_ulong arg2)
136{
137 return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
138 (int64_t)(int32_t)arg2));
139}
140
141target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
142 target_ulong arg2)
143{
144 return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
145 (uint64_t)(uint32_t)arg2);
146}
147
148target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
149 target_ulong arg2)
150{
151 return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
152 (int64_t)(int32_t)arg2);
153}
154
155target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
156 target_ulong arg2)
157{
158 return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
159 (int64_t)(int32_t)arg2);
160}
161
162target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
163 target_ulong arg2)
164{
165 return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
166 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
167}
168
169target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
170 target_ulong arg2)
171{
172 return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
173 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
174}
175
176target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
177 target_ulong arg2)
178{
179 return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
180 (int64_t)(int32_t)arg2);
181}
182
183target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
184 target_ulong arg2)
185{
186 return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
187 (int64_t)(int32_t)arg2);
188}
189
190target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
191 target_ulong arg2)
192{
193 return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
194 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
195}
196
197target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
198 target_ulong arg2)
199{
200 return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
201 (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
202}
203
204target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
205 target_ulong arg2)
206{
207 return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
208}
209
210target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
211 target_ulong arg2)
212{
213 return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
214 (uint64_t)(uint32_t)arg2);
215}
216
217target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
218 target_ulong arg2)
219{
220 return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
221 (int64_t)(int32_t)arg2);
222}
223
224target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
225 target_ulong arg2)
226{
227 return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
228 (uint64_t)(uint32_t)arg2);
229}
230
231static inline target_ulong bitswap(target_ulong v)
232{
233 v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
234 ((v & (target_ulong)0x5555555555555555ULL) << 1);
235 v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
236 ((v & (target_ulong)0x3333333333333333ULL) << 2);
237 v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
238 ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
239 return v;
240}
241
242#ifdef TARGET_MIPS64
243target_ulong helper_dbitswap(target_ulong rt)
244{
245 return bitswap(rt);
246}
247#endif
248
249target_ulong helper_bitswap(target_ulong rt)
250{
251 return (int32_t)bitswap(rt);
252}
253
254target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx,
255 uint32_t stripe)
256{
257 int i;
258 uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff);
259 uint64_t tmp1 = tmp0;
260 for (i = 0; i <= 46; i++) {
261 int s;
262 if (i & 0x8) {
263 s = shift;
264 } else {
265 s = shiftx;
266 }
267
268 if (stripe != 0 && !(i & 0x4)) {
269 s = ~s;
270 }
271 if (s & 0x10) {
272 if (tmp0 & (1LL << (i + 16))) {
273 tmp1 |= 1LL << i;
274 } else {
275 tmp1 &= ~(1LL << i);
276 }
277 }
278 }
279
280 uint64_t tmp2 = tmp1;
281 for (i = 0; i <= 38; i++) {
282 int s;
283 if (i & 0x4) {
284 s = shift;
285 } else {
286 s = shiftx;
287 }
288
289 if (s & 0x8) {
290 if (tmp1 & (1LL << (i + 8))) {
291 tmp2 |= 1LL << i;
292 } else {
293 tmp2 &= ~(1LL << i);
294 }
295 }
296 }
297
298 uint64_t tmp3 = tmp2;
299 for (i = 0; i <= 34; i++) {
300 int s;
301 if (i & 0x2) {
302 s = shift;
303 } else {
304 s = shiftx;
305 }
306 if (s & 0x4) {
307 if (tmp2 & (1LL << (i + 4))) {
308 tmp3 |= 1LL << i;
309 } else {
310 tmp3 &= ~(1LL << i);
311 }
312 }
313 }
314
315 uint64_t tmp4 = tmp3;
316 for (i = 0; i <= 32; i++) {
317 int s;
318 if (i & 0x1) {
319 s = shift;
320 } else {
321 s = shiftx;
322 }
323 if (s & 0x2) {
324 if (tmp3 & (1LL << (i + 2))) {
325 tmp4 |= 1LL << i;
326 } else {
327 tmp4 &= ~(1LL << i);
328 }
329 }
330 }
331
332 uint64_t tmp5 = tmp4;
333 for (i = 0; i <= 31; i++) {
334 int s;
335 s = shift;
336 if (s & 0x1) {
337 if (tmp4 & (1LL << (i + 1))) {
338 tmp5 |= 1LL << i;
339 } else {
340 tmp5 &= ~(1LL << i);
341 }
342 }
343 }
344
345 return (int64_t)(int32_t)(uint32_t)tmp5;
346}
347
348#ifndef CONFIG_USER_ONLY
349
350static inline hwaddr do_translate_address(CPUMIPSState *env,
351 target_ulong address,
352 int rw, uintptr_t retaddr)
353{
354 hwaddr paddr;
355 CPUState *cs = env_cpu(env);
356
357 paddr = cpu_mips_translate_address(env, address, rw);
358
359 if (paddr == -1LL) {
360 cpu_loop_exit_restore(cs, retaddr);
361 } else {
362 return paddr;
363 }
364}
365
366#define HELPER_LD_ATOMIC(name, insn, almask) \
367target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \
368{ \
369 if (arg & almask) { \
370 if (!(env->hflags & MIPS_HFLAG_DM)) { \
371 env->CP0_BadVAddr = arg; \
372 } \
373 do_raise_exception(env, EXCP_AdEL, GETPC()); \
374 } \
375 env->CP0_LLAddr = do_translate_address(env, arg, 0, GETPC()); \
376 env->lladdr = arg; \
377 env->llval = do_##insn(env, arg, mem_idx, GETPC()); \
378 return env->llval; \
379}
380HELPER_LD_ATOMIC(ll, lw, 0x3)
381#ifdef TARGET_MIPS64
382HELPER_LD_ATOMIC(lld, ld, 0x7)
383#endif
384#undef HELPER_LD_ATOMIC
385#endif
386
387#ifdef TARGET_WORDS_BIGENDIAN
388#define GET_LMASK(v) ((v) & 3)
389#define GET_OFFSET(addr, offset) (addr + (offset))
390#else
391#define GET_LMASK(v) (((v) & 3) ^ 3)
392#define GET_OFFSET(addr, offset) (addr - (offset))
393#endif
394
395void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
396 int mem_idx)
397{
398 do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC());
399
400 if (GET_LMASK(arg2) <= 2) {
401 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx,
402 GETPC());
403 }
404
405 if (GET_LMASK(arg2) <= 1) {
406 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx,
407 GETPC());
408 }
409
410 if (GET_LMASK(arg2) == 0) {
411 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx,
412 GETPC());
413 }
414}
415
416void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
417 int mem_idx)
418{
419 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
420
421 if (GET_LMASK(arg2) >= 1) {
422 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
423 GETPC());
424 }
425
426 if (GET_LMASK(arg2) >= 2) {
427 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
428 GETPC());
429 }
430
431 if (GET_LMASK(arg2) == 3) {
432 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
433 GETPC());
434 }
435}
436
437#if defined(TARGET_MIPS64)
438/* "half" load and stores. We must do the memory access inline,
439 or fault handling won't work. */
440
441#ifdef TARGET_WORDS_BIGENDIAN
442#define GET_LMASK64(v) ((v) & 7)
443#else
444#define GET_LMASK64(v) (((v) & 7) ^ 7)
445#endif
446
447void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
448 int mem_idx)
449{
450 do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC());
451
452 if (GET_LMASK64(arg2) <= 6) {
453 do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx,
454 GETPC());
455 }
456
457 if (GET_LMASK64(arg2) <= 5) {
458 do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx,
459 GETPC());
460 }
461
462 if (GET_LMASK64(arg2) <= 4) {
463 do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx,
464 GETPC());
465 }
466
467 if (GET_LMASK64(arg2) <= 3) {
468 do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx,
469 GETPC());
470 }
471
472 if (GET_LMASK64(arg2) <= 2) {
473 do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx,
474 GETPC());
475 }
476
477 if (GET_LMASK64(arg2) <= 1) {
478 do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx,
479 GETPC());
480 }
481
482 if (GET_LMASK64(arg2) <= 0) {
483 do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx,
484 GETPC());
485 }
486}
487
488void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
489 int mem_idx)
490{
491 do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC());
492
493 if (GET_LMASK64(arg2) >= 1) {
494 do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx,
495 GETPC());
496 }
497
498 if (GET_LMASK64(arg2) >= 2) {
499 do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx,
500 GETPC());
501 }
502
503 if (GET_LMASK64(arg2) >= 3) {
504 do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx,
505 GETPC());
506 }
507
508 if (GET_LMASK64(arg2) >= 4) {
509 do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx,
510 GETPC());
511 }
512
513 if (GET_LMASK64(arg2) >= 5) {
514 do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx,
515 GETPC());
516 }
517
518 if (GET_LMASK64(arg2) >= 6) {
519 do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx,
520 GETPC());
521 }
522
523 if (GET_LMASK64(arg2) == 7) {
524 do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx,
525 GETPC());
526 }
527}
528#endif /* TARGET_MIPS64 */
529
530static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
531
532void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
533 uint32_t mem_idx)
534{
535 target_ulong base_reglist = reglist & 0xf;
536 target_ulong do_r31 = reglist & 0x10;
537
538 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
539 target_ulong i;
540
541 for (i = 0; i < base_reglist; i++) {
542 env->active_tc.gpr[multiple_regs[i]] =
543 (target_long)do_lw(env, addr, mem_idx, GETPC());
544 addr += 4;
545 }
546 }
547
548 if (do_r31) {
549 env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx,
550 GETPC());
551 }
552}
553
554void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
555 uint32_t mem_idx)
556{
557 target_ulong base_reglist = reglist & 0xf;
558 target_ulong do_r31 = reglist & 0x10;
559
560 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
561 target_ulong i;
562
563 for (i = 0; i < base_reglist; i++) {
564 do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
565 GETPC());
566 addr += 4;
567 }
568 }
569
570 if (do_r31) {
571 do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
572 }
573}
574
575#if defined(TARGET_MIPS64)
576void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
577 uint32_t mem_idx)
578{
579 target_ulong base_reglist = reglist & 0xf;
580 target_ulong do_r31 = reglist & 0x10;
581
582 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
583 target_ulong i;
584
585 for (i = 0; i < base_reglist; i++) {
586 env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx,
587 GETPC());
588 addr += 8;
589 }
590 }
591
592 if (do_r31) {
593 env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC());
594 }
595}
596
597void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
598 uint32_t mem_idx)
599{
600 target_ulong base_reglist = reglist & 0xf;
601 target_ulong do_r31 = reglist & 0x10;
602
603 if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
604 target_ulong i;
605
606 for (i = 0; i < base_reglist; i++) {
607 do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx,
608 GETPC());
609 addr += 8;
610 }
611 }
612
613 if (do_r31) {
614 do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC());
615 }
616}
617#endif
618
619#ifndef CONFIG_USER_ONLY
620/* SMP helpers. */
621static bool mips_vpe_is_wfi(MIPSCPU *c)
622{
623 CPUState *cpu = CPU(c);
624 CPUMIPSState *env = &c->env;
625
626 /* If the VPE is halted but otherwise active, it means it's waiting for
627 an interrupt. */
628 return cpu->halted && mips_vpe_active(env);
629}
630
631static bool mips_vp_is_wfi(MIPSCPU *c)
632{
633 CPUState *cpu = CPU(c);
634 CPUMIPSState *env = &c->env;
635
636 return cpu->halted && mips_vp_active(env);
637}
638
639static inline void mips_vpe_wake(MIPSCPU *c)
640{
641 /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
642 because there might be other conditions that state that c should
643 be sleeping. */
644 qemu_mutex_lock_iothread();
645 cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
646 qemu_mutex_unlock_iothread();
647}
648
649static inline void mips_vpe_sleep(MIPSCPU *cpu)
650{
651 CPUState *cs = CPU(cpu);
652
653 /* The VPE was shut off, really go to bed.
654 Reset any old _WAKE requests. */
655 cs->halted = 1;
656 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
657}
658
659static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
660{
661 CPUMIPSState *c = &cpu->env;
662
663 /* FIXME: TC reschedule. */
664 if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
665 mips_vpe_wake(cpu);
666 }
667}
668
669static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
670{
671 CPUMIPSState *c = &cpu->env;
672
673 /* FIXME: TC reschedule. */
674 if (!mips_vpe_active(c)) {
675 mips_vpe_sleep(cpu);
676 }
677}
678
679/**
680 * mips_cpu_map_tc:
681 * @env: CPU from which mapping is performed.
682 * @tc: Should point to an int with the value of the global TC index.
683 *
684 * This function will transform @tc into a local index within the
685 * returned #CPUMIPSState.
686 */
687/* FIXME: This code assumes that all VPEs have the same number of TCs,
688 which depends on runtime setup. Can probably be fixed by
689 walking the list of CPUMIPSStates. */
690static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
691{
692 MIPSCPU *cpu;
693 CPUState *cs;
694 CPUState *other_cs;
695 int vpe_idx;
696 int tc_idx = *tc;
697
698 if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
699 /* Not allowed to address other CPUs. */
700 *tc = env->current_tc;
701 return env;
702 }
703
704 cs = env_cpu(env);
705 vpe_idx = tc_idx / cs->nr_threads;
706 *tc = tc_idx % cs->nr_threads;
707 other_cs = qemu_get_cpu(vpe_idx);
708 if (other_cs == NULL) {
709 return env;
710 }
711 cpu = MIPS_CPU(other_cs);
712 return &cpu->env;
713}
714
715/* The per VPE CP0_Status register shares some fields with the per TC
716 CP0_TCStatus registers. These fields are wired to the same registers,
717 so changes to either of them should be reflected on both registers.
718
719 Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
720
721 These helper call synchronizes the regs for a given cpu. */
722
723/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
724/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
725 int tc); */
726
727/* Called for updates to CP0_TCStatus. */
728static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
729 target_ulong v)
730{
731 uint32_t status;
732 uint32_t tcu, tmx, tasid, tksu;
733 uint32_t mask = ((1U << CP0St_CU3)
734 | (1 << CP0St_CU2)
735 | (1 << CP0St_CU1)
736 | (1 << CP0St_CU0)
737 | (1 << CP0St_MX)
738 | (3 << CP0St_KSU));
739
740 tcu = (v >> CP0TCSt_TCU0) & 0xf;
741 tmx = (v >> CP0TCSt_TMX) & 0x1;
742 tasid = v & cpu->CP0_EntryHi_ASID_mask;
743 tksu = (v >> CP0TCSt_TKSU) & 0x3;
744
745 status = tcu << CP0St_CU0;
746 status |= tmx << CP0St_MX;
747 status |= tksu << CP0St_KSU;
748
749 cpu->CP0_Status &= ~mask;
750 cpu->CP0_Status |= status;
751
752 /* Sync the TASID with EntryHi. */
753 cpu->CP0_EntryHi &= ~cpu->CP0_EntryHi_ASID_mask;
754 cpu->CP0_EntryHi |= tasid;
755
756 compute_hflags(cpu);
757}
758
759/* Called for updates to CP0_EntryHi. */
760static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
761{
762 int32_t *tcst;
763 uint32_t asid, v = cpu->CP0_EntryHi;
764
765 asid = v & cpu->CP0_EntryHi_ASID_mask;
766
767 if (tc == cpu->current_tc) {
768 tcst = &cpu->active_tc.CP0_TCStatus;
769 } else {
770 tcst = &cpu->tcs[tc].CP0_TCStatus;
771 }
772
773 *tcst &= ~cpu->CP0_EntryHi_ASID_mask;
774 *tcst |= asid;
775}
776
777/* CP0 helpers */
778target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
779{
780 return env->mvp->CP0_MVPControl;
781}
782
783target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
784{
785 return env->mvp->CP0_MVPConf0;
786}
787
788target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
789{
790 return env->mvp->CP0_MVPConf1;
791}
792
793target_ulong helper_mfc0_random(CPUMIPSState *env)
794{
795 return (int32_t)cpu_mips_get_random(env);
796}
797
798target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
799{
800 return env->active_tc.CP0_TCStatus;
801}
802
803target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
804{
805 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
806 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
807
808 if (other_tc == other->current_tc)
809 return other->active_tc.CP0_TCStatus;
810 else
811 return other->tcs[other_tc].CP0_TCStatus;
812}
813
814target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
815{
816 return env->active_tc.CP0_TCBind;
817}
818
819target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
820{
821 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
822 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
823
824 if (other_tc == other->current_tc)
825 return other->active_tc.CP0_TCBind;
826 else
827 return other->tcs[other_tc].CP0_TCBind;
828}
829
830target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
831{
832 return env->active_tc.PC;
833}
834
835target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
836{
837 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
838 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
839
840 if (other_tc == other->current_tc)
841 return other->active_tc.PC;
842 else
843 return other->tcs[other_tc].PC;
844}
845
846target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
847{
848 return env->active_tc.CP0_TCHalt;
849}
850
851target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
852{
853 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
854 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
855
856 if (other_tc == other->current_tc)
857 return other->active_tc.CP0_TCHalt;
858 else
859 return other->tcs[other_tc].CP0_TCHalt;
860}
861
862target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
863{
864 return env->active_tc.CP0_TCContext;
865}
866
867target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
868{
869 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
870 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
871
872 if (other_tc == other->current_tc)
873 return other->active_tc.CP0_TCContext;
874 else
875 return other->tcs[other_tc].CP0_TCContext;
876}
877
878target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
879{
880 return env->active_tc.CP0_TCSchedule;
881}
882
883target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
884{
885 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
886 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
887
888 if (other_tc == other->current_tc)
889 return other->active_tc.CP0_TCSchedule;
890 else
891 return other->tcs[other_tc].CP0_TCSchedule;
892}
893
894target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
895{
896 return env->active_tc.CP0_TCScheFBack;
897}
898
899target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
900{
901 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
902 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
903
904 if (other_tc == other->current_tc)
905 return other->active_tc.CP0_TCScheFBack;
906 else
907 return other->tcs[other_tc].CP0_TCScheFBack;
908}
909
910target_ulong helper_mfc0_count(CPUMIPSState *env)
911{
912 return (int32_t)cpu_mips_get_count(env);
913}
914
915target_ulong helper_mfc0_saar(CPUMIPSState *env)
916{
917 if ((env->CP0_SAARI & 0x3f) < 2) {
918 return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f];
919 }
920 return 0;
921}
922
923target_ulong helper_mfhc0_saar(CPUMIPSState *env)
924{
925 if ((env->CP0_SAARI & 0x3f) < 2) {
926 return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32;
927 }
928 return 0;
929}
930
931target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
932{
933 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
934 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
935
936 return other->CP0_EntryHi;
937}
938
939target_ulong helper_mftc0_cause(CPUMIPSState *env)
940{
941 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
942 int32_t tccause;
943 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
944
945 if (other_tc == other->current_tc) {
946 tccause = other->CP0_Cause;
947 } else {
948 tccause = other->CP0_Cause;
949 }
950
951 return tccause;
952}
953
954target_ulong helper_mftc0_status(CPUMIPSState *env)
955{
956 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
957 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
958
959 return other->CP0_Status;
960}
961
962target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
963{
964 return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift);
965}
966
967target_ulong helper_mfc0_maar(CPUMIPSState *env)
968{
969 return (int32_t) env->CP0_MAAR[env->CP0_MAARI];
970}
971
972target_ulong helper_mfhc0_maar(CPUMIPSState *env)
973{
974 return env->CP0_MAAR[env->CP0_MAARI] >> 32;
975}
976
977target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
978{
979 return (int32_t)env->CP0_WatchLo[sel];
980}
981
982target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
983{
984 return env->CP0_WatchHi[sel];
985}
986
987target_ulong helper_mfc0_debug(CPUMIPSState *env)
988{
989 target_ulong t0 = env->CP0_Debug;
990 if (env->hflags & MIPS_HFLAG_DM)
991 t0 |= 1 << CP0DB_DM;
992
993 return t0;
994}
995
996target_ulong helper_mftc0_debug(CPUMIPSState *env)
997{
998 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
999 int32_t tcstatus;
1000 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1001
1002 if (other_tc == other->current_tc)
1003 tcstatus = other->active_tc.CP0_Debug_tcstatus;
1004 else
1005 tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
1006
1007 /* XXX: Might be wrong, check with EJTAG spec. */
1008 return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1009 (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1010}
1011
1012#if defined(TARGET_MIPS64)
1013target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
1014{
1015 return env->active_tc.PC;
1016}
1017
1018target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
1019{
1020 return env->active_tc.CP0_TCHalt;
1021}
1022
1023target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
1024{
1025 return env->active_tc.CP0_TCContext;
1026}
1027
1028target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
1029{
1030 return env->active_tc.CP0_TCSchedule;
1031}
1032
1033target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
1034{
1035 return env->active_tc.CP0_TCScheFBack;
1036}
1037
1038target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
1039{
1040 return env->CP0_LLAddr >> env->CP0_LLAddr_shift;
1041}
1042
1043target_ulong helper_dmfc0_maar(CPUMIPSState *env)
1044{
1045 return env->CP0_MAAR[env->CP0_MAARI];
1046}
1047
1048target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
1049{
1050 return env->CP0_WatchLo[sel];
1051}
1052
1053target_ulong helper_dmfc0_saar(CPUMIPSState *env)
1054{
1055 if ((env->CP0_SAARI & 0x3f) < 2) {
1056 return env->CP0_SAAR[env->CP0_SAARI & 0x3f];
1057 }
1058 return 0;
1059}
1060#endif /* TARGET_MIPS64 */
1061
1062void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
1063{
1064 uint32_t index_p = env->CP0_Index & 0x80000000;
1065 uint32_t tlb_index = arg1 & 0x7fffffff;
1066 if (tlb_index < env->tlb->nb_tlb) {
1067 if (env->insn_flags & ISA_MIPS32R6) {
1068 index_p |= arg1 & 0x80000000;
1069 }
1070 env->CP0_Index = index_p | tlb_index;
1071 }
1072}
1073
1074void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
1075{
1076 uint32_t mask = 0;
1077 uint32_t newval;
1078
1079 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
1080 mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
1081 (1 << CP0MVPCo_EVP);
1082 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1083 mask |= (1 << CP0MVPCo_STLB);
1084 newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
1085
1086 // TODO: Enable/disable shared TLB, enable/disable VPEs.
1087
1088 env->mvp->CP0_MVPControl = newval;
1089}
1090
1091void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1092{
1093 uint32_t mask;
1094 uint32_t newval;
1095
1096 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1097 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1098 newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
1099
1100 /* Yield scheduler intercept not implemented. */
1101 /* Gating storage scheduler intercept not implemented. */
1102
1103 // TODO: Enable/disable TCs.
1104
1105 env->CP0_VPEControl = newval;
1106}
1107
1108void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1109{
1110 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1111 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1112 uint32_t mask;
1113 uint32_t newval;
1114
1115 mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1116 (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1117 newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1118
1119 /* TODO: Enable/disable TCs. */
1120
1121 other->CP0_VPEControl = newval;
1122}
1123
1124target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1125{
1126 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1127 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1128 /* FIXME: Mask away return zero on read bits. */
1129 return other->CP0_VPEControl;
1130}
1131
1132target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1133{
1134 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1135 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1136
1137 return other->CP0_VPEConf0;
1138}
1139
1140void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1141{
1142 uint32_t mask = 0;
1143 uint32_t newval;
1144
1145 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1146 if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1147 mask |= (0xff << CP0VPEC0_XTC);
1148 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1149 }
1150 newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1151
1152 // TODO: TC exclusive handling due to ERL/EXL.
1153
1154 env->CP0_VPEConf0 = newval;
1155}
1156
1157void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1158{
1159 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1160 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1161 uint32_t mask = 0;
1162 uint32_t newval;
1163
1164 mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1165 newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1166
1167 /* TODO: TC exclusive handling due to ERL/EXL. */
1168 other->CP0_VPEConf0 = newval;
1169}
1170
1171void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1172{
1173 uint32_t mask = 0;
1174 uint32_t newval;
1175
1176 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1177 mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1178 (0xff << CP0VPEC1_NCP1);
1179 newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1180
1181 /* UDI not implemented. */
1182 /* CP2 not implemented. */
1183
1184 // TODO: Handle FPU (CP1) binding.
1185
1186 env->CP0_VPEConf1 = newval;
1187}
1188
1189void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1190{
1191 /* Yield qualifier inputs not implemented. */
1192 env->CP0_YQMask = 0x00000000;
1193}
1194
1195void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1196{
1197 env->CP0_VPEOpt = arg1 & 0x0000ffff;
1198}
1199
1200#define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF)
1201
1202void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1203{
1204 /* 1k pages not implemented */
1205 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1206 env->CP0_EntryLo0 = (arg1 & MTC0_ENTRYLO_MASK(env))
1207 | (rxi << (CP0EnLo_XI - 30));
1208}
1209
1210#if defined(TARGET_MIPS64)
1211#define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6)
1212
1213void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1214{
1215 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1216 env->CP0_EntryLo0 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1217}
1218#endif
1219
1220void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1221{
1222 uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1223 uint32_t newval;
1224
1225 newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1226
1227 env->active_tc.CP0_TCStatus = newval;
1228 sync_c0_tcstatus(env, env->current_tc, newval);
1229}
1230
1231void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1232{
1233 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235
1236 if (other_tc == other->current_tc)
1237 other->active_tc.CP0_TCStatus = arg1;
1238 else
1239 other->tcs[other_tc].CP0_TCStatus = arg1;
1240 sync_c0_tcstatus(other, other_tc, arg1);
1241}
1242
1243void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1244{
1245 uint32_t mask = (1 << CP0TCBd_TBE);
1246 uint32_t newval;
1247
1248 if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1249 mask |= (1 << CP0TCBd_CurVPE);
1250 newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1251 env->active_tc.CP0_TCBind = newval;
1252}
1253
1254void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1255{
1256 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1257 uint32_t mask = (1 << CP0TCBd_TBE);
1258 uint32_t newval;
1259 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1260
1261 if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1262 mask |= (1 << CP0TCBd_CurVPE);
1263 if (other_tc == other->current_tc) {
1264 newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1265 other->active_tc.CP0_TCBind = newval;
1266 } else {
1267 newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1268 other->tcs[other_tc].CP0_TCBind = newval;
1269 }
1270}
1271
1272void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1273{
1274 env->active_tc.PC = arg1;
1275 env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1276 env->CP0_LLAddr = 0;
1277 env->lladdr = 0;
1278 /* MIPS16 not implemented. */
1279}
1280
1281void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1282{
1283 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1284 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1285
1286 if (other_tc == other->current_tc) {
1287 other->active_tc.PC = arg1;
1288 other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1289 other->CP0_LLAddr = 0;
1290 other->lladdr = 0;
1291 /* MIPS16 not implemented. */
1292 } else {
1293 other->tcs[other_tc].PC = arg1;
1294 other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1295 other->CP0_LLAddr = 0;
1296 other->lladdr = 0;
1297 /* MIPS16 not implemented. */
1298 }
1299}
1300
1301void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1302{
1303 MIPSCPU *cpu = env_archcpu(env);
1304
1305 env->active_tc.CP0_TCHalt = arg1 & 0x1;
1306
1307 // TODO: Halt TC / Restart (if allocated+active) TC.
1308 if (env->active_tc.CP0_TCHalt & 1) {
1309 mips_tc_sleep(cpu, env->current_tc);
1310 } else {
1311 mips_tc_wake(cpu, env->current_tc);
1312 }
1313}
1314
1315void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1316{
1317 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1318 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1319 MIPSCPU *other_cpu = env_archcpu(other);
1320
1321 // TODO: Halt TC / Restart (if allocated+active) TC.
1322
1323 if (other_tc == other->current_tc)
1324 other->active_tc.CP0_TCHalt = arg1;
1325 else
1326 other->tcs[other_tc].CP0_TCHalt = arg1;
1327
1328 if (arg1 & 1) {
1329 mips_tc_sleep(other_cpu, other_tc);
1330 } else {
1331 mips_tc_wake(other_cpu, other_tc);
1332 }
1333}
1334
1335void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1336{
1337 env->active_tc.CP0_TCContext = arg1;
1338}
1339
1340void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1341{
1342 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1343 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1344
1345 if (other_tc == other->current_tc)
1346 other->active_tc.CP0_TCContext = arg1;
1347 else
1348 other->tcs[other_tc].CP0_TCContext = arg1;
1349}
1350
1351void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1352{
1353 env->active_tc.CP0_TCSchedule = arg1;
1354}
1355
1356void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1357{
1358 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1359 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1360
1361 if (other_tc == other->current_tc)
1362 other->active_tc.CP0_TCSchedule = arg1;
1363 else
1364 other->tcs[other_tc].CP0_TCSchedule = arg1;
1365}
1366
1367void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1368{
1369 env->active_tc.CP0_TCScheFBack = arg1;
1370}
1371
1372void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1373{
1374 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1375 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1376
1377 if (other_tc == other->current_tc)
1378 other->active_tc.CP0_TCScheFBack = arg1;
1379 else
1380 other->tcs[other_tc].CP0_TCScheFBack = arg1;
1381}
1382
1383void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1384{
1385 /* 1k pages not implemented */
1386 target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1387 env->CP0_EntryLo1 = (arg1 & MTC0_ENTRYLO_MASK(env))
1388 | (rxi << (CP0EnLo_XI - 30));
1389}
1390
1391#if defined(TARGET_MIPS64)
1392void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1393{
1394 uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1395 env->CP0_EntryLo1 = (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi;
1396}
1397#endif
1398
1399void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1400{
1401 env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1402}
1403
1404void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask)
1405{
1406 uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1);
1407 if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) ||
1408 (mask == 0x0000 || mask == 0x0003 || mask == 0x000F ||
1409 mask == 0x003F || mask == 0x00FF || mask == 0x03FF ||
1410 mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) {
1411 env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1412 }
1413}
1414
1415void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1416{
1417 update_pagemask(env, arg1, &env->CP0_PageMask);
1418}
1419
1420void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1421{
1422 /* SmartMIPS not implemented */
1423 /* 1k pages not implemented */
1424 env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1425 (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1426 compute_hflags(env);
1427 restore_pamask(env);
1428}
1429
1430void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1)
1431{
1432 CPUState *cs = env_cpu(env);
1433
1434 env->CP0_SegCtl0 = arg1 & CP0SC0_MASK;
1435 tlb_flush(cs);
1436}
1437
1438void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1)
1439{
1440 CPUState *cs = env_cpu(env);
1441
1442 env->CP0_SegCtl1 = arg1 & CP0SC1_MASK;
1443 tlb_flush(cs);
1444}
1445
1446void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1)
1447{
1448 CPUState *cs = env_cpu(env);
1449
1450 env->CP0_SegCtl2 = arg1 & CP0SC2_MASK;
1451 tlb_flush(cs);
1452}
1453
1454void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1)
1455{
1456#if defined(TARGET_MIPS64)
1457 uint64_t mask = 0x3F3FFFFFFFULL;
1458 uint32_t old_ptei = (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL;
1459 uint32_t new_ptei = (arg1 >> CP0PF_PTEI) & 0x3FULL;
1460
1461 if ((env->insn_flags & ISA_MIPS32R6)) {
1462 if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) {
1463 mask &= ~(0x3FULL << CP0PF_BDI);
1464 }
1465 if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) {
1466 mask &= ~(0x3FULL << CP0PF_GDI);
1467 }
1468 if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) {
1469 mask &= ~(0x3FULL << CP0PF_UDI);
1470 }
1471 if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) {
1472 mask &= ~(0x3FULL << CP0PF_MDI);
1473 }
1474 if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) {
1475 mask &= ~(0x3FULL << CP0PF_PTI);
1476 }
1477 }
1478 env->CP0_PWField = arg1 & mask;
1479
1480 if ((new_ptei >= 32) ||
1481 ((env->insn_flags & ISA_MIPS32R6) &&
1482 (new_ptei == 0 || new_ptei == 1))) {
1483 env->CP0_PWField = (env->CP0_PWField & ~0x3FULL) |
1484 (old_ptei << CP0PF_PTEI);
1485 }
1486#else
1487 uint32_t mask = 0x3FFFFFFF;
1488 uint32_t old_ptew = (env->CP0_PWField >> CP0PF_PTEW) & 0x3F;
1489 uint32_t new_ptew = (arg1 >> CP0PF_PTEW) & 0x3F;
1490
1491 if ((env->insn_flags & ISA_MIPS32R6)) {
1492 if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) {
1493 mask &= ~(0x3F << CP0PF_GDW);
1494 }
1495 if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) {
1496 mask &= ~(0x3F << CP0PF_UDW);
1497 }
1498 if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) {
1499 mask &= ~(0x3F << CP0PF_MDW);
1500 }
1501 if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) {
1502 mask &= ~(0x3F << CP0PF_PTW);
1503 }
1504 }
1505 env->CP0_PWField = arg1 & mask;
1506
1507 if ((new_ptew >= 32) ||
1508 ((env->insn_flags & ISA_MIPS32R6) &&
1509 (new_ptew == 0 || new_ptew == 1))) {
1510 env->CP0_PWField = (env->CP0_PWField & ~0x3F) |
1511 (old_ptew << CP0PF_PTEW);
1512 }
1513#endif
1514}
1515
1516void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1)
1517{
1518#if defined(TARGET_MIPS64)
1519 env->CP0_PWSize = arg1 & 0x3F7FFFFFFFULL;
1520#else
1521 env->CP0_PWSize = arg1 & 0x3FFFFFFF;
1522#endif
1523}
1524
1525void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1526{
1527 if (env->insn_flags & ISA_MIPS32R6) {
1528 if (arg1 < env->tlb->nb_tlb) {
1529 env->CP0_Wired = arg1;
1530 }
1531 } else {
1532 env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1533 }
1534}
1535
1536void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1)
1537{
1538#if defined(TARGET_MIPS64)
1539 /* PWEn = 0. Hardware page table walking is not implemented. */
1540 env->CP0_PWCtl = (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F);
1541#else
1542 env->CP0_PWCtl = (arg1 & 0x800000FF);
1543#endif
1544}
1545
1546void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1547{
1548 env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1549}
1550
1551void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1552{
1553 env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1554}
1555
1556void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1557{
1558 env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1559}
1560
1561void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1562{
1563 env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1564}
1565
1566void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1567{
1568 env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1569}
1570
1571void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1572{
1573 uint32_t mask = 0x0000000F;
1574
1575 if ((env->CP0_Config1 & (1 << CP0C1_PC)) &&
1576 (env->insn_flags & ISA_MIPS32R6)) {
1577 mask |= (1 << 4);
1578 }
1579 if (env->insn_flags & ISA_MIPS32R6) {
1580 mask |= (1 << 5);
1581 }
1582 if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1583 mask |= (1 << 29);
1584
1585 if (arg1 & (1 << 29)) {
1586 env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1587 } else {
1588 env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1589 }
1590 }
1591
1592 env->CP0_HWREna = arg1 & mask;
1593}
1594
1595void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1596{
1597 cpu_mips_store_count(env, arg1);
1598}
1599
1600void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1)
1601{
1602 uint32_t target = arg1 & 0x3f;
1603 if (target <= 1) {
1604 env->CP0_SAARI = target;
1605 }
1606}
1607
1608void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1)
1609{
1610 uint32_t target = env->CP0_SAARI & 0x3f;
1611 if (target < 2) {
1612 env->CP0_SAAR[target] = arg1 & 0x00000ffffffff03fULL;
1613 switch (target) {
1614 case 0:
1615 if (env->itu) {
1616 itc_reconfigure(env->itu);
1617 }
1618 break;
1619 }
1620 }
1621}
1622
1623void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1)
1624{
1625 uint32_t target = env->CP0_SAARI & 0x3f;
1626 if (target < 2) {
1627 env->CP0_SAAR[target] =
1628 (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) |
1629 (env->CP0_SAAR[target] & 0x00000000ffffffffULL);
1630 switch (target) {
1631 case 0:
1632 if (env->itu) {
1633 itc_reconfigure(env->itu);
1634 }
1635 break;
1636 }
1637 }
1638}
1639
1640void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1641{
1642 target_ulong old, val, mask;
1643 mask = (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask;
1644 if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1645 mask |= 1 << CP0EnHi_EHINV;
1646 }
1647
1648 /* 1k pages not implemented */
1649#if defined(TARGET_MIPS64)
1650 if (env->insn_flags & ISA_MIPS32R6) {
1651 int entryhi_r = extract64(arg1, 62, 2);
1652 int config0_at = extract32(env->CP0_Config0, 13, 2);
1653 bool no_supervisor = (env->CP0_Status_rw_bitmask & 0x8) == 0;
1654 if ((entryhi_r == 2) ||
1655 (entryhi_r == 1 && (no_supervisor || config0_at == 1))) {
1656 /* skip EntryHi.R field if new value is reserved */
1657 mask &= ~(0x3ull << 62);
1658 }
1659 }
1660 mask &= env->SEGMask;
1661#endif
1662 old = env->CP0_EntryHi;
1663 val = (arg1 & mask) | (old & ~mask);
1664 env->CP0_EntryHi = val;
1665 if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1666 sync_c0_entryhi(env, env->current_tc);
1667 }
1668 /* If the ASID changes, flush qemu's TLB. */
1669 if ((old & env->CP0_EntryHi_ASID_mask) !=
1670 (val & env->CP0_EntryHi_ASID_mask)) {
1671 tlb_flush(env_cpu(env));
1672 }
1673}
1674
1675void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1676{
1677 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1678 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1679
1680 other->CP0_EntryHi = arg1;
1681 sync_c0_entryhi(other, other_tc);
1682}
1683
1684void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1685{
1686 cpu_mips_store_compare(env, arg1);
1687}
1688
1689void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1690{
1691 uint32_t val, old;
1692
1693 old = env->CP0_Status;
1694 cpu_mips_store_status(env, arg1);
1695 val = env->CP0_Status;
1696
1697 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1698 qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1699 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1700 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1701 env->CP0_Cause);
1702 switch (cpu_mmu_index(env, false)) {
1703 case 3:
1704 qemu_log(", ERL\n");
1705 break;
1706 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1707 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1708 case MIPS_HFLAG_KM: qemu_log("\n"); break;
1709 default:
1710 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
1711 break;
1712 }
1713 }
1714}
1715
1716void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1717{
1718 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1719 uint32_t mask = env->CP0_Status_rw_bitmask & ~0xf1000018;
1720 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1721
1722 other->CP0_Status = (other->CP0_Status & ~mask) | (arg1 & mask);
1723 sync_c0_status(env, other, other_tc);
1724}
1725
1726void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1727{
1728 env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1729}
1730
1731void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1732{
1733 uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1734 env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1735}
1736
1737void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1738{
1739 cpu_mips_store_cause(env, arg1);
1740}
1741
1742void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1743{
1744 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1745 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1746
1747 cpu_mips_store_cause(other, arg1);
1748}
1749
1750target_ulong helper_mftc0_epc(CPUMIPSState *env)
1751{
1752 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1753 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1754
1755 return other->CP0_EPC;
1756}
1757
1758target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1759{
1760 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1761 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1762
1763 return other->CP0_EBase;
1764}
1765
1766void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1767{
1768 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1769 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1770 mask |= ~0x3FFFFFFF;
1771 }
1772 env->CP0_EBase = (env->CP0_EBase & ~mask) | (arg1 & mask);
1773}
1774
1775void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1776{
1777 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1778 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1779 target_ulong mask = 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask;
1780 if (arg1 & env->CP0_EBaseWG_rw_bitmask) {
1781 mask |= ~0x3FFFFFFF;
1782 }
1783 other->CP0_EBase = (other->CP0_EBase & ~mask) | (arg1 & mask);
1784}
1785
1786target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1787{
1788 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1789 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1790
1791 switch (idx) {
1792 case 0: return other->CP0_Config0;
1793 case 1: return other->CP0_Config1;
1794 case 2: return other->CP0_Config2;
1795 case 3: return other->CP0_Config3;
1796 /* 4 and 5 are reserved. */
1797 case 6: return other->CP0_Config6;
1798 case 7: return other->CP0_Config7;
1799 default:
1800 break;
1801 }
1802 return 0;
1803}
1804
1805void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1806{
1807 env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1808}
1809
1810void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1811{
1812 /* tertiary/secondary caches not implemented */
1813 env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1814}
1815
1816void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1)
1817{
1818 if (env->insn_flags & ASE_MICROMIPS) {
1819 env->CP0_Config3 = (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC)) |
1820 (arg1 & (1 << CP0C3_ISA_ON_EXC));
1821 }
1822}
1823
1824void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1825{
1826 env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1827 (arg1 & env->CP0_Config4_rw_bitmask);
1828}
1829
1830void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1831{
1832 env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1833 (arg1 & env->CP0_Config5_rw_bitmask);
1834 compute_hflags(env);
1835}
1836
1837void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1838{
1839 target_long mask = env->CP0_LLAddr_rw_bitmask;
1840 arg1 = arg1 << env->CP0_LLAddr_shift;
1841 env->CP0_LLAddr = (env->CP0_LLAddr & ~mask) | (arg1 & mask);
1842}
1843
1844#define MTC0_MAAR_MASK(env) \
1845 ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3)
1846
1847void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1)
1848{
1849 env->CP0_MAAR[env->CP0_MAARI] = arg1 & MTC0_MAAR_MASK(env);
1850}
1851
1852void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1)
1853{
1854 env->CP0_MAAR[env->CP0_MAARI] =
1855 (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) |
1856 (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL);
1857}
1858
1859void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
1860{
1861 int index = arg1 & 0x3f;
1862 if (index == 0x3f) {
1863 /* Software may write all ones to INDEX to determine the
1864 maximum value supported. */
1865 env->CP0_MAARI = MIPS_MAAR_MAX - 1;
1866 } else if (index < MIPS_MAAR_MAX) {
1867 env->CP0_MAARI = index;
1868 }
1869 /* Other than the all ones, if the
1870 value written is not supported, then INDEX is unchanged
1871 from its previous value. */
1872}
1873
1874void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1875{
1876 /* Watch exceptions for instructions, data loads, data stores
1877 not implemented. */
1878 env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1879}
1880
1881void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1882{
1883 int mask = 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_ASID);
1884 env->CP0_WatchHi[sel] = arg1 & mask;
1885 env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1886}
1887
1888void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1889{
1890 target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1891 env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1892}
1893
1894void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1895{
1896 env->CP0_Framemask = arg1; /* XXX */
1897}
1898
1899void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1900{
1901 env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1902 if (arg1 & (1 << CP0DB_DM))
1903 env->hflags |= MIPS_HFLAG_DM;
1904 else
1905 env->hflags &= ~MIPS_HFLAG_DM;
1906}
1907
1908void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1909{
1910 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1911 uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1912 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1913
1914 /* XXX: Might be wrong, check with EJTAG spec. */
1915 if (other_tc == other->current_tc)
1916 other->active_tc.CP0_Debug_tcstatus = val;
1917 else
1918 other->tcs[other_tc].CP0_Debug_tcstatus = val;
1919 other->CP0_Debug = (other->CP0_Debug &
1920 ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1921 (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1922}
1923
1924void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1925{
1926 env->CP0_Performance0 = arg1 & 0x000007ff;
1927}
1928
1929void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
1930{
1931 int32_t wst = arg1 & (1 << CP0EC_WST);
1932 int32_t spr = arg1 & (1 << CP0EC_SPR);
1933 int32_t itc = env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0;
1934
1935 env->CP0_ErrCtl = wst | spr | itc;
1936
1937 if (itc && !wst && !spr) {
1938 env->hflags |= MIPS_HFLAG_ITC_CACHE;
1939 } else {
1940 env->hflags &= ~MIPS_HFLAG_ITC_CACHE;
1941 }
1942}
1943
1944void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1945{
1946 if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
1947 /* If CACHE instruction is configured for ITC tags then make all
1948 CP0.TagLo bits writable. The actual write to ITC Configuration
1949 Tag will take care of the read-only bits. */
1950 env->CP0_TagLo = arg1;
1951 } else {
1952 env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1953 }
1954}
1955
1956void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1957{
1958 env->CP0_DataLo = arg1; /* XXX */
1959}
1960
1961void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1962{
1963 env->CP0_TagHi = arg1; /* XXX */
1964}
1965
1966void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1967{
1968 env->CP0_DataHi = arg1; /* XXX */
1969}
1970
1971/* MIPS MT functions */
1972target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1973{
1974 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1975 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1976
1977 if (other_tc == other->current_tc)
1978 return other->active_tc.gpr[sel];
1979 else
1980 return other->tcs[other_tc].gpr[sel];
1981}
1982
1983target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1984{
1985 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1986 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1987
1988 if (other_tc == other->current_tc)
1989 return other->active_tc.LO[sel];
1990 else
1991 return other->tcs[other_tc].LO[sel];
1992}
1993
1994target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1995{
1996 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1997 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1998
1999 if (other_tc == other->current_tc)
2000 return other->active_tc.HI[sel];
2001 else
2002 return other->tcs[other_tc].HI[sel];
2003}
2004
2005target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
2006{
2007 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2008 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2009
2010 if (other_tc == other->current_tc)
2011 return other->active_tc.ACX[sel];
2012 else
2013 return other->tcs[other_tc].ACX[sel];
2014}
2015
2016target_ulong helper_mftdsp(CPUMIPSState *env)
2017{
2018 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2019 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2020
2021 if (other_tc == other->current_tc)
2022 return other->active_tc.DSPControl;
2023 else
2024 return other->tcs[other_tc].DSPControl;
2025}
2026
2027void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2028{
2029 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2030 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2031
2032 if (other_tc == other->current_tc)
2033 other->active_tc.gpr[sel] = arg1;
2034 else
2035 other->tcs[other_tc].gpr[sel] = arg1;
2036}
2037
2038void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2039{
2040 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2041 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2042
2043 if (other_tc == other->current_tc)
2044 other->active_tc.LO[sel] = arg1;
2045 else
2046 other->tcs[other_tc].LO[sel] = arg1;
2047}
2048
2049void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2050{
2051 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2052 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2053
2054 if (other_tc == other->current_tc)
2055 other->active_tc.HI[sel] = arg1;
2056 else
2057 other->tcs[other_tc].HI[sel] = arg1;
2058}
2059
2060void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
2061{
2062 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2063 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2064
2065 if (other_tc == other->current_tc)
2066 other->active_tc.ACX[sel] = arg1;
2067 else
2068 other->tcs[other_tc].ACX[sel] = arg1;
2069}
2070
2071void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
2072{
2073 int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
2074 CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
2075
2076 if (other_tc == other->current_tc)
2077 other->active_tc.DSPControl = arg1;
2078 else
2079 other->tcs[other_tc].DSPControl = arg1;
2080}
2081
2082/* MIPS MT functions */
2083target_ulong helper_dmt(void)
2084{
2085 // TODO
2086 return 0;
2087}
2088
2089target_ulong helper_emt(void)
2090{
2091 // TODO
2092 return 0;
2093}
2094
2095target_ulong helper_dvpe(CPUMIPSState *env)
2096{
2097 CPUState *other_cs = first_cpu;
2098 target_ulong prev = env->mvp->CP0_MVPControl;
2099
2100 CPU_FOREACH(other_cs) {
2101 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2102 /* Turn off all VPEs except the one executing the dvpe. */
2103 if (&other_cpu->env != env) {
2104 other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
2105 mips_vpe_sleep(other_cpu);
2106 }
2107 }
2108 return prev;
2109}
2110
2111target_ulong helper_evpe(CPUMIPSState *env)
2112{
2113 CPUState *other_cs = first_cpu;
2114 target_ulong prev = env->mvp->CP0_MVPControl;
2115
2116 CPU_FOREACH(other_cs) {
2117 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2118
2119 if (&other_cpu->env != env
2120 /* If the VPE is WFI, don't disturb its sleep. */
2121 && !mips_vpe_is_wfi(other_cpu)) {
2122 /* Enable the VPE. */
2123 other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
2124 mips_vpe_wake(other_cpu); /* And wake it up. */
2125 }
2126 }
2127 return prev;
2128}
2129#endif /* !CONFIG_USER_ONLY */
2130
2131void helper_fork(target_ulong arg1, target_ulong arg2)
2132{
2133 // arg1 = rt, arg2 = rs
2134 // TODO: store to TC register
2135}
2136
2137target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
2138{
2139 target_long arg1 = arg;
2140
2141 if (arg1 < 0) {
2142 /* No scheduling policy implemented. */
2143 if (arg1 != -2) {
2144 if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
2145 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
2146 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2147 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
2148 do_raise_exception(env, EXCP_THREAD, GETPC());
2149 }
2150 }
2151 } else if (arg1 == 0) {
2152 if (0 /* TODO: TC underflow */) {
2153 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2154 do_raise_exception(env, EXCP_THREAD, GETPC());
2155 } else {
2156 // TODO: Deallocate TC
2157 }
2158 } else if (arg1 > 0) {
2159 /* Yield qualifier inputs not implemented. */
2160 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
2161 env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
2162 do_raise_exception(env, EXCP_THREAD, GETPC());
2163 }
2164 return env->CP0_YQMask;
2165}
2166
2167/* R6 Multi-threading */
2168#ifndef CONFIG_USER_ONLY
2169target_ulong helper_dvp(CPUMIPSState *env)
2170{
2171 CPUState *other_cs = first_cpu;
2172 target_ulong prev = env->CP0_VPControl;
2173
2174 if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) {
2175 CPU_FOREACH(other_cs) {
2176 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2177 /* Turn off all VPs except the one executing the dvp. */
2178 if (&other_cpu->env != env) {
2179 mips_vpe_sleep(other_cpu);
2180 }
2181 }
2182 env->CP0_VPControl |= (1 << CP0VPCtl_DIS);
2183 }
2184 return prev;
2185}
2186
2187target_ulong helper_evp(CPUMIPSState *env)
2188{
2189 CPUState *other_cs = first_cpu;
2190 target_ulong prev = env->CP0_VPControl;
2191
2192 if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) {
2193 CPU_FOREACH(other_cs) {
2194 MIPSCPU *other_cpu = MIPS_CPU(other_cs);
2195 if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
2196 /* If the VP is WFI, don't disturb its sleep.
2197 * Otherwise, wake it up. */
2198 mips_vpe_wake(other_cpu);
2199 }
2200 }
2201 env->CP0_VPControl &= ~(1 << CP0VPCtl_DIS);
2202 }
2203 return prev;
2204}
2205#endif /* !CONFIG_USER_ONLY */
2206
2207#ifndef CONFIG_USER_ONLY
2208/* TLB management */
2209static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
2210{
2211 /* Discard entries from env->tlb[first] onwards. */
2212 while (env->tlb->tlb_in_use > first) {
2213 r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
2214 }
2215}
2216
2217static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo)
2218{
2219#if defined(TARGET_MIPS64)
2220 return extract64(entrylo, 6, 54);
2221#else
2222 return extract64(entrylo, 6, 24) | /* PFN */
2223 (extract64(entrylo, 32, 32) << 24); /* PFNX */
2224#endif
2225}
2226
2227static void r4k_fill_tlb(CPUMIPSState *env, int idx)
2228{
2229 r4k_tlb_t *tlb;
2230 uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1);
2231
2232 /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
2233 tlb = &env->tlb->mmu.r4k.tlb[idx];
2234 if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
2235 tlb->EHINV = 1;
2236 return;
2237 }
2238 tlb->EHINV = 0;
2239 tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2240#if defined(TARGET_MIPS64)
2241 tlb->VPN &= env->SEGMask;
2242#endif
2243 tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2244 tlb->PageMask = env->CP0_PageMask;
2245 tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2246 tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
2247 tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
2248 tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
2249 tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
2250 tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
2251 tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12;
2252 tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
2253 tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
2254 tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
2255 tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
2256 tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
2257 tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12;
2258}
2259
2260void r4k_helper_tlbinv(CPUMIPSState *env)
2261{
2262 int idx;
2263 r4k_tlb_t *tlb;
2264 uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2265
2266 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2267 tlb = &env->tlb->mmu.r4k.tlb[idx];
2268 if (!tlb->G && tlb->ASID == ASID) {
2269 tlb->EHINV = 1;
2270 }
2271 }
2272 cpu_mips_tlb_flush(env);
2273}
2274
2275void r4k_helper_tlbinvf(CPUMIPSState *env)
2276{
2277 int idx;
2278
2279 for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
2280 env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
2281 }
2282 cpu_mips_tlb_flush(env);
2283}
2284
2285void r4k_helper_tlbwi(CPUMIPSState *env)
2286{
2287 r4k_tlb_t *tlb;
2288 int idx;
2289 target_ulong VPN;
2290 uint16_t ASID;
2291 bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1;
2292
2293 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2294 tlb = &env->tlb->mmu.r4k.tlb[idx];
2295 VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
2296#if defined(TARGET_MIPS64)
2297 VPN &= env->SEGMask;
2298#endif
2299 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2300 EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0;
2301 G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
2302 V0 = (env->CP0_EntryLo0 & 2) != 0;
2303 D0 = (env->CP0_EntryLo0 & 4) != 0;
2304 XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1;
2305 RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1;
2306 V1 = (env->CP0_EntryLo1 & 2) != 0;
2307 D1 = (env->CP0_EntryLo1 & 4) != 0;
2308 XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
2309 RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
2310
2311 /* Discard cached TLB entries, unless tlbwi is just upgrading access
2312 permissions on the current entry. */
2313 if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
2314 (!tlb->EHINV && EHINV) ||
2315 (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
2316 (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) ||
2317 (tlb->V1 && !V1) || (tlb->D1 && !D1) ||
2318 (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) {
2319 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2320 }
2321
2322 r4k_invalidate_tlb(env, idx, 0);
2323 r4k_fill_tlb(env, idx);
2324}
2325
2326void r4k_helper_tlbwr(CPUMIPSState *env)
2327{
2328 int r = cpu_mips_get_random(env);
2329
2330 r4k_invalidate_tlb(env, r, 1);
2331 r4k_fill_tlb(env, r);
2332}
2333
2334void r4k_helper_tlbp(CPUMIPSState *env)
2335{
2336 r4k_tlb_t *tlb;
2337 target_ulong mask;
2338 target_ulong tag;
2339 target_ulong VPN;
2340 uint16_t ASID;
2341 int i;
2342
2343 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2344 for (i = 0; i < env->tlb->nb_tlb; i++) {
2345 tlb = &env->tlb->mmu.r4k.tlb[i];
2346 /* 1k pages are not supported. */
2347 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2348 tag = env->CP0_EntryHi & ~mask;
2349 VPN = tlb->VPN & ~mask;
2350#if defined(TARGET_MIPS64)
2351 tag &= env->SEGMask;
2352#endif
2353 /* Check ASID, virtual page number & size */
2354 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
2355 /* TLB match */
2356 env->CP0_Index = i;
2357 break;
2358 }
2359 }
2360 if (i == env->tlb->nb_tlb) {
2361 /* No match. Discard any shadow entries, if any of them match. */
2362 for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
2363 tlb = &env->tlb->mmu.r4k.tlb[i];
2364 /* 1k pages are not supported. */
2365 mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
2366 tag = env->CP0_EntryHi & ~mask;
2367 VPN = tlb->VPN & ~mask;
2368#if defined(TARGET_MIPS64)
2369 tag &= env->SEGMask;
2370#endif
2371 /* Check ASID, virtual page number & size */
2372 if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
2373 r4k_mips_tlb_flush_extra (env, i);
2374 break;
2375 }
2376 }
2377
2378 env->CP0_Index |= 0x80000000;
2379 }
2380}
2381
2382static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn)
2383{
2384#if defined(TARGET_MIPS64)
2385 return tlb_pfn << 6;
2386#else
2387 return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */
2388 (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */
2389#endif
2390}
2391
2392void r4k_helper_tlbr(CPUMIPSState *env)
2393{
2394 r4k_tlb_t *tlb;
2395 uint16_t ASID;
2396 int idx;
2397
2398 ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
2399 idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2400 tlb = &env->tlb->mmu.r4k.tlb[idx];
2401
2402 /* If this will change the current ASID, flush qemu's TLB. */
2403 if (ASID != tlb->ASID)
2404 cpu_mips_tlb_flush(env);
2405
2406 r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2407
2408 if (tlb->EHINV) {
2409 env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2410 env->CP0_PageMask = 0;
2411 env->CP0_EntryLo0 = 0;
2412 env->CP0_EntryLo1 = 0;
2413 } else {
2414 env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2415 env->CP0_PageMask = tlb->PageMask;
2416 env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2417 ((uint64_t)tlb->RI0 << CP0EnLo_RI) |
2418 ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) |
2419 get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12);
2420 env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2421 ((uint64_t)tlb->RI1 << CP0EnLo_RI) |
2422 ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) |
2423 get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12);
2424 }
2425}
2426
2427void helper_tlbwi(CPUMIPSState *env)
2428{
2429 env->tlb->helper_tlbwi(env);
2430}
2431
2432void helper_tlbwr(CPUMIPSState *env)
2433{
2434 env->tlb->helper_tlbwr(env);
2435}
2436
2437void helper_tlbp(CPUMIPSState *env)
2438{
2439 env->tlb->helper_tlbp(env);
2440}
2441
2442void helper_tlbr(CPUMIPSState *env)
2443{
2444 env->tlb->helper_tlbr(env);
2445}
2446
2447void helper_tlbinv(CPUMIPSState *env)
2448{
2449 env->tlb->helper_tlbinv(env);
2450}
2451
2452void helper_tlbinvf(CPUMIPSState *env)
2453{
2454 env->tlb->helper_tlbinvf(env);
2455}
2456
2457/* Specials */
2458target_ulong helper_di(CPUMIPSState *env)
2459{
2460 target_ulong t0 = env->CP0_Status;
2461
2462 env->CP0_Status = t0 & ~(1 << CP0St_IE);
2463 return t0;
2464}
2465
2466target_ulong helper_ei(CPUMIPSState *env)
2467{
2468 target_ulong t0 = env->CP0_Status;
2469
2470 env->CP0_Status = t0 | (1 << CP0St_IE);
2471 return t0;
2472}
2473
2474static void debug_pre_eret(CPUMIPSState *env)
2475{
2476 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2477 qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2478 env->active_tc.PC, env->CP0_EPC);
2479 if (env->CP0_Status & (1 << CP0St_ERL))
2480 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2481 if (env->hflags & MIPS_HFLAG_DM)
2482 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2483 qemu_log("\n");
2484 }
2485}
2486
2487static void debug_post_eret(CPUMIPSState *env)
2488{
2489 if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2490 qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2491 env->active_tc.PC, env->CP0_EPC);
2492 if (env->CP0_Status & (1 << CP0St_ERL))
2493 qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2494 if (env->hflags & MIPS_HFLAG_DM)
2495 qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2496 switch (cpu_mmu_index(env, false)) {
2497 case 3:
2498 qemu_log(", ERL\n");
2499 break;
2500 case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2501 case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2502 case MIPS_HFLAG_KM: qemu_log("\n"); break;
2503 default:
2504 cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
2505 break;
2506 }
2507 }
2508}
2509
2510static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2511{
2512 env->active_tc.PC = error_pc & ~(target_ulong)1;
2513 if (error_pc & 1) {
2514 env->hflags |= MIPS_HFLAG_M16;
2515 } else {
2516 env->hflags &= ~(MIPS_HFLAG_M16);
2517 }
2518}
2519
2520static inline void exception_return(CPUMIPSState *env)
2521{
2522 debug_pre_eret(env);
2523 if (env->CP0_Status & (1 << CP0St_ERL)) {
2524 set_pc(env, env->CP0_ErrorEPC);
2525 env->CP0_Status &= ~(1 << CP0St_ERL);
2526 } else {
2527 set_pc(env, env->CP0_EPC);
2528 env->CP0_Status &= ~(1 << CP0St_EXL);
2529 }
2530 compute_hflags(env);
2531 debug_post_eret(env);
2532}
2533
2534void helper_eret(CPUMIPSState *env)
2535{
2536 exception_return(env);
2537 env->CP0_LLAddr = 1;
2538 env->lladdr = 1;
2539}
2540
2541void helper_eretnc(CPUMIPSState *env)
2542{
2543 exception_return(env);
2544}
2545
2546void helper_deret(CPUMIPSState *env)
2547{
2548 debug_pre_eret(env);
2549
2550 env->hflags &= ~MIPS_HFLAG_DM;
2551 compute_hflags(env);
2552
2553 set_pc(env, env->CP0_DEPC);
2554
2555 debug_post_eret(env);
2556}
2557#endif /* !CONFIG_USER_ONLY */
2558
2559static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc)
2560{
2561 if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) {
2562 return;
2563 }
2564 do_raise_exception(env, EXCP_RI, pc);
2565}
2566
2567target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2568{
2569 check_hwrena(env, 0, GETPC());
2570 return env->CP0_EBase & 0x3ff;
2571}
2572
2573target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2574{
2575 check_hwrena(env, 1, GETPC());
2576 return env->SYNCI_Step;
2577}
2578
2579target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2580{
2581 check_hwrena(env, 2, GETPC());
2582#ifdef CONFIG_USER_ONLY
2583 return env->CP0_Count;
2584#else
2585 return (int32_t)cpu_mips_get_count(env);
2586#endif
2587}
2588
2589target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2590{
2591 check_hwrena(env, 3, GETPC());
2592 return env->CCRes;
2593}
2594
2595target_ulong helper_rdhwr_performance(CPUMIPSState *env)
2596{
2597 check_hwrena(env, 4, GETPC());
2598 return env->CP0_Performance0;
2599}
2600
2601target_ulong helper_rdhwr_xnp(CPUMIPSState *env)
2602{
2603 check_hwrena(env, 5, GETPC());
2604 return (env->CP0_Config5 >> CP0C5_XNP) & 1;
2605}
2606
2607void helper_pmon(CPUMIPSState *env, int function)
2608{
2609 function /= 2;
2610 switch (function) {
2611 case 2: /* TODO: char inbyte(int waitflag); */
2612 if (env->active_tc.gpr[4] == 0)
2613 env->active_tc.gpr[2] = -1;
2614 /* Fall through */
2615 case 11: /* TODO: char inbyte (void); */
2616 env->active_tc.gpr[2] = -1;
2617 break;
2618 case 3:
2619 case 12:
2620 printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2621 break;
2622 case 17:
2623 break;
2624 case 158:
2625 {
2626 unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2627 printf("%s", fmt);
2628 }
2629 break;
2630 }
2631}
2632
2633void helper_wait(CPUMIPSState *env)
2634{
2635 CPUState *cs = env_cpu(env);
2636
2637 cs->halted = 1;
2638 cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2639 /* Last instruction in the block, PC was updated before
2640 - no need to recover PC and icount */
2641 raise_exception(env, EXCP_HLT);
2642}
2643
2644#if !defined(CONFIG_USER_ONLY)
2645
2646void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2647 MMUAccessType access_type,
2648 int mmu_idx, uintptr_t retaddr)
2649{
2650 MIPSCPU *cpu = MIPS_CPU(cs);
2651 CPUMIPSState *env = &cpu->env;
2652 int error_code = 0;
2653 int excp;
2654
2655 if (!(env->hflags & MIPS_HFLAG_DM)) {
2656 env->CP0_BadVAddr = addr;
2657 }
2658
2659 if (access_type == MMU_DATA_STORE) {
2660 excp = EXCP_AdES;
2661 } else {
2662 excp = EXCP_AdEL;
2663 if (access_type == MMU_INST_FETCH) {
2664 error_code |= EXCP_INST_NOTAVAIL;
2665 }
2666 }
2667
2668 do_raise_exception_err(env, excp, error_code, retaddr);
2669}
2670
2671void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2672 bool is_write, bool is_exec, int unused,
2673 unsigned size)
2674{
2675 MIPSCPU *cpu = MIPS_CPU(cs);
2676 CPUMIPSState *env = &cpu->env;
2677
2678 /*
2679 * Raising an exception with KVM enabled will crash because it won't be from
2680 * the main execution loop so the longjmp won't have a matching setjmp.
2681 * Until we can trigger a bus error exception through KVM lets just ignore
2682 * the access.
2683 */
2684 if (kvm_enabled()) {
2685 return;
2686 }
2687
2688 if (is_exec) {
2689 raise_exception(env, EXCP_IBE);
2690 } else {
2691 raise_exception(env, EXCP_DBE);
2692 }
2693}
2694#endif /* !CONFIG_USER_ONLY */
2695
2696/* Complex FPU operations which may need stack space. */
2697
2698#define FLOAT_TWO32 make_float32(1 << 30)
2699#define FLOAT_TWO64 make_float64(1ULL << 62)
2700
2701#define FP_TO_INT32_OVERFLOW 0x7fffffff
2702#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2703
2704/* convert MIPS rounding mode in FCR31 to IEEE library */
2705unsigned int ieee_rm[] = {
2706 float_round_nearest_even,
2707 float_round_to_zero,
2708 float_round_up,
2709 float_round_down
2710};
2711
2712target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2713{
2714 target_ulong arg1 = 0;
2715
2716 switch (reg) {
2717 case 0:
2718 arg1 = (int32_t)env->active_fpu.fcr0;
2719 break;
2720 case 1:
2721 /* UFR Support - Read Status FR */
2722 if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2723 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2724 arg1 = (int32_t)
2725 ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR);
2726 } else {
2727 do_raise_exception(env, EXCP_RI, GETPC());
2728 }
2729 }
2730 break;
2731 case 5:
2732 /* FRE Support - read Config5.FRE bit */
2733 if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
2734 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2735 arg1 = (env->CP0_Config5 >> CP0C5_FRE) & 1;
2736 } else {
2737 helper_raise_exception(env, EXCP_RI);
2738 }
2739 }
2740 break;
2741 case 25:
2742 arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2743 break;
2744 case 26:
2745 arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2746 break;
2747 case 28:
2748 arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2749 break;
2750 default:
2751 arg1 = (int32_t)env->active_fpu.fcr31;
2752 break;
2753 }
2754
2755 return arg1;
2756}
2757
2758void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2759{
2760 switch (fs) {
2761 case 1:
2762 /* UFR Alias - Reset Status FR */
2763 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2764 return;
2765 }
2766 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2767 env->CP0_Status &= ~(1 << CP0St_FR);
2768 compute_hflags(env);
2769 } else {
2770 do_raise_exception(env, EXCP_RI, GETPC());
2771 }
2772 break;
2773 case 4:
2774 /* UNFR Alias - Set Status FR */
2775 if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2776 return;
2777 }
2778 if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2779 env->CP0_Status |= (1 << CP0St_FR);
2780 compute_hflags(env);
2781 } else {
2782 do_raise_exception(env, EXCP_RI, GETPC());
2783 }
2784 break;
2785 case 5:
2786 /* FRE Support - clear Config5.FRE bit */
2787 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2788 return;
2789 }
2790 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2791 env->CP0_Config5 &= ~(1 << CP0C5_FRE);
2792 compute_hflags(env);
2793 } else {
2794 helper_raise_exception(env, EXCP_RI);
2795 }
2796 break;
2797 case 6:
2798 /* FRE Support - set Config5.FRE bit */
2799 if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt == 0))) {
2800 return;
2801 }
2802 if (env->CP0_Config5 & (1 << CP0C5_UFE)) {
2803 env->CP0_Config5 |= (1 << CP0C5_FRE);
2804 compute_hflags(env);
2805 } else {
2806 helper_raise_exception(env, EXCP_RI);
2807 }
2808 break;
2809 case 25:
2810 if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
2811 return;
2812 }
2813 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2814 ((arg1 & 0x1) << 23);
2815 break;
2816 case 26:
2817 if (arg1 & 0x007c0000)
2818 return;
2819 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2820 break;
2821 case 28:
2822 if (arg1 & 0x007c0000)
2823 return;
2824 env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2825 ((arg1 & 0x4) << 22);
2826 break;
2827 case 31:
2828 env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
2829 (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask));
2830 break;
2831 default:
2832 if (env->insn_flags & ISA_MIPS32R6) {
2833 do_raise_exception(env, EXCP_RI, GETPC());
2834 }
2835 return;
2836 }
2837 restore_fp_status(env);
2838 set_float_exception_flags(0, &env->active_fpu.fp_status);
2839 if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2840 do_raise_exception(env, EXCP_FPE, GETPC());
2841}
2842
2843int ieee_ex_to_mips(int xcpt)
2844{
2845 int ret = 0;
2846 if (xcpt) {
2847 if (xcpt & float_flag_invalid) {
2848 ret |= FP_INVALID;
2849 }
2850 if (xcpt & float_flag_overflow) {
2851 ret |= FP_OVERFLOW;
2852 }
2853 if (xcpt & float_flag_underflow) {
2854 ret |= FP_UNDERFLOW;
2855 }
2856 if (xcpt & float_flag_divbyzero) {
2857 ret |= FP_DIV0;
2858 }
2859 if (xcpt & float_flag_inexact) {
2860 ret |= FP_INEXACT;
2861 }
2862 }
2863 return ret;
2864}
2865
2866static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2867{
2868 int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2869
2870 SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2871
2872 if (tmp) {
2873 set_float_exception_flags(0, &env->active_fpu.fp_status);
2874
2875 if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2876 do_raise_exception(env, EXCP_FPE, pc);
2877 } else {
2878 UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2879 }
2880 }
2881}
2882
2883/* Float support.
2884 Single precition routines have a "s" suffix, double precision a
2885 "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2886 paired single lower "pl", paired single upper "pu". */
2887
2888/* unary operations, modifying fp status */
2889uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2890{
2891 fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2892 update_fcr31(env, GETPC());
2893 return fdt0;
2894}
2895
2896uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2897{
2898 fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2899 update_fcr31(env, GETPC());
2900 return fst0;
2901}
2902
2903uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2904{
2905 uint64_t fdt2;
2906
2907 fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2908 update_fcr31(env, GETPC());
2909 return fdt2;
2910}
2911
2912uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2913{
2914 uint64_t fdt2;
2915
2916 fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2917 update_fcr31(env, GETPC());
2918 return fdt2;
2919}
2920
2921uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2922{
2923 uint64_t fdt2;
2924
2925 fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2926 update_fcr31(env, GETPC());
2927 return fdt2;
2928}
2929
2930uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0)
2931{
2932 uint64_t dt2;
2933
2934 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2935 if (get_float_exception_flags(&env->active_fpu.fp_status)
2936 & (float_flag_invalid | float_flag_overflow)) {
2937 dt2 = FP_TO_INT64_OVERFLOW;
2938 }
2939 update_fcr31(env, GETPC());
2940 return dt2;
2941}
2942
2943uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0)
2944{
2945 uint64_t dt2;
2946
2947 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2948 if (get_float_exception_flags(&env->active_fpu.fp_status)
2949 & (float_flag_invalid | float_flag_overflow)) {
2950 dt2 = FP_TO_INT64_OVERFLOW;
2951 }
2952 update_fcr31(env, GETPC());
2953 return dt2;
2954}
2955
2956uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2957{
2958 uint32_t fst2;
2959 uint32_t fsth2;
2960
2961 fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2962 fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2963 update_fcr31(env, GETPC());
2964 return ((uint64_t)fsth2 << 32) | fst2;
2965}
2966
2967uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2968{
2969 uint32_t wt2;
2970 uint32_t wth2;
2971 int excp, excph;
2972
2973 wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2974 excp = get_float_exception_flags(&env->active_fpu.fp_status);
2975 if (excp & (float_flag_overflow | float_flag_invalid)) {
2976 wt2 = FP_TO_INT32_OVERFLOW;
2977 }
2978
2979 set_float_exception_flags(0, &env->active_fpu.fp_status);
2980 wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2981 excph = get_float_exception_flags(&env->active_fpu.fp_status);
2982 if (excph & (float_flag_overflow | float_flag_invalid)) {
2983 wth2 = FP_TO_INT32_OVERFLOW;
2984 }
2985
2986 set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2987 update_fcr31(env, GETPC());
2988
2989 return ((uint64_t)wth2 << 32) | wt2;
2990}
2991
2992uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2993{
2994 uint32_t fst2;
2995
2996 fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2997 update_fcr31(env, GETPC());
2998 return fst2;
2999}
3000
3001uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
3002{
3003 uint32_t fst2;
3004
3005 fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
3006 update_fcr31(env, GETPC());
3007 return fst2;
3008}
3009
3010uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
3011{
3012 uint32_t fst2;
3013
3014 fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
3015 update_fcr31(env, GETPC());
3016 return fst2;
3017}
3018
3019uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
3020{
3021 uint32_t wt2;
3022
3023 wt2 = wt0;
3024 update_fcr31(env, GETPC());
3025 return wt2;
3026}
3027
3028uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
3029{
3030 uint32_t wt2;
3031
3032 wt2 = wth0;
3033 update_fcr31(env, GETPC());
3034 return wt2;
3035}
3036
3037uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0)
3038{
3039 uint32_t wt2;
3040
3041 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3042 if (get_float_exception_flags(&env->active_fpu.fp_status)
3043 & (float_flag_invalid | float_flag_overflow)) {
3044 wt2 = FP_TO_INT32_OVERFLOW;
3045 }
3046 update_fcr31(env, GETPC());
3047 return wt2;
3048}
3049
3050uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0)
3051{
3052 uint32_t wt2;
3053
3054 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3055 if (get_float_exception_flags(&env->active_fpu.fp_status)
3056 & (float_flag_invalid | float_flag_overflow)) {
3057 wt2 = FP_TO_INT32_OVERFLOW;
3058 }
3059 update_fcr31(env, GETPC());
3060 return wt2;
3061}
3062
3063uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
3064{
3065 uint64_t dt2;
3066
3067 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3068 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3069 restore_rounding_mode(env);
3070 if (get_float_exception_flags(&env->active_fpu.fp_status)
3071 & (float_flag_invalid | float_flag_overflow)) {
3072 dt2 = FP_TO_INT64_OVERFLOW;
3073 }
3074 update_fcr31(env, GETPC());
3075 return dt2;
3076}
3077
3078uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
3079{
3080 uint64_t dt2;
3081
3082 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3083 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3084 restore_rounding_mode(env);
3085 if (get_float_exception_flags(&env->active_fpu.fp_status)
3086 & (float_flag_invalid | float_flag_overflow)) {
3087 dt2 = FP_TO_INT64_OVERFLOW;
3088 }
3089 update_fcr31(env, GETPC());
3090 return dt2;
3091}
3092
3093uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
3094{
3095 uint32_t wt2;
3096
3097 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3098 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3099 restore_rounding_mode(env);
3100 if (get_float_exception_flags(&env->active_fpu.fp_status)
3101 & (float_flag_invalid | float_flag_overflow)) {
3102 wt2 = FP_TO_INT32_OVERFLOW;
3103 }
3104 update_fcr31(env, GETPC());
3105 return wt2;
3106}
3107
3108uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
3109{
3110 uint32_t wt2;
3111
3112 set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
3113 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3114 restore_rounding_mode(env);
3115 if (get_float_exception_flags(&env->active_fpu.fp_status)
3116 & (float_flag_invalid | float_flag_overflow)) {
3117 wt2 = FP_TO_INT32_OVERFLOW;
3118 }
3119 update_fcr31(env, GETPC());
3120 return wt2;
3121}
3122
3123uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
3124{
3125 uint64_t dt2;
3126
3127 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3128 if (get_float_exception_flags(&env->active_fpu.fp_status)
3129 & (float_flag_invalid | float_flag_overflow)) {
3130 dt2 = FP_TO_INT64_OVERFLOW;
3131 }
3132 update_fcr31(env, GETPC());
3133 return dt2;
3134}
3135
3136uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0)
3137{
3138 uint64_t dt2;
3139
3140 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3141 if (get_float_exception_flags(&env->active_fpu.fp_status)
3142 & (float_flag_invalid | float_flag_overflow)) {
3143 dt2 = FP_TO_INT64_OVERFLOW;
3144 }
3145 update_fcr31(env, GETPC());
3146 return dt2;
3147}
3148
3149uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0)
3150{
3151 uint32_t wt2;
3152
3153 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3154 if (get_float_exception_flags(&env->active_fpu.fp_status)
3155 & (float_flag_invalid | float_flag_overflow)) {
3156 wt2 = FP_TO_INT32_OVERFLOW;
3157 }
3158 update_fcr31(env, GETPC());
3159 return wt2;
3160}
3161
3162uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0)
3163{
3164 uint32_t wt2;
3165
3166 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3167 if (get_float_exception_flags(&env->active_fpu.fp_status)
3168 & (float_flag_invalid | float_flag_overflow)) {
3169 wt2 = FP_TO_INT32_OVERFLOW;
3170 }
3171 update_fcr31(env, GETPC());
3172 return wt2;
3173}
3174
3175uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0)
3176{
3177 uint64_t dt2;
3178
3179 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3180 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3181 restore_rounding_mode(env);
3182 if (get_float_exception_flags(&env->active_fpu.fp_status)
3183 & (float_flag_invalid | float_flag_overflow)) {
3184 dt2 = FP_TO_INT64_OVERFLOW;
3185 }
3186 update_fcr31(env, GETPC());
3187 return dt2;
3188}
3189
3190uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0)
3191{
3192 uint64_t dt2;
3193
3194 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3195 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3196 restore_rounding_mode(env);
3197 if (get_float_exception_flags(&env->active_fpu.fp_status)
3198 & (float_flag_invalid | float_flag_overflow)) {
3199 dt2 = FP_TO_INT64_OVERFLOW;
3200 }
3201 update_fcr31(env, GETPC());
3202 return dt2;
3203}
3204
3205uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0)
3206{
3207 uint32_t wt2;
3208
3209 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3210 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3211 restore_rounding_mode(env);
3212 if (get_float_exception_flags(&env->active_fpu.fp_status)
3213 & (float_flag_invalid | float_flag_overflow)) {
3214 wt2 = FP_TO_INT32_OVERFLOW;
3215 }
3216 update_fcr31(env, GETPC());
3217 return wt2;
3218}
3219
3220uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0)
3221{
3222 uint32_t wt2;
3223
3224 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3225 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3226 restore_rounding_mode(env);
3227 if (get_float_exception_flags(&env->active_fpu.fp_status)
3228 & (float_flag_invalid | float_flag_overflow)) {
3229 wt2 = FP_TO_INT32_OVERFLOW;
3230 }
3231 update_fcr31(env, GETPC());
3232 return wt2;
3233}
3234
3235uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0)
3236{
3237 uint64_t dt2;
3238
3239 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3240 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3241 restore_rounding_mode(env);
3242 if (get_float_exception_flags(&env->active_fpu.fp_status)
3243 & (float_flag_invalid | float_flag_overflow)) {
3244 dt2 = FP_TO_INT64_OVERFLOW;
3245 }
3246 update_fcr31(env, GETPC());
3247 return dt2;
3248}
3249
3250uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0)
3251{
3252 uint64_t dt2;
3253
3254 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3255 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3256 restore_rounding_mode(env);
3257 if (get_float_exception_flags(&env->active_fpu.fp_status)
3258 & (float_flag_invalid | float_flag_overflow)) {
3259 dt2 = FP_TO_INT64_OVERFLOW;
3260 }
3261 update_fcr31(env, GETPC());
3262 return dt2;
3263}
3264
3265uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0)
3266{
3267 uint32_t wt2;
3268
3269 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3270 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3271 restore_rounding_mode(env);
3272 if (get_float_exception_flags(&env->active_fpu.fp_status)
3273 & (float_flag_invalid | float_flag_overflow)) {
3274 wt2 = FP_TO_INT32_OVERFLOW;
3275 }
3276 update_fcr31(env, GETPC());
3277 return wt2;
3278}
3279
3280uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0)
3281{
3282 uint32_t wt2;
3283
3284 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3285 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3286 restore_rounding_mode(env);
3287 if (get_float_exception_flags(&env->active_fpu.fp_status)
3288 & (float_flag_invalid | float_flag_overflow)) {
3289 wt2 = FP_TO_INT32_OVERFLOW;
3290 }
3291 update_fcr31(env, GETPC());
3292 return wt2;
3293}
3294
3295uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3296{
3297 uint64_t dt2;
3298
3299 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3300 if (get_float_exception_flags(&env->active_fpu.fp_status)
3301 & float_flag_invalid) {
3302 if (float64_is_any_nan(fdt0)) {
3303 dt2 = 0;
3304 }
3305 }
3306 update_fcr31(env, GETPC());
3307 return dt2;
3308}
3309
3310uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3311{
3312 uint64_t dt2;
3313
3314 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3315 if (get_float_exception_flags(&env->active_fpu.fp_status)
3316 & float_flag_invalid) {
3317 if (float32_is_any_nan(fst0)) {
3318 dt2 = 0;
3319 }
3320 }
3321 update_fcr31(env, GETPC());
3322 return dt2;
3323}
3324
3325uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3326{
3327 uint32_t wt2;
3328
3329 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3330 if (get_float_exception_flags(&env->active_fpu.fp_status)
3331 & float_flag_invalid) {
3332 if (float64_is_any_nan(fdt0)) {
3333 wt2 = 0;
3334 }
3335 }
3336 update_fcr31(env, GETPC());
3337 return wt2;
3338}
3339
3340uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3341{
3342 uint32_t wt2;
3343
3344 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3345 if (get_float_exception_flags(&env->active_fpu.fp_status)
3346 & float_flag_invalid) {
3347 if (float32_is_any_nan(fst0)) {
3348 wt2 = 0;
3349 }
3350 }
3351 update_fcr31(env, GETPC());
3352 return wt2;
3353}
3354
3355uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3356{
3357 uint64_t dt2;
3358
3359 set_float_rounding_mode(float_round_nearest_even,
3360 &env->active_fpu.fp_status);
3361 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3362 restore_rounding_mode(env);
3363 if (get_float_exception_flags(&env->active_fpu.fp_status)
3364 & float_flag_invalid) {
3365 if (float64_is_any_nan(fdt0)) {
3366 dt2 = 0;
3367 }
3368 }
3369 update_fcr31(env, GETPC());
3370 return dt2;
3371}
3372
3373uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3374{
3375 uint64_t dt2;
3376
3377 set_float_rounding_mode(float_round_nearest_even,
3378 &env->active_fpu.fp_status);
3379 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3380 restore_rounding_mode(env);
3381 if (get_float_exception_flags(&env->active_fpu.fp_status)
3382 & float_flag_invalid) {
3383 if (float32_is_any_nan(fst0)) {
3384 dt2 = 0;
3385 }
3386 }
3387 update_fcr31(env, GETPC());
3388 return dt2;
3389}
3390
3391uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3392{
3393 uint32_t wt2;
3394
3395 set_float_rounding_mode(float_round_nearest_even,
3396 &env->active_fpu.fp_status);
3397 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3398 restore_rounding_mode(env);
3399 if (get_float_exception_flags(&env->active_fpu.fp_status)
3400 & float_flag_invalid) {
3401 if (float64_is_any_nan(fdt0)) {
3402 wt2 = 0;
3403 }
3404 }
3405 update_fcr31(env, GETPC());
3406 return wt2;
3407}
3408
3409uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3410{
3411 uint32_t wt2;
3412
3413 set_float_rounding_mode(float_round_nearest_even,
3414 &env->active_fpu.fp_status);
3415 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3416 restore_rounding_mode(env);
3417 if (get_float_exception_flags(&env->active_fpu.fp_status)
3418 & float_flag_invalid) {
3419 if (float32_is_any_nan(fst0)) {
3420 wt2 = 0;
3421 }
3422 }
3423 update_fcr31(env, GETPC());
3424 return wt2;
3425}
3426
3427uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3428{
3429 uint64_t dt2;
3430
3431 dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
3432 if (get_float_exception_flags(&env->active_fpu.fp_status)
3433 & float_flag_invalid) {
3434 if (float64_is_any_nan(fdt0)) {
3435 dt2 = 0;
3436 }
3437 }
3438 update_fcr31(env, GETPC());
3439 return dt2;
3440}
3441
3442uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3443{
3444 uint64_t dt2;
3445
3446 dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
3447 if (get_float_exception_flags(&env->active_fpu.fp_status)
3448 & float_flag_invalid) {
3449 if (float32_is_any_nan(fst0)) {
3450 dt2 = 0;
3451 }
3452 }
3453 update_fcr31(env, GETPC());
3454 return dt2;
3455}
3456
3457uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3458{
3459 uint32_t wt2;
3460
3461 wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
3462 if (get_float_exception_flags(&env->active_fpu.fp_status)
3463 & float_flag_invalid) {
3464 if (float64_is_any_nan(fdt0)) {
3465 wt2 = 0;
3466 }
3467 }
3468 update_fcr31(env, GETPC());
3469 return wt2;
3470}
3471
3472uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3473{
3474 uint32_t wt2;
3475
3476 wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
3477 if (get_float_exception_flags(&env->active_fpu.fp_status)
3478 & float_flag_invalid) {
3479 if (float32_is_any_nan(fst0)) {
3480 wt2 = 0;
3481 }
3482 }
3483 update_fcr31(env, GETPC());
3484 return wt2;
3485}
3486
3487uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3488{
3489 uint64_t dt2;
3490
3491 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3492 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3493 restore_rounding_mode(env);
3494 if (get_float_exception_flags(&env->active_fpu.fp_status)
3495 & float_flag_invalid) {
3496 if (float64_is_any_nan(fdt0)) {
3497 dt2 = 0;
3498 }
3499 }
3500 update_fcr31(env, GETPC());
3501 return dt2;
3502}
3503
3504uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3505{
3506 uint64_t dt2;
3507
3508 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3509 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3510 restore_rounding_mode(env);
3511 if (get_float_exception_flags(&env->active_fpu.fp_status)
3512 & float_flag_invalid) {
3513 if (float32_is_any_nan(fst0)) {
3514 dt2 = 0;
3515 }
3516 }
3517 update_fcr31(env, GETPC());
3518 return dt2;
3519}
3520
3521uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3522{
3523 uint32_t wt2;
3524
3525 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3526 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3527 restore_rounding_mode(env);
3528 if (get_float_exception_flags(&env->active_fpu.fp_status)
3529 & float_flag_invalid) {
3530 if (float64_is_any_nan(fdt0)) {
3531 wt2 = 0;
3532 }
3533 }
3534 update_fcr31(env, GETPC());
3535 return wt2;
3536}
3537
3538uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3539{
3540 uint32_t wt2;
3541
3542 set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
3543 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3544 restore_rounding_mode(env);
3545 if (get_float_exception_flags(&env->active_fpu.fp_status)
3546 & float_flag_invalid) {
3547 if (float32_is_any_nan(fst0)) {
3548 wt2 = 0;
3549 }
3550 }
3551 update_fcr31(env, GETPC());
3552 return wt2;
3553}
3554
3555uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0)
3556{
3557 uint64_t dt2;
3558
3559 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3560 dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
3561 restore_rounding_mode(env);
3562 if (get_float_exception_flags(&env->active_fpu.fp_status)
3563 & float_flag_invalid) {
3564 if (float64_is_any_nan(fdt0)) {
3565 dt2 = 0;
3566 }
3567 }
3568 update_fcr31(env, GETPC());
3569 return dt2;
3570}
3571
3572uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0)
3573{
3574 uint64_t dt2;
3575
3576 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3577 dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
3578 restore_rounding_mode(env);
3579 if (get_float_exception_flags(&env->active_fpu.fp_status)
3580 & float_flag_invalid) {
3581 if (float32_is_any_nan(fst0)) {
3582 dt2 = 0;
3583 }
3584 }
3585 update_fcr31(env, GETPC());
3586 return dt2;
3587}
3588
3589uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0)
3590{
3591 uint32_t wt2;
3592
3593 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3594 wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
3595 restore_rounding_mode(env);
3596 if (get_float_exception_flags(&env->active_fpu.fp_status)
3597 & float_flag_invalid) {
3598 if (float64_is_any_nan(fdt0)) {
3599 wt2 = 0;
3600 }
3601 }
3602 update_fcr31(env, GETPC());
3603 return wt2;
3604}
3605
3606uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0)
3607{
3608 uint32_t wt2;
3609
3610 set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
3611 wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
3612 restore_rounding_mode(env);
3613 if (get_float_exception_flags(&env->active_fpu.fp_status)
3614 & float_flag_invalid) {
3615 if (float32_is_any_nan(fst0)) {
3616 wt2 = 0;
3617 }
3618 }
3619 update_fcr31(env, GETPC());
3620 return wt2;
3621}
3622
3623/* unary operations, not modifying fp status */
3624#define FLOAT_UNOP(name) \
3625uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \
3626{ \
3627 return float64_ ## name(fdt0); \
3628} \
3629uint32_t helper_float_ ## name ## _s(uint32_t fst0) \
3630{ \
3631 return float32_ ## name(fst0); \
3632} \
3633uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \
3634{ \
3635 uint32_t wt0; \
3636 uint32_t wth0; \
3637 \
3638 wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF); \
3639 wth0 = float32_ ## name(fdt0 >> 32); \
3640 return ((uint64_t)wth0 << 32) | wt0; \
3641}
3642FLOAT_UNOP(abs)
3643FLOAT_UNOP(chs)
3644#undef FLOAT_UNOP
3645
3646/* MIPS specific unary operations */
3647uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3648{
3649 uint64_t fdt2;
3650
3651 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3652 update_fcr31(env, GETPC());
3653 return fdt2;
3654}
3655
3656uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3657{
3658 uint32_t fst2;
3659
3660 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3661 update_fcr31(env, GETPC());
3662 return fst2;
3663}
3664
3665uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3666{
3667 uint64_t fdt2;
3668
3669 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3670 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3671 update_fcr31(env, GETPC());
3672 return fdt2;
3673}
3674
3675uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3676{
3677 uint32_t fst2;
3678
3679 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3680 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3681 update_fcr31(env, GETPC());
3682 return fst2;
3683}
3684
3685uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3686{
3687 uint64_t fdt2;
3688
3689 fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3690 update_fcr31(env, GETPC());
3691 return fdt2;
3692}
3693
3694uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3695{
3696 uint32_t fst2;
3697
3698 fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3699 update_fcr31(env, GETPC());
3700 return fst2;
3701}
3702
3703uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3704{
3705 uint32_t fst2;
3706 uint32_t fsth2;
3707
3708 fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3709 fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3710 update_fcr31(env, GETPC());
3711 return ((uint64_t)fsth2 << 32) | fst2;
3712}
3713
3714uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3715{
3716 uint64_t fdt2;
3717
3718 fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3719 fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3720 update_fcr31(env, GETPC());
3721 return fdt2;
3722}
3723
3724uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3725{
3726 uint32_t fst2;
3727
3728 fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3729 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3730 update_fcr31(env, GETPC());
3731 return fst2;
3732}
3733
3734uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3735{
3736 uint32_t fst2;
3737 uint32_t fsth2;
3738
3739 fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3740 fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3741 fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3742 fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3743 update_fcr31(env, GETPC());
3744 return ((uint64_t)fsth2 << 32) | fst2;
3745}
3746
3747#define FLOAT_RINT(name, bits) \
3748uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3749 uint ## bits ## _t fs) \
3750{ \
3751 uint ## bits ## _t fdret; \
3752 \
3753 fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
3754 update_fcr31(env, GETPC()); \
3755 return fdret; \
3756}
3757
3758FLOAT_RINT(rint_s, 32)
3759FLOAT_RINT(rint_d, 64)
3760#undef FLOAT_RINT
3761
3762#define FLOAT_CLASS_SIGNALING_NAN 0x001
3763#define FLOAT_CLASS_QUIET_NAN 0x002
3764#define FLOAT_CLASS_NEGATIVE_INFINITY 0x004
3765#define FLOAT_CLASS_NEGATIVE_NORMAL 0x008
3766#define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
3767#define FLOAT_CLASS_NEGATIVE_ZERO 0x020
3768#define FLOAT_CLASS_POSITIVE_INFINITY 0x040
3769#define FLOAT_CLASS_POSITIVE_NORMAL 0x080
3770#define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
3771#define FLOAT_CLASS_POSITIVE_ZERO 0x200
3772
3773#define FLOAT_CLASS(name, bits) \
3774uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
3775 float_status *status) \
3776{ \
3777 if (float ## bits ## _is_signaling_nan(arg, status)) { \
3778 return FLOAT_CLASS_SIGNALING_NAN; \
3779 } else if (float ## bits ## _is_quiet_nan(arg, status)) { \
3780 return FLOAT_CLASS_QUIET_NAN; \
3781 } else if (float ## bits ## _is_neg(arg)) { \
3782 if (float ## bits ## _is_infinity(arg)) { \
3783 return FLOAT_CLASS_NEGATIVE_INFINITY; \
3784 } else if (float ## bits ## _is_zero(arg)) { \
3785 return FLOAT_CLASS_NEGATIVE_ZERO; \
3786 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3787 return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \
3788 } else { \
3789 return FLOAT_CLASS_NEGATIVE_NORMAL; \
3790 } \
3791 } else { \
3792 if (float ## bits ## _is_infinity(arg)) { \
3793 return FLOAT_CLASS_POSITIVE_INFINITY; \
3794 } else if (float ## bits ## _is_zero(arg)) { \
3795 return FLOAT_CLASS_POSITIVE_ZERO; \
3796 } else if (float ## bits ## _is_zero_or_denormal(arg)) { \
3797 return FLOAT_CLASS_POSITIVE_SUBNORMAL; \
3798 } else { \
3799 return FLOAT_CLASS_POSITIVE_NORMAL; \
3800 } \
3801 } \
3802} \
3803 \
3804uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3805 uint ## bits ## _t arg) \
3806{ \
3807 return float_ ## name(arg, &env->active_fpu.fp_status); \
3808}
3809
3810FLOAT_CLASS(class_s, 32)
3811FLOAT_CLASS(class_d, 64)
3812#undef FLOAT_CLASS
3813
3814/* binary operations */
3815#define FLOAT_BINOP(name) \
3816uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3817 uint64_t fdt0, uint64_t fdt1) \
3818{ \
3819 uint64_t dt2; \
3820 \
3821 dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
3822 update_fcr31(env, GETPC()); \
3823 return dt2; \
3824} \
3825 \
3826uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
3827 uint32_t fst0, uint32_t fst1) \
3828{ \
3829 uint32_t wt2; \
3830 \
3831 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3832 update_fcr31(env, GETPC()); \
3833 return wt2; \
3834} \
3835 \
3836uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
3837 uint64_t fdt0, \
3838 uint64_t fdt1) \
3839{ \
3840 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
3841 uint32_t fsth0 = fdt0 >> 32; \
3842 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
3843 uint32_t fsth1 = fdt1 >> 32; \
3844 uint32_t wt2; \
3845 uint32_t wth2; \
3846 \
3847 wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
3848 wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
3849 update_fcr31(env, GETPC()); \
3850 return ((uint64_t)wth2 << 32) | wt2; \
3851}
3852
3853FLOAT_BINOP(add)
3854FLOAT_BINOP(sub)
3855FLOAT_BINOP(mul)
3856FLOAT_BINOP(div)
3857#undef FLOAT_BINOP
3858
3859/* MIPS specific binary operations */
3860uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3861{
3862 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3863 fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3864 update_fcr31(env, GETPC());
3865 return fdt2;
3866}
3867
3868uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3869{
3870 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3871 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3872 update_fcr31(env, GETPC());
3873 return fst2;
3874}
3875
3876uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3877{
3878 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3879 uint32_t fsth0 = fdt0 >> 32;
3880 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3881 uint32_t fsth2 = fdt2 >> 32;
3882
3883 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3884 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3885 fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3886 fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3887 update_fcr31(env, GETPC());
3888 return ((uint64_t)fsth2 << 32) | fst2;
3889}
3890
3891uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3892{
3893 fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3894 fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3895 fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3896 update_fcr31(env, GETPC());
3897 return fdt2;
3898}
3899
3900uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3901{
3902 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3903 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3904 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3905 update_fcr31(env, GETPC());
3906 return fst2;
3907}
3908
3909uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3910{
3911 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3912 uint32_t fsth0 = fdt0 >> 32;
3913 uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3914 uint32_t fsth2 = fdt2 >> 32;
3915
3916 fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3917 fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3918 fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3919 fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3920 fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3921 fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3922 update_fcr31(env, GETPC());
3923 return ((uint64_t)fsth2 << 32) | fst2;
3924}
3925
3926uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3927{
3928 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3929 uint32_t fsth0 = fdt0 >> 32;
3930 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3931 uint32_t fsth1 = fdt1 >> 32;
3932 uint32_t fst2;
3933 uint32_t fsth2;
3934
3935 fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3936 fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3937 update_fcr31(env, GETPC());
3938 return ((uint64_t)fsth2 << 32) | fst2;
3939}
3940
3941uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3942{
3943 uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3944 uint32_t fsth0 = fdt0 >> 32;
3945 uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3946 uint32_t fsth1 = fdt1 >> 32;
3947 uint32_t fst2;
3948 uint32_t fsth2;
3949
3950 fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3951 fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3952 update_fcr31(env, GETPC());
3953 return ((uint64_t)fsth2 << 32) | fst2;
3954}
3955
3956#define FLOAT_MINMAX(name, bits, minmaxfunc) \
3957uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
3958 uint ## bits ## _t fs, \
3959 uint ## bits ## _t ft) \
3960{ \
3961 uint ## bits ## _t fdret; \
3962 \
3963 fdret = float ## bits ## _ ## minmaxfunc(fs, ft, \
3964 &env->active_fpu.fp_status); \
3965 update_fcr31(env, GETPC()); \
3966 return fdret; \
3967}
3968
3969FLOAT_MINMAX(max_s, 32, maxnum)
3970FLOAT_MINMAX(max_d, 64, maxnum)
3971FLOAT_MINMAX(maxa_s, 32, maxnummag)
3972FLOAT_MINMAX(maxa_d, 64, maxnummag)
3973
3974FLOAT_MINMAX(min_s, 32, minnum)
3975FLOAT_MINMAX(min_d, 64, minnum)
3976FLOAT_MINMAX(mina_s, 32, minnummag)
3977FLOAT_MINMAX(mina_d, 64, minnummag)
3978#undef FLOAT_MINMAX
3979
3980/* ternary operations */
3981#define UNFUSED_FMA(prefix, a, b, c, flags) \
3982{ \
3983 a = prefix##_mul(a, b, &env->active_fpu.fp_status); \
3984 if ((flags) & float_muladd_negate_c) { \
3985 a = prefix##_sub(a, c, &env->active_fpu.fp_status); \
3986 } else { \
3987 a = prefix##_add(a, c, &env->active_fpu.fp_status); \
3988 } \
3989 if ((flags) & float_muladd_negate_result) { \
3990 a = prefix##_chs(a); \
3991 } \
3992}
3993
3994/* FMA based operations */
3995#define FLOAT_FMA(name, type) \
3996uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
3997 uint64_t fdt0, uint64_t fdt1, \
3998 uint64_t fdt2) \
3999{ \
4000 UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \
4001 update_fcr31(env, GETPC()); \
4002 return fdt0; \
4003} \
4004 \
4005uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
4006 uint32_t fst0, uint32_t fst1, \
4007 uint32_t fst2) \
4008{ \
4009 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4010 update_fcr31(env, GETPC()); \
4011 return fst0; \
4012} \
4013 \
4014uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
4015 uint64_t fdt0, uint64_t fdt1, \
4016 uint64_t fdt2) \
4017{ \
4018 uint32_t fst0 = fdt0 & 0XFFFFFFFF; \
4019 uint32_t fsth0 = fdt0 >> 32; \
4020 uint32_t fst1 = fdt1 & 0XFFFFFFFF; \
4021 uint32_t fsth1 = fdt1 >> 32; \
4022 uint32_t fst2 = fdt2 & 0XFFFFFFFF; \
4023 uint32_t fsth2 = fdt2 >> 32; \
4024 \
4025 UNFUSED_FMA(float32, fst0, fst1, fst2, type); \
4026 UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \
4027 update_fcr31(env, GETPC()); \
4028 return ((uint64_t)fsth0 << 32) | fst0; \
4029}
4030FLOAT_FMA(madd, 0)
4031FLOAT_FMA(msub, float_muladd_negate_c)
4032FLOAT_FMA(nmadd, float_muladd_negate_result)
4033FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
4034#undef FLOAT_FMA
4035
4036#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
4037uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
4038 uint ## bits ## _t fs, \
4039 uint ## bits ## _t ft, \
4040 uint ## bits ## _t fd) \
4041{ \
4042 uint ## bits ## _t fdret; \
4043 \
4044 fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg, \
4045 &env->active_fpu.fp_status); \
4046 update_fcr31(env, GETPC()); \
4047 return fdret; \
4048}
4049
4050FLOAT_FMADDSUB(maddf_s, 32, 0)
4051FLOAT_FMADDSUB(maddf_d, 64, 0)
4052FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
4053FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
4054#undef FLOAT_FMADDSUB
4055
4056/* compare operations */
4057#define FOP_COND_D(op, cond) \
4058void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4059 uint64_t fdt1, int cc) \
4060{ \
4061 int c; \
4062 c = cond; \
4063 update_fcr31(env, GETPC()); \
4064 if (c) \
4065 SET_FP_COND(cc, env->active_fpu); \
4066 else \
4067 CLEAR_FP_COND(cc, env->active_fpu); \
4068} \
4069void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4070 uint64_t fdt1, int cc) \
4071{ \
4072 int c; \
4073 fdt0 = float64_abs(fdt0); \
4074 fdt1 = float64_abs(fdt1); \
4075 c = cond; \
4076 update_fcr31(env, GETPC()); \
4077 if (c) \
4078 SET_FP_COND(cc, env->active_fpu); \
4079 else \
4080 CLEAR_FP_COND(cc, env->active_fpu); \
4081}
4082
4083/* NOTE: the comma operator will make "cond" to eval to false,
4084 * but float64_unordered_quiet() is still called. */
4085FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4086FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
4087FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4088FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4089FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4090FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4091FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4092FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
4093/* NOTE: the comma operator will make "cond" to eval to false,
4094 * but float64_unordered() is still called. */
4095FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4096FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
4097FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4098FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
4099FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4100FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
4101FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4102FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
4103
4104#define FOP_COND_S(op, cond) \
4105void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4106 uint32_t fst1, int cc) \
4107{ \
4108 int c; \
4109 c = cond; \
4110 update_fcr31(env, GETPC()); \
4111 if (c) \
4112 SET_FP_COND(cc, env->active_fpu); \
4113 else \
4114 CLEAR_FP_COND(cc, env->active_fpu); \
4115} \
4116void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
4117 uint32_t fst1, int cc) \
4118{ \
4119 int c; \
4120 fst0 = float32_abs(fst0); \
4121 fst1 = float32_abs(fst1); \
4122 c = cond; \
4123 update_fcr31(env, GETPC()); \
4124 if (c) \
4125 SET_FP_COND(cc, env->active_fpu); \
4126 else \
4127 CLEAR_FP_COND(cc, env->active_fpu); \
4128}
4129
4130/* NOTE: the comma operator will make "cond" to eval to false,
4131 * but float32_unordered_quiet() is still called. */
4132FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4133FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
4134FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4135FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
4136FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4137FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
4138FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4139FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
4140/* NOTE: the comma operator will make "cond" to eval to false,
4141 * but float32_unordered() is still called. */
4142FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4143FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
4144FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4145FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
4146FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4147FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
4148FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
4149FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
4150
4151#define FOP_COND_PS(op, condl, condh) \
4152void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4153 uint64_t fdt1, int cc) \
4154{ \
4155 uint32_t fst0, fsth0, fst1, fsth1; \
4156 int ch, cl; \
4157 fst0 = fdt0 & 0XFFFFFFFF; \
4158 fsth0 = fdt0 >> 32; \
4159 fst1 = fdt1 & 0XFFFFFFFF; \
4160 fsth1 = fdt1 >> 32; \
4161 cl = condl; \
4162 ch = condh; \
4163 update_fcr31(env, GETPC()); \
4164 if (cl) \
4165 SET_FP_COND(cc, env->active_fpu); \
4166 else \
4167 CLEAR_FP_COND(cc, env->active_fpu); \
4168 if (ch) \
4169 SET_FP_COND(cc + 1, env->active_fpu); \
4170 else \
4171 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4172} \
4173void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
4174 uint64_t fdt1, int cc) \
4175{ \
4176 uint32_t fst0, fsth0, fst1, fsth1; \
4177 int ch, cl; \
4178 fst0 = float32_abs(fdt0 & 0XFFFFFFFF); \
4179 fsth0 = float32_abs(fdt0 >> 32); \
4180 fst1 = float32_abs(fdt1 & 0XFFFFFFFF); \
4181 fsth1 = float32_abs(fdt1 >> 32); \
4182 cl = condl; \
4183 ch = condh; \
4184 update_fcr31(env, GETPC()); \
4185 if (cl) \
4186 SET_FP_COND(cc, env->active_fpu); \
4187 else \
4188 CLEAR_FP_COND(cc, env->active_fpu); \
4189 if (ch) \
4190 SET_FP_COND(cc + 1, env->active_fpu); \
4191 else \
4192 CLEAR_FP_COND(cc + 1, env->active_fpu); \
4193}
4194
4195/* NOTE: the comma operator will make "cond" to eval to false,
4196 * but float32_unordered_quiet() is still called. */
4197FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
4198 (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4199FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
4200 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
4201FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4202 float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4203FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
4204 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4205FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4206 float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4207FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
4208 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4209FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4210 float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4211FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
4212 float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
4213/* NOTE: the comma operator will make "cond" to eval to false,
4214 * but float32_unordered() is still called. */
4215FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
4216 (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
4217FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
4218 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
4219FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4220 float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4221FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
4222 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
4223FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4224 float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4225FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
4226 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
4227FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
4228 float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4229FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
4230 float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
4231
4232/* R6 compare operations */
4233#define FOP_CONDN_D(op, cond) \
4234uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
4235 uint64_t fdt1) \
4236{ \
4237 uint64_t c; \
4238 c = cond; \
4239 update_fcr31(env, GETPC()); \
4240 if (c) { \
4241 return -1; \
4242 } else { \
4243 return 0; \
4244 } \
4245}
4246
4247/* NOTE: the comma operator will make "cond" to eval to false,
4248 * but float64_unordered_quiet() is still called. */
4249FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4250FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
4251FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4252FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4253 || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4254FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4255FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4256 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4257FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4258FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4259 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4260/* NOTE: the comma operator will make "cond" to eval to false,
4261 * but float64_unordered() is still called. */
4262FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
4263FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
4264FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4265FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4266 || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
4267FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4268FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4269 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4270FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4271FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4272 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4273FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4274 || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4275FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4276 || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4277 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4278FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
4279 || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
4280FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
4281 || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
4282FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
4283 || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4284 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4285FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
4286 || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
4287
4288#define FOP_CONDN_S(op, cond) \
4289uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
4290 uint32_t fst1) \
4291{ \
4292 uint64_t c; \
4293 c = cond; \
4294 update_fcr31(env, GETPC()); \
4295 if (c) { \
4296 return -1; \
4297 } else { \
4298 return 0; \
4299 } \
4300}
4301
4302/* NOTE: the comma operator will make "cond" to eval to false,
4303 * but float32_unordered_quiet() is still called. */
4304FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
4305FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
4306FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4307FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4308 || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4309FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4310FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4311 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4312FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4313FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4314 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4315/* NOTE: the comma operator will make "cond" to eval to false,
4316 * but float32_unordered() is still called. */
4317FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
4318FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
4319FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4320FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4321 || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
4322FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4323FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4324 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4325FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4326FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4327 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4328FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
4329 || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4330FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
4331 || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4332 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4333FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
4334 || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
4335FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
4336 || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
4337FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
4338 || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4339 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4340FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
4341 || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
4342
4343/* MSA */
4344/* Data format min and max values */
4345#define DF_BITS(df) (1 << ((df) + 3))
4346
4347/* Element-by-element access macros */
4348#define DF_ELEMENTS(df) (MSA_WRLEN / DF_BITS(df))
4349
4350#if !defined(CONFIG_USER_ONLY)
4351#define MEMOP_IDX(DF) \
4352 TCGMemOpIdx oi = make_memop_idx(MO_TE | DF | MO_UNALN, \
4353 cpu_mmu_index(env, false));
4354#else
4355#define MEMOP_IDX(DF)
4356#endif
4357
4358void helper_msa_ld_b(CPUMIPSState *env, uint32_t wd,
4359 target_ulong addr)
4360{
4361 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4362 MEMOP_IDX(DF_BYTE)
4363#if !defined(CONFIG_USER_ONLY)
4364#if !defined(HOST_WORDS_BIGENDIAN)
4365 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
4366 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
4367 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
4368 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
4369 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
4370 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
4371 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
4372 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
4373 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
4374 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
4375 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
4376 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
4377 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
4378 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
4379 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
4380 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
4381#else
4382 pwd->b[0] = helper_ret_ldub_mmu(env, addr + (7 << DF_BYTE), oi, GETPC());
4383 pwd->b[1] = helper_ret_ldub_mmu(env, addr + (6 << DF_BYTE), oi, GETPC());
4384 pwd->b[2] = helper_ret_ldub_mmu(env, addr + (5 << DF_BYTE), oi, GETPC());
4385 pwd->b[3] = helper_ret_ldub_mmu(env, addr + (4 << DF_BYTE), oi, GETPC());
4386 pwd->b[4] = helper_ret_ldub_mmu(env, addr + (3 << DF_BYTE), oi, GETPC());
4387 pwd->b[5] = helper_ret_ldub_mmu(env, addr + (2 << DF_BYTE), oi, GETPC());
4388 pwd->b[6] = helper_ret_ldub_mmu(env, addr + (1 << DF_BYTE), oi, GETPC());
4389 pwd->b[7] = helper_ret_ldub_mmu(env, addr + (0 << DF_BYTE), oi, GETPC());
4390 pwd->b[8] = helper_ret_ldub_mmu(env, addr + (15 << DF_BYTE), oi, GETPC());
4391 pwd->b[9] = helper_ret_ldub_mmu(env, addr + (14 << DF_BYTE), oi, GETPC());
4392 pwd->b[10] = helper_ret_ldub_mmu(env, addr + (13 << DF_BYTE), oi, GETPC());
4393 pwd->b[11] = helper_ret_ldub_mmu(env, addr + (12 << DF_BYTE), oi, GETPC());
4394 pwd->b[12] = helper_ret_ldub_mmu(env, addr + (11 << DF_BYTE), oi, GETPC());
4395 pwd->b[13] = helper_ret_ldub_mmu(env, addr + (10 << DF_BYTE), oi, GETPC());
4396 pwd->b[14] = helper_ret_ldub_mmu(env, addr + (9 << DF_BYTE), oi, GETPC());
4397 pwd->b[15] = helper_ret_ldub_mmu(env, addr + (8 << DF_BYTE), oi, GETPC());
4398#endif
4399#else
4400#if !defined(HOST_WORDS_BIGENDIAN)
4401 pwd->b[0] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
4402 pwd->b[1] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
4403 pwd->b[2] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
4404 pwd->b[3] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
4405 pwd->b[4] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
4406 pwd->b[5] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
4407 pwd->b[6] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
4408 pwd->b[7] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
4409 pwd->b[8] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
4410 pwd->b[9] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
4411 pwd->b[10] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
4412 pwd->b[11] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
4413 pwd->b[12] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
4414 pwd->b[13] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
4415 pwd->b[14] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
4416 pwd->b[15] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
4417#else
4418 pwd->b[0] = cpu_ldub_data(env, addr + (7 << DF_BYTE));
4419 pwd->b[1] = cpu_ldub_data(env, addr + (6 << DF_BYTE));
4420 pwd->b[2] = cpu_ldub_data(env, addr + (5 << DF_BYTE));
4421 pwd->b[3] = cpu_ldub_data(env, addr + (4 << DF_BYTE));
4422 pwd->b[4] = cpu_ldub_data(env, addr + (3 << DF_BYTE));
4423 pwd->b[5] = cpu_ldub_data(env, addr + (2 << DF_BYTE));
4424 pwd->b[6] = cpu_ldub_data(env, addr + (1 << DF_BYTE));
4425 pwd->b[7] = cpu_ldub_data(env, addr + (0 << DF_BYTE));
4426 pwd->b[8] = cpu_ldub_data(env, addr + (15 << DF_BYTE));
4427 pwd->b[9] = cpu_ldub_data(env, addr + (14 << DF_BYTE));
4428 pwd->b[10] = cpu_ldub_data(env, addr + (13 << DF_BYTE));
4429 pwd->b[11] = cpu_ldub_data(env, addr + (12 << DF_BYTE));
4430 pwd->b[12] = cpu_ldub_data(env, addr + (11 << DF_BYTE));
4431 pwd->b[13] = cpu_ldub_data(env, addr + (10 << DF_BYTE));
4432 pwd->b[14] = cpu_ldub_data(env, addr + (9 << DF_BYTE));
4433 pwd->b[15] = cpu_ldub_data(env, addr + (8 << DF_BYTE));
4434#endif
4435#endif
4436}
4437
4438void helper_msa_ld_h(CPUMIPSState *env, uint32_t wd,
4439 target_ulong addr)
4440{
4441 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4442 MEMOP_IDX(DF_HALF)
4443#if !defined(CONFIG_USER_ONLY)
4444#if !defined(HOST_WORDS_BIGENDIAN)
4445 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
4446 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
4447 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
4448 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
4449 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
4450 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
4451 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
4452 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
4453#else
4454 pwd->h[0] = helper_ret_lduw_mmu(env, addr + (3 << DF_HALF), oi, GETPC());
4455 pwd->h[1] = helper_ret_lduw_mmu(env, addr + (2 << DF_HALF), oi, GETPC());
4456 pwd->h[2] = helper_ret_lduw_mmu(env, addr + (1 << DF_HALF), oi, GETPC());
4457 pwd->h[3] = helper_ret_lduw_mmu(env, addr + (0 << DF_HALF), oi, GETPC());
4458 pwd->h[4] = helper_ret_lduw_mmu(env, addr + (7 << DF_HALF), oi, GETPC());
4459 pwd->h[5] = helper_ret_lduw_mmu(env, addr + (6 << DF_HALF), oi, GETPC());
4460 pwd->h[6] = helper_ret_lduw_mmu(env, addr + (5 << DF_HALF), oi, GETPC());
4461 pwd->h[7] = helper_ret_lduw_mmu(env, addr + (4 << DF_HALF), oi, GETPC());
4462#endif
4463#else
4464#if !defined(HOST_WORDS_BIGENDIAN)
4465 pwd->h[0] = cpu_lduw_data(env, addr + (0 << DF_HALF));
4466 pwd->h[1] = cpu_lduw_data(env, addr + (1 << DF_HALF));
4467 pwd->h[2] = cpu_lduw_data(env, addr + (2 << DF_HALF));
4468 pwd->h[3] = cpu_lduw_data(env, addr + (3 << DF_HALF));
4469 pwd->h[4] = cpu_lduw_data(env, addr + (4 << DF_HALF));
4470 pwd->h[5] = cpu_lduw_data(env, addr + (5 << DF_HALF));
4471 pwd->h[6] = cpu_lduw_data(env, addr + (6 << DF_HALF));
4472 pwd->h[7] = cpu_lduw_data(env, addr + (7 << DF_HALF));
4473#else
4474 pwd->h[0] = cpu_lduw_data(env, addr + (3 << DF_HALF));
4475 pwd->h[1] = cpu_lduw_data(env, addr + (2 << DF_HALF));
4476 pwd->h[2] = cpu_lduw_data(env, addr + (1 << DF_HALF));
4477 pwd->h[3] = cpu_lduw_data(env, addr + (0 << DF_HALF));
4478 pwd->h[4] = cpu_lduw_data(env, addr + (7 << DF_HALF));
4479 pwd->h[5] = cpu_lduw_data(env, addr + (6 << DF_HALF));
4480 pwd->h[6] = cpu_lduw_data(env, addr + (5 << DF_HALF));
4481 pwd->h[7] = cpu_lduw_data(env, addr + (4 << DF_HALF));
4482#endif
4483#endif
4484}
4485
4486void helper_msa_ld_w(CPUMIPSState *env, uint32_t wd,
4487 target_ulong addr)
4488{
4489 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4490 MEMOP_IDX(DF_WORD)
4491#if !defined(CONFIG_USER_ONLY)
4492#if !defined(HOST_WORDS_BIGENDIAN)
4493 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
4494 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
4495 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
4496 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
4497#else
4498 pwd->w[0] = helper_ret_ldul_mmu(env, addr + (1 << DF_WORD), oi, GETPC());
4499 pwd->w[1] = helper_ret_ldul_mmu(env, addr + (0 << DF_WORD), oi, GETPC());
4500 pwd->w[2] = helper_ret_ldul_mmu(env, addr + (3 << DF_WORD), oi, GETPC());
4501 pwd->w[3] = helper_ret_ldul_mmu(env, addr + (2 << DF_WORD), oi, GETPC());
4502#endif
4503#else
4504#if !defined(HOST_WORDS_BIGENDIAN)
4505 pwd->w[0] = cpu_ldl_data(env, addr + (0 << DF_WORD));
4506 pwd->w[1] = cpu_ldl_data(env, addr + (1 << DF_WORD));
4507 pwd->w[2] = cpu_ldl_data(env, addr + (2 << DF_WORD));
4508 pwd->w[3] = cpu_ldl_data(env, addr + (3 << DF_WORD));
4509#else
4510 pwd->w[0] = cpu_ldl_data(env, addr + (1 << DF_WORD));
4511 pwd->w[1] = cpu_ldl_data(env, addr + (0 << DF_WORD));
4512 pwd->w[2] = cpu_ldl_data(env, addr + (3 << DF_WORD));
4513 pwd->w[3] = cpu_ldl_data(env, addr + (2 << DF_WORD));
4514#endif
4515#endif
4516}
4517
4518void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
4519 target_ulong addr)
4520{
4521 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4522 MEMOP_IDX(DF_DOUBLE)
4523#if !defined(CONFIG_USER_ONLY)
4524 pwd->d[0] = helper_ret_ldq_mmu(env, addr + (0 << DF_DOUBLE), oi, GETPC());
4525 pwd->d[1] = helper_ret_ldq_mmu(env, addr + (1 << DF_DOUBLE), oi, GETPC());
4526#else
4527 pwd->d[0] = cpu_ldq_data(env, addr + (0 << DF_DOUBLE));
4528 pwd->d[1] = cpu_ldq_data(env, addr + (1 << DF_DOUBLE));
4529#endif
4530}
4531
4532#define MSA_PAGESPAN(x) \
4533 ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
4534
4535static inline void ensure_writable_pages(CPUMIPSState *env,
4536 target_ulong addr,
4537 int mmu_idx,
4538 uintptr_t retaddr)
4539{
4540 /* FIXME: Probe the actual accesses (pass and use a size) */
4541 if (unlikely(MSA_PAGESPAN(addr))) {
4542 /* first page */
4543 probe_write(env, addr, 0, mmu_idx, retaddr);
4544 /* second page */
4545 addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
4546 probe_write(env, addr, 0, mmu_idx, retaddr);
4547 }
4548}
4549
4550void helper_msa_st_b(CPUMIPSState *env, uint32_t wd,
4551 target_ulong addr)
4552{
4553 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4554 int mmu_idx = cpu_mmu_index(env, false);
4555
4556 MEMOP_IDX(DF_BYTE)
4557 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4558#if !defined(CONFIG_USER_ONLY)
4559#if !defined(HOST_WORDS_BIGENDIAN)
4560 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[0], oi, GETPC());
4561 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[1], oi, GETPC());
4562 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[2], oi, GETPC());
4563 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[3], oi, GETPC());
4564 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[4], oi, GETPC());
4565 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[5], oi, GETPC());
4566 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[6], oi, GETPC());
4567 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[7], oi, GETPC());
4568 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[8], oi, GETPC());
4569 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[9], oi, GETPC());
4570 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[10], oi, GETPC());
4571 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[11], oi, GETPC());
4572 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[12], oi, GETPC());
4573 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[13], oi, GETPC());
4574 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[14], oi, GETPC());
4575 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[15], oi, GETPC());
4576#else
4577 helper_ret_stb_mmu(env, addr + (7 << DF_BYTE), pwd->b[0], oi, GETPC());
4578 helper_ret_stb_mmu(env, addr + (6 << DF_BYTE), pwd->b[1], oi, GETPC());
4579 helper_ret_stb_mmu(env, addr + (5 << DF_BYTE), pwd->b[2], oi, GETPC());
4580 helper_ret_stb_mmu(env, addr + (4 << DF_BYTE), pwd->b[3], oi, GETPC());
4581 helper_ret_stb_mmu(env, addr + (3 << DF_BYTE), pwd->b[4], oi, GETPC());
4582 helper_ret_stb_mmu(env, addr + (2 << DF_BYTE), pwd->b[5], oi, GETPC());
4583 helper_ret_stb_mmu(env, addr + (1 << DF_BYTE), pwd->b[6], oi, GETPC());
4584 helper_ret_stb_mmu(env, addr + (0 << DF_BYTE), pwd->b[7], oi, GETPC());
4585 helper_ret_stb_mmu(env, addr + (15 << DF_BYTE), pwd->b[8], oi, GETPC());
4586 helper_ret_stb_mmu(env, addr + (14 << DF_BYTE), pwd->b[9], oi, GETPC());
4587 helper_ret_stb_mmu(env, addr + (13 << DF_BYTE), pwd->b[10], oi, GETPC());
4588 helper_ret_stb_mmu(env, addr + (12 << DF_BYTE), pwd->b[11], oi, GETPC());
4589 helper_ret_stb_mmu(env, addr + (11 << DF_BYTE), pwd->b[12], oi, GETPC());
4590 helper_ret_stb_mmu(env, addr + (10 << DF_BYTE), pwd->b[13], oi, GETPC());
4591 helper_ret_stb_mmu(env, addr + (9 << DF_BYTE), pwd->b[14], oi, GETPC());
4592 helper_ret_stb_mmu(env, addr + (8 << DF_BYTE), pwd->b[15], oi, GETPC());
4593#endif
4594#else
4595#if !defined(HOST_WORDS_BIGENDIAN)
4596 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[0]);
4597 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[1]);
4598 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[2]);
4599 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[3]);
4600 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[4]);
4601 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[5]);
4602 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[6]);
4603 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[7]);
4604 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[8]);
4605 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[9]);
4606 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[10]);
4607 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[11]);
4608 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[12]);
4609 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[13]);
4610 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[14]);
4611 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[15]);
4612#else
4613 cpu_stb_data(env, addr + (7 << DF_BYTE), pwd->b[0]);
4614 cpu_stb_data(env, addr + (6 << DF_BYTE), pwd->b[1]);
4615 cpu_stb_data(env, addr + (5 << DF_BYTE), pwd->b[2]);
4616 cpu_stb_data(env, addr + (4 << DF_BYTE), pwd->b[3]);
4617 cpu_stb_data(env, addr + (3 << DF_BYTE), pwd->b[4]);
4618 cpu_stb_data(env, addr + (2 << DF_BYTE), pwd->b[5]);
4619 cpu_stb_data(env, addr + (1 << DF_BYTE), pwd->b[6]);
4620 cpu_stb_data(env, addr + (0 << DF_BYTE), pwd->b[7]);
4621 cpu_stb_data(env, addr + (15 << DF_BYTE), pwd->b[8]);
4622 cpu_stb_data(env, addr + (14 << DF_BYTE), pwd->b[9]);
4623 cpu_stb_data(env, addr + (13 << DF_BYTE), pwd->b[10]);
4624 cpu_stb_data(env, addr + (12 << DF_BYTE), pwd->b[11]);
4625 cpu_stb_data(env, addr + (11 << DF_BYTE), pwd->b[12]);
4626 cpu_stb_data(env, addr + (10 << DF_BYTE), pwd->b[13]);
4627 cpu_stb_data(env, addr + (9 << DF_BYTE), pwd->b[14]);
4628 cpu_stb_data(env, addr + (8 << DF_BYTE), pwd->b[15]);
4629#endif
4630#endif
4631}
4632
4633void helper_msa_st_h(CPUMIPSState *env, uint32_t wd,
4634 target_ulong addr)
4635{
4636 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4637 int mmu_idx = cpu_mmu_index(env, false);
4638
4639 MEMOP_IDX(DF_HALF)
4640 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4641#if !defined(CONFIG_USER_ONLY)
4642#if !defined(HOST_WORDS_BIGENDIAN)
4643 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[0], oi, GETPC());
4644 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[1], oi, GETPC());
4645 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[2], oi, GETPC());
4646 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[3], oi, GETPC());
4647 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[4], oi, GETPC());
4648 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[5], oi, GETPC());
4649 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[6], oi, GETPC());
4650 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[7], oi, GETPC());
4651#else
4652 helper_ret_stw_mmu(env, addr + (3 << DF_HALF), pwd->h[0], oi, GETPC());
4653 helper_ret_stw_mmu(env, addr + (2 << DF_HALF), pwd->h[1], oi, GETPC());
4654 helper_ret_stw_mmu(env, addr + (1 << DF_HALF), pwd->h[2], oi, GETPC());
4655 helper_ret_stw_mmu(env, addr + (0 << DF_HALF), pwd->h[3], oi, GETPC());
4656 helper_ret_stw_mmu(env, addr + (7 << DF_HALF), pwd->h[4], oi, GETPC());
4657 helper_ret_stw_mmu(env, addr + (6 << DF_HALF), pwd->h[5], oi, GETPC());
4658 helper_ret_stw_mmu(env, addr + (5 << DF_HALF), pwd->h[6], oi, GETPC());
4659 helper_ret_stw_mmu(env, addr + (4 << DF_HALF), pwd->h[7], oi, GETPC());
4660#endif
4661#else
4662#if !defined(HOST_WORDS_BIGENDIAN)
4663 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[0]);
4664 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[1]);
4665 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[2]);
4666 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[3]);
4667 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[4]);
4668 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[5]);
4669 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[6]);
4670 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[7]);
4671#else
4672 cpu_stw_data(env, addr + (3 << DF_HALF), pwd->h[0]);
4673 cpu_stw_data(env, addr + (2 << DF_HALF), pwd->h[1]);
4674 cpu_stw_data(env, addr + (1 << DF_HALF), pwd->h[2]);
4675 cpu_stw_data(env, addr + (0 << DF_HALF), pwd->h[3]);
4676 cpu_stw_data(env, addr + (7 << DF_HALF), pwd->h[4]);
4677 cpu_stw_data(env, addr + (6 << DF_HALF), pwd->h[5]);
4678 cpu_stw_data(env, addr + (5 << DF_HALF), pwd->h[6]);
4679 cpu_stw_data(env, addr + (4 << DF_HALF), pwd->h[7]);
4680#endif
4681#endif
4682}
4683
4684void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
4685 target_ulong addr)
4686{
4687 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4688 int mmu_idx = cpu_mmu_index(env, false);
4689
4690 MEMOP_IDX(DF_WORD)
4691 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4692#if !defined(CONFIG_USER_ONLY)
4693#if !defined(HOST_WORDS_BIGENDIAN)
4694 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
4695 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
4696 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
4697 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
4698#else
4699 helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
4700 helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
4701 helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
4702 helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
4703#endif
4704#else
4705#if !defined(HOST_WORDS_BIGENDIAN)
4706 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[0]);
4707 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[1]);
4708 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[2]);
4709 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[3]);
4710#else
4711 cpu_stl_data(env, addr + (1 << DF_WORD), pwd->w[0]);
4712 cpu_stl_data(env, addr + (0 << DF_WORD), pwd->w[1]);
4713 cpu_stl_data(env, addr + (3 << DF_WORD), pwd->w[2]);
4714 cpu_stl_data(env, addr + (2 << DF_WORD), pwd->w[3]);
4715#endif
4716#endif
4717}
4718
4719void helper_msa_st_d(CPUMIPSState *env, uint32_t wd,
4720 target_ulong addr)
4721{
4722 wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
4723 int mmu_idx = cpu_mmu_index(env, false);
4724
4725 MEMOP_IDX(DF_DOUBLE)
4726 ensure_writable_pages(env, addr, mmu_idx, GETPC());
4727#if !defined(CONFIG_USER_ONLY)
4728 helper_ret_stq_mmu(env, addr + (0 << DF_DOUBLE), pwd->d[0], oi, GETPC());
4729 helper_ret_stq_mmu(env, addr + (1 << DF_DOUBLE), pwd->d[1], oi, GETPC());
4730#else
4731 cpu_stq_data(env, addr + (0 << DF_DOUBLE), pwd->d[0]);
4732 cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]);
4733#endif
4734}
4735
4736void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op)
4737{
4738#ifndef CONFIG_USER_ONLY
4739 target_ulong index = addr & 0x1fffffff;
4740 if (op == 9) {
4741 /* Index Store Tag */
4742 memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo,
4743 MO_64, MEMTXATTRS_UNSPECIFIED);
4744 } else if (op == 5) {
4745 /* Index Load Tag */
4746 memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo,
4747 MO_64, MEMTXATTRS_UNSPECIFIED);
4748 }
4749#endif
4750}
4751