1 | /* |
2 | * MIPS emulation for qemu: CPU initialisation routines. |
3 | * |
4 | * Copyright (c) 2004-2005 Jocelyn Mayer |
5 | * Copyright (c) 2007 Herve Poussineau |
6 | * |
7 | * This library is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU Lesser General Public |
9 | * License as published by the Free Software Foundation; either |
10 | * version 2 of the License, or (at your option) any later version. |
11 | * |
12 | * This library is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
15 | * Lesser General Public License for more details. |
16 | * |
17 | * You should have received a copy of the GNU Lesser General Public |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
19 | */ |
20 | |
21 | /* CPU / CPU family specific config register values. */ |
22 | |
23 | /* Have config1, uncached coherency */ |
24 | #define MIPS_CONFIG0 \ |
25 | ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) |
26 | |
27 | /* Have config2, no coprocessor2 attached, no MDMX support attached, |
28 | no performance counters, watch registers present, |
29 | no code compression, EJTAG present, no FPU */ |
30 | #define MIPS_CONFIG1 \ |
31 | ((1U << CP0C1_M) | \ |
32 | (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ |
33 | (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ |
34 | (0 << CP0C1_FP)) |
35 | |
36 | /* Have config3, no tertiary/secondary caches implemented */ |
37 | #define MIPS_CONFIG2 \ |
38 | ((1U << CP0C2_M)) |
39 | |
40 | /* No config4, no DSP ASE, no large physaddr (PABITS), |
41 | no external interrupt controller, no vectored interrupts, |
42 | no 1kb pages, no SmartMIPS ASE, no trace logic */ |
43 | #define MIPS_CONFIG3 \ |
44 | ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
45 | (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
46 | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
47 | |
48 | #define MIPS_CONFIG4 \ |
49 | ((0 << CP0C4_M)) |
50 | |
51 | #define MIPS_CONFIG5 \ |
52 | ((0 << CP0C5_M)) |
53 | |
54 | /*****************************************************************************/ |
55 | /* MIPS CPU definitions */ |
56 | const mips_def_t mips_defs[] = |
57 | { |
58 | { |
59 | .name = "4Kc" , |
60 | .CP0_PRid = 0x00018000, |
61 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
62 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
63 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
64 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
65 | (0 << CP0C1_CA), |
66 | .CP0_Config2 = MIPS_CONFIG2, |
67 | .CP0_Config3 = MIPS_CONFIG3, |
68 | .CP0_LLAddr_rw_bitmask = 0, |
69 | .CP0_LLAddr_shift = 4, |
70 | .SYNCI_Step = 32, |
71 | .CCRes = 2, |
72 | .CP0_Status_rw_bitmask = 0x1278FF17, |
73 | .SEGBITS = 32, |
74 | .PABITS = 32, |
75 | .insn_flags = CPU_MIPS32, |
76 | .mmu_type = MMU_TYPE_R4000, |
77 | }, |
78 | { |
79 | .name = "4Km" , |
80 | .CP0_PRid = 0x00018300, |
81 | /* Config1 implemented, fixed mapping MMU, |
82 | no virtual icache, uncached coherency. */ |
83 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
84 | .CP0_Config1 = MIPS_CONFIG1 | |
85 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
86 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
87 | (1 << CP0C1_CA), |
88 | .CP0_Config2 = MIPS_CONFIG2, |
89 | .CP0_Config3 = MIPS_CONFIG3, |
90 | .CP0_LLAddr_rw_bitmask = 0, |
91 | .CP0_LLAddr_shift = 4, |
92 | .SYNCI_Step = 32, |
93 | .CCRes = 2, |
94 | .CP0_Status_rw_bitmask = 0x1258FF17, |
95 | .SEGBITS = 32, |
96 | .PABITS = 32, |
97 | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
98 | .mmu_type = MMU_TYPE_FMT, |
99 | }, |
100 | { |
101 | .name = "4KEcR1" , |
102 | .CP0_PRid = 0x00018400, |
103 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT), |
104 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
105 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
106 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
107 | (0 << CP0C1_CA), |
108 | .CP0_Config2 = MIPS_CONFIG2, |
109 | .CP0_Config3 = MIPS_CONFIG3, |
110 | .CP0_LLAddr_rw_bitmask = 0, |
111 | .CP0_LLAddr_shift = 4, |
112 | .SYNCI_Step = 32, |
113 | .CCRes = 2, |
114 | .CP0_Status_rw_bitmask = 0x1278FF17, |
115 | .SEGBITS = 32, |
116 | .PABITS = 32, |
117 | .insn_flags = CPU_MIPS32, |
118 | .mmu_type = MMU_TYPE_R4000, |
119 | }, |
120 | { |
121 | .name = "4KEmR1" , |
122 | .CP0_PRid = 0x00018500, |
123 | .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT), |
124 | .CP0_Config1 = MIPS_CONFIG1 | |
125 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
126 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
127 | (1 << CP0C1_CA), |
128 | .CP0_Config2 = MIPS_CONFIG2, |
129 | .CP0_Config3 = MIPS_CONFIG3, |
130 | .CP0_LLAddr_rw_bitmask = 0, |
131 | .CP0_LLAddr_shift = 4, |
132 | .SYNCI_Step = 32, |
133 | .CCRes = 2, |
134 | .CP0_Status_rw_bitmask = 0x1258FF17, |
135 | .SEGBITS = 32, |
136 | .PABITS = 32, |
137 | .insn_flags = CPU_MIPS32 | ASE_MIPS16, |
138 | .mmu_type = MMU_TYPE_FMT, |
139 | }, |
140 | { |
141 | .name = "4KEc" , |
142 | .CP0_PRid = 0x00019000, |
143 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
144 | (MMU_TYPE_R4000 << CP0C0_MT), |
145 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
146 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
147 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
148 | (0 << CP0C1_CA), |
149 | .CP0_Config2 = MIPS_CONFIG2, |
150 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
151 | .CP0_LLAddr_rw_bitmask = 0, |
152 | .CP0_LLAddr_shift = 4, |
153 | .SYNCI_Step = 32, |
154 | .CCRes = 2, |
155 | .CP0_Status_rw_bitmask = 0x1278FF17, |
156 | .SEGBITS = 32, |
157 | .PABITS = 32, |
158 | .insn_flags = CPU_MIPS32R2, |
159 | .mmu_type = MMU_TYPE_R4000, |
160 | }, |
161 | { |
162 | .name = "4KEm" , |
163 | .CP0_PRid = 0x00019100, |
164 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
165 | (MMU_TYPE_FMT << CP0C0_MT), |
166 | .CP0_Config1 = MIPS_CONFIG1 | |
167 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
168 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
169 | (1 << CP0C1_CA), |
170 | .CP0_Config2 = MIPS_CONFIG2, |
171 | .CP0_Config3 = MIPS_CONFIG3, |
172 | .CP0_LLAddr_rw_bitmask = 0, |
173 | .CP0_LLAddr_shift = 4, |
174 | .SYNCI_Step = 32, |
175 | .CCRes = 2, |
176 | .CP0_Status_rw_bitmask = 0x1258FF17, |
177 | .SEGBITS = 32, |
178 | .PABITS = 32, |
179 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
180 | .mmu_type = MMU_TYPE_FMT, |
181 | }, |
182 | { |
183 | .name = "24Kc" , |
184 | .CP0_PRid = 0x00019300, |
185 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
186 | (MMU_TYPE_R4000 << CP0C0_MT), |
187 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
188 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
189 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
190 | (1 << CP0C1_CA), |
191 | .CP0_Config2 = MIPS_CONFIG2, |
192 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
193 | .CP0_LLAddr_rw_bitmask = 0, |
194 | .CP0_LLAddr_shift = 4, |
195 | .SYNCI_Step = 32, |
196 | .CCRes = 2, |
197 | /* No DSP implemented. */ |
198 | .CP0_Status_rw_bitmask = 0x1278FF1F, |
199 | .SEGBITS = 32, |
200 | .PABITS = 32, |
201 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
202 | .mmu_type = MMU_TYPE_R4000, |
203 | }, |
204 | { |
205 | .name = "24KEc" , |
206 | .CP0_PRid = 0x00019600, |
207 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
208 | (MMU_TYPE_R4000 << CP0C0_MT), |
209 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
210 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
211 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
212 | (1 << CP0C1_CA), |
213 | .CP0_Config2 = MIPS_CONFIG2, |
214 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSPP) | (0 << CP0C3_VInt), |
215 | .CP0_LLAddr_rw_bitmask = 0, |
216 | .CP0_LLAddr_shift = 4, |
217 | .SYNCI_Step = 32, |
218 | .CCRes = 2, |
219 | /* we have a DSP, but no FPU */ |
220 | .CP0_Status_rw_bitmask = 0x1378FF1F, |
221 | .SEGBITS = 32, |
222 | .PABITS = 32, |
223 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP, |
224 | .mmu_type = MMU_TYPE_R4000, |
225 | }, |
226 | { |
227 | .name = "24Kf" , |
228 | .CP0_PRid = 0x00019300, |
229 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
230 | (MMU_TYPE_R4000 << CP0C0_MT), |
231 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
232 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
233 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
234 | (1 << CP0C1_CA), |
235 | .CP0_Config2 = MIPS_CONFIG2, |
236 | .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt), |
237 | .CP0_LLAddr_rw_bitmask = 0, |
238 | .CP0_LLAddr_shift = 4, |
239 | .SYNCI_Step = 32, |
240 | .CCRes = 2, |
241 | /* No DSP implemented. */ |
242 | .CP0_Status_rw_bitmask = 0x3678FF1F, |
243 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
244 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
245 | .CP1_fcr31 = 0, |
246 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
247 | .SEGBITS = 32, |
248 | .PABITS = 32, |
249 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16, |
250 | .mmu_type = MMU_TYPE_R4000, |
251 | }, |
252 | { |
253 | .name = "34Kf" , |
254 | .CP0_PRid = 0x00019500, |
255 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
256 | (MMU_TYPE_R4000 << CP0C0_MT), |
257 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
258 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
259 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
260 | (1 << CP0C1_CA), |
261 | .CP0_Config2 = MIPS_CONFIG2, |
262 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) | |
263 | (1 << CP0C3_DSPP), |
264 | .CP0_LLAddr_rw_bitmask = 0, |
265 | .CP0_LLAddr_shift = 0, |
266 | .SYNCI_Step = 32, |
267 | .CCRes = 2, |
268 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
269 | .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) | |
270 | (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) | |
271 | (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) | |
272 | (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) | |
273 | (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) | |
274 | (0xff << CP0TCSt_TASID), |
275 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
276 | (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), |
277 | .CP1_fcr31 = 0, |
278 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
279 | .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), |
280 | .CP0_SRSConf0_rw_bitmask = 0x3fffffff, |
281 | .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | |
282 | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), |
283 | .CP0_SRSConf1_rw_bitmask = 0x3fffffff, |
284 | .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | |
285 | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), |
286 | .CP0_SRSConf2_rw_bitmask = 0x3fffffff, |
287 | .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | |
288 | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), |
289 | .CP0_SRSConf3_rw_bitmask = 0x3fffffff, |
290 | .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | |
291 | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), |
292 | .CP0_SRSConf4_rw_bitmask = 0x3fffffff, |
293 | .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | |
294 | (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), |
295 | .SEGBITS = 32, |
296 | .PABITS = 32, |
297 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, |
298 | .mmu_type = MMU_TYPE_R4000, |
299 | }, |
300 | { |
301 | .name = "74Kf" , |
302 | .CP0_PRid = 0x00019700, |
303 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
304 | (MMU_TYPE_R4000 << CP0C0_MT), |
305 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
306 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
307 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | |
308 | (1 << CP0C1_CA), |
309 | .CP0_Config2 = MIPS_CONFIG2, |
310 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | |
311 | (1 << CP0C3_VInt), |
312 | .CP0_LLAddr_rw_bitmask = 0, |
313 | .CP0_LLAddr_shift = 4, |
314 | .SYNCI_Step = 32, |
315 | .CCRes = 2, |
316 | .CP0_Status_rw_bitmask = 0x3778FF1F, |
317 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
318 | (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), |
319 | .CP1_fcr31 = 0, |
320 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
321 | .SEGBITS = 32, |
322 | .PABITS = 32, |
323 | .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2, |
324 | .mmu_type = MMU_TYPE_R4000, |
325 | }, |
326 | { |
327 | .name = "M14K" , |
328 | .CP0_PRid = 0x00019b00, |
329 | /* Config1 implemented, fixed mapping MMU, |
330 | no virtual icache, uncached coherency. */ |
331 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) | |
332 | (0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT), |
333 | .CP0_Config1 = MIPS_CONFIG1, |
334 | .CP0_Config2 = MIPS_CONFIG2, |
335 | .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt), |
336 | .CP0_LLAddr_rw_bitmask = 0, |
337 | .CP0_LLAddr_shift = 4, |
338 | .SYNCI_Step = 32, |
339 | .CCRes = 2, |
340 | .CP0_Status_rw_bitmask = 0x1258FF17, |
341 | .SEGBITS = 32, |
342 | .PABITS = 32, |
343 | .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, |
344 | .mmu_type = MMU_TYPE_FMT, |
345 | }, |
346 | { |
347 | .name = "M14Kc" , |
348 | /* This is the TLB-based MMU core. */ |
349 | .CP0_PRid = 0x00019c00, |
350 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | |
351 | (MMU_TYPE_R4000 << CP0C0_MT), |
352 | .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) | |
353 | (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | |
354 | (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA), |
355 | .CP0_Config2 = MIPS_CONFIG2, |
356 | .CP0_Config3 = MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt), |
357 | .CP0_LLAddr_rw_bitmask = 0, |
358 | .CP0_LLAddr_shift = 4, |
359 | .SYNCI_Step = 32, |
360 | .CCRes = 2, |
361 | .CP0_Status_rw_bitmask = 0x1278FF17, |
362 | .SEGBITS = 32, |
363 | .PABITS = 32, |
364 | .insn_flags = CPU_MIPS32R2 | ASE_MICROMIPS, |
365 | .mmu_type = MMU_TYPE_R4000, |
366 | }, |
367 | { |
368 | /* FIXME: |
369 | * Config3: CMGCR, PW, VZ, CTXTC, CDMM, TL |
370 | * Config4: MMUExtDef |
371 | * Config5: MRP |
372 | * FIR(FCR0): Has2008 |
373 | * */ |
374 | .name = "P5600" , |
375 | .CP0_PRid = 0x0001A800, |
376 | .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (1 << CP0C0_AR) | |
377 | (MMU_TYPE_R4000 << CP0C0_MT), |
378 | .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | |
379 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
380 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
381 | (1 << CP0C1_PC) | (1 << CP0C1_FP), |
382 | .CP0_Config2 = MIPS_CONFIG2, |
383 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | |
384 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) | |
385 | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | |
386 | (1 << CP0C3_VInt), |
387 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) | |
388 | (0x1c << CP0C4_KScrExist), |
389 | .CP0_Config4_rw_bitmask = 0, |
390 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) | |
391 | (1 << CP0C5_LLB) | (1 << CP0C5_MRP), |
392 | .CP0_Config5_rw_bitmask = (1 << CP0C5_K) | (1 << CP0C5_CV) | |
393 | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) | |
394 | (1 << CP0C5_FRE) | (1 << CP0C5_UFR), |
395 | .CP0_LLAddr_rw_bitmask = 0, |
396 | .CP0_LLAddr_shift = 0, |
397 | .SYNCI_Step = 32, |
398 | .CCRes = 2, |
399 | .CP0_Status_rw_bitmask = 0x3C68FF1F, |
400 | .CP0_PageGrain_rw_bitmask = (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | |
401 | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC), |
402 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
403 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_UFRP) | (1 << FCR0_HAS2008) | |
404 | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
405 | (1 << FCR0_D) | (1 << FCR0_S) | (0x03 << FCR0_PRID), |
406 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
407 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
408 | .SEGBITS = 32, |
409 | .PABITS = 40, |
410 | .insn_flags = CPU_MIPS32R5 | ASE_MSA, |
411 | .mmu_type = MMU_TYPE_R4000, |
412 | }, |
413 | { |
414 | /* A generic CPU supporting MIPS32 Release 6 ISA. |
415 | FIXME: Support IEEE 754-2008 FP. |
416 | Eventually this should be replaced by a real CPU model. */ |
417 | .name = "mips32r6-generic" , |
418 | .CP0_PRid = 0x00010000, |
419 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | |
420 | (MMU_TYPE_R4000 << CP0C0_MT), |
421 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
422 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
423 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
424 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
425 | .CP0_Config2 = MIPS_CONFIG2, |
426 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | |
427 | (2 << CP0C3_ISA) | (1 << CP0C3_ULRI) | |
428 | (1 << CP0C3_RXI) | (1U << CP0C3_M), |
429 | .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | |
430 | (3 << CP0C4_IE) | (1U << CP0C4_M), |
431 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB), |
432 | .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | |
433 | (1 << CP0C5_UFE), |
434 | .CP0_LLAddr_rw_bitmask = 0, |
435 | .CP0_LLAddr_shift = 0, |
436 | .SYNCI_Step = 32, |
437 | .CCRes = 2, |
438 | .CP0_Status_rw_bitmask = 0x3058FF1F, |
439 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
440 | (1U << CP0PG_RIE), |
441 | .CP0_PageGrain_rw_bitmask = 0, |
442 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
443 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
444 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
445 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
446 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
447 | .SEGBITS = 32, |
448 | .PABITS = 32, |
449 | .insn_flags = CPU_MIPS32R6 | ASE_MICROMIPS, |
450 | .mmu_type = MMU_TYPE_R4000, |
451 | }, |
452 | { |
453 | .name = "I7200" , |
454 | .CP0_PRid = 0x00010000, |
455 | .CP0_Config0 = MIPS_CONFIG0 | (1 << CP0C0_MM) | (0x2 << CP0C0_AR) | |
456 | (MMU_TYPE_R4000 << CP0C0_MT), |
457 | .CP0_Config1 = (1U << CP0C1_M) | (15 << CP0C1_MMU) | (2 << CP0C1_IS) | |
458 | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_DS) | |
459 | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | |
460 | (1 << CP0C1_EP), |
461 | .CP0_Config2 = MIPS_CONFIG2, |
462 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | |
463 | (1 << CP0C3_BI) | (1 << CP0C3_SC) | (3 << CP0C3_MMAR) | |
464 | (1 << CP0C3_ISA_ON_EXC) | (1 << CP0C3_ISA) | |
465 | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | |
466 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | |
467 | (1 << CP0C3_CTXTC) | (1 << CP0C3_VInt) | |
468 | (1 << CP0C3_CDMM) | (1 << CP0C3_MT) | (1 << CP0C3_TL), |
469 | .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | |
470 | (2 << CP0C4_IE) | (1U << CP0C4_M), |
471 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB), |
472 | .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | |
473 | (1 << CP0C5_UFE), |
474 | .CP0_LLAddr_rw_bitmask = 0, |
475 | .CP0_LLAddr_shift = 0, |
476 | .SYNCI_Step = 32, |
477 | .CCRes = 2, |
478 | .CP0_Status_rw_bitmask = 0x3158FF1F, |
479 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
480 | (1U << CP0PG_RIE), |
481 | .CP0_PageGrain_rw_bitmask = 0, |
482 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
483 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
484 | (1 << FCR0_S) | (0x02 << FCR0_PRID) | (0x0 << FCR0_REV), |
485 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
486 | .SEGBITS = 32, |
487 | .PABITS = 32, |
488 | .insn_flags = CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | |
489 | ASE_MT, |
490 | .mmu_type = MMU_TYPE_R4000, |
491 | }, |
492 | #if defined(TARGET_MIPS64) |
493 | { |
494 | .name = "R4000" , |
495 | .CP0_PRid = 0x00000400, |
496 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
497 | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
498 | /* Note: Config1 is only used internally, the R4000 has only Config0. */ |
499 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
500 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF, |
501 | .CP0_LLAddr_shift = 4, |
502 | .SYNCI_Step = 16, |
503 | .CCRes = 2, |
504 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
505 | /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
506 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV), |
507 | .CP1_fcr31 = 0, |
508 | .CP1_fcr31_rw_bitmask = 0x0183FFFF, |
509 | .SEGBITS = 40, |
510 | .PABITS = 36, |
511 | .insn_flags = CPU_MIPS3, |
512 | .mmu_type = MMU_TYPE_R4000, |
513 | }, |
514 | { |
515 | .name = "VR5432" , |
516 | .CP0_PRid = 0x00005400, |
517 | /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */ |
518 | .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), |
519 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
520 | .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL, |
521 | .CP0_LLAddr_shift = 4, |
522 | .SYNCI_Step = 16, |
523 | .CCRes = 2, |
524 | .CP0_Status_rw_bitmask = 0x3678FFFF, |
525 | /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ |
526 | .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV), |
527 | .CP1_fcr31 = 0, |
528 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
529 | .SEGBITS = 40, |
530 | .PABITS = 32, |
531 | .insn_flags = CPU_VR54XX, |
532 | .mmu_type = MMU_TYPE_R4000, |
533 | }, |
534 | { |
535 | .name = "5Kc" , |
536 | .CP0_PRid = 0x00018100, |
537 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
538 | (MMU_TYPE_R4000 << CP0C0_MT), |
539 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
540 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
541 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
542 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
543 | .CP0_Config2 = MIPS_CONFIG2, |
544 | .CP0_Config3 = MIPS_CONFIG3, |
545 | .CP0_LLAddr_rw_bitmask = 0, |
546 | .CP0_LLAddr_shift = 4, |
547 | .SYNCI_Step = 32, |
548 | .CCRes = 2, |
549 | .CP0_Status_rw_bitmask = 0x12F8FFFF, |
550 | .SEGBITS = 42, |
551 | .PABITS = 36, |
552 | .insn_flags = CPU_MIPS64, |
553 | .mmu_type = MMU_TYPE_R4000, |
554 | }, |
555 | { |
556 | .name = "5Kf" , |
557 | .CP0_PRid = 0x00018100, |
558 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
559 | (MMU_TYPE_R4000 << CP0C0_MT), |
560 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
561 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
562 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
563 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
564 | .CP0_Config2 = MIPS_CONFIG2, |
565 | .CP0_Config3 = MIPS_CONFIG3, |
566 | .CP0_LLAddr_rw_bitmask = 0, |
567 | .CP0_LLAddr_shift = 4, |
568 | .SYNCI_Step = 32, |
569 | .CCRes = 2, |
570 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
571 | /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ |
572 | .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) | |
573 | (0x81 << FCR0_PRID) | (0x0 << FCR0_REV), |
574 | .CP1_fcr31 = 0, |
575 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
576 | .SEGBITS = 42, |
577 | .PABITS = 36, |
578 | .insn_flags = CPU_MIPS64, |
579 | .mmu_type = MMU_TYPE_R4000, |
580 | }, |
581 | { |
582 | .name = "20Kc" , |
583 | /* We emulate a later version of the 20Kc, earlier ones had a broken |
584 | WAIT instruction. */ |
585 | .CP0_PRid = 0x000182a0, |
586 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) | |
587 | (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), |
588 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | |
589 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
590 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
591 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
592 | .CP0_Config2 = MIPS_CONFIG2, |
593 | .CP0_Config3 = MIPS_CONFIG3, |
594 | .CP0_LLAddr_rw_bitmask = 0, |
595 | .CP0_LLAddr_shift = 0, |
596 | .SYNCI_Step = 32, |
597 | .CCRes = 1, |
598 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
599 | /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ |
600 | .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) | |
601 | (1 << FCR0_D) | (1 << FCR0_S) | |
602 | (0x82 << FCR0_PRID) | (0x0 << FCR0_REV), |
603 | .CP1_fcr31 = 0, |
604 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
605 | .SEGBITS = 40, |
606 | .PABITS = 36, |
607 | .insn_flags = CPU_MIPS64 | ASE_MIPS3D, |
608 | .mmu_type = MMU_TYPE_R4000, |
609 | }, |
610 | { |
611 | /* A generic CPU providing MIPS64 Release 2 features. |
612 | FIXME: Eventually this should be replaced by a real CPU model. */ |
613 | .name = "MIPS64R2-generic" , |
614 | .CP0_PRid = 0x00010000, |
615 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
616 | (MMU_TYPE_R4000 << CP0C0_MT), |
617 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
618 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
619 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
620 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
621 | .CP0_Config2 = MIPS_CONFIG2, |
622 | .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), |
623 | .CP0_LLAddr_rw_bitmask = 0, |
624 | .CP0_LLAddr_shift = 0, |
625 | .SYNCI_Step = 32, |
626 | .CCRes = 2, |
627 | .CP0_Status_rw_bitmask = 0x36FBFFFF, |
628 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
629 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
630 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
631 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
632 | .CP1_fcr31 = 0, |
633 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
634 | .SEGBITS = 42, |
635 | .PABITS = 36, |
636 | .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D, |
637 | .mmu_type = MMU_TYPE_R4000, |
638 | }, |
639 | { |
640 | .name = "5KEc" , |
641 | .CP0_PRid = 0x00018900, |
642 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
643 | (MMU_TYPE_R4000 << CP0C0_MT), |
644 | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | |
645 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
646 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
647 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
648 | .CP0_Config2 = MIPS_CONFIG2, |
649 | .CP0_Config3 = MIPS_CONFIG3, |
650 | .CP0_LLAddr_rw_bitmask = 0, |
651 | .CP0_LLAddr_shift = 4, |
652 | .SYNCI_Step = 32, |
653 | .CCRes = 2, |
654 | .CP0_Status_rw_bitmask = 0x12F8FFFF, |
655 | .SEGBITS = 42, |
656 | .PABITS = 36, |
657 | .insn_flags = CPU_MIPS64R2, |
658 | .mmu_type = MMU_TYPE_R4000, |
659 | }, |
660 | { |
661 | .name = "5KEf" , |
662 | .CP0_PRid = 0x00018900, |
663 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
664 | (MMU_TYPE_R4000 << CP0C0_MT), |
665 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | |
666 | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | |
667 | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | |
668 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
669 | .CP0_Config2 = MIPS_CONFIG2, |
670 | .CP0_Config3 = MIPS_CONFIG3, |
671 | .CP0_LLAddr_rw_bitmask = 0, |
672 | .CP0_LLAddr_shift = 4, |
673 | .SYNCI_Step = 32, |
674 | .CCRes = 2, |
675 | .CP0_Status_rw_bitmask = 0x36F8FFFF, |
676 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | |
677 | (1 << FCR0_D) | (1 << FCR0_S) | |
678 | (0x89 << FCR0_PRID) | (0x0 << FCR0_REV), |
679 | .SEGBITS = 42, |
680 | .PABITS = 36, |
681 | .insn_flags = CPU_MIPS64R2, |
682 | .mmu_type = MMU_TYPE_R4000, |
683 | }, |
684 | { |
685 | .name = "I6400" , |
686 | .CP0_PRid = 0x1A900, |
687 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
688 | (MMU_TYPE_R4000 << CP0C0_MT), |
689 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
690 | (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | |
691 | (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | |
692 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
693 | .CP0_Config2 = MIPS_CONFIG2, |
694 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | |
695 | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | |
696 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
697 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), |
698 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | |
699 | (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), |
700 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | |
701 | (1 << CP0C5_LLB) | (1 << CP0C5_MRP), |
702 | .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | |
703 | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), |
704 | .CP0_LLAddr_rw_bitmask = 0, |
705 | .CP0_LLAddr_shift = 0, |
706 | .SYNCI_Step = 32, |
707 | .CCRes = 2, |
708 | .CP0_Status_rw_bitmask = 0x30D8FFFF, |
709 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
710 | (1U << CP0PG_RIE), |
711 | .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), |
712 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
713 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
714 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
715 | (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), |
716 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
717 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
718 | .MSAIR = 0x03 << MSAIR_ProcID, |
719 | .SEGBITS = 48, |
720 | .PABITS = 48, |
721 | .insn_flags = CPU_MIPS64R6 | ASE_MSA, |
722 | .mmu_type = MMU_TYPE_R4000, |
723 | }, |
724 | { |
725 | .name = "I6500" , |
726 | .CP0_PRid = 0x1B000, |
727 | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
728 | (MMU_TYPE_R4000 << CP0C0_MT), |
729 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | |
730 | (2 << CP0C1_IS) | (5 << CP0C1_IL) | (3 << CP0C1_IA) | |
731 | (2 << CP0C1_DS) | (5 << CP0C1_DL) | (3 << CP0C1_DA) | |
732 | (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
733 | .CP0_Config2 = MIPS_CONFIG2, |
734 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | |
735 | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | |
736 | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | |
737 | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), |
738 | .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) | |
739 | (1 << CP0C4_AE) | (0xfc << CP0C4_KScrExist), |
740 | .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_VP) | |
741 | (1 << CP0C5_LLB) | (1 << CP0C5_MRP), |
742 | .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) | |
743 | (1 << CP0C5_FRE) | (1 << CP0C5_UFE), |
744 | .CP0_LLAddr_rw_bitmask = 0, |
745 | .CP0_LLAddr_shift = 0, |
746 | .SYNCI_Step = 64, |
747 | .CCRes = 2, |
748 | .CP0_Status_rw_bitmask = 0x30D8FFFF, |
749 | .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) | |
750 | (1U << CP0PG_RIE), |
751 | .CP0_PageGrain_rw_bitmask = (1 << CP0PG_ELPA), |
752 | .CP0_EBaseWG_rw_bitmask = (1 << CP0EBase_WG), |
753 | .CP1_fcr0 = (1 << FCR0_FREP) | (1 << FCR0_HAS2008) | (1 << FCR0_F64) | |
754 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
755 | (1 << FCR0_S) | (0x03 << FCR0_PRID) | (0x0 << FCR0_REV), |
756 | .CP1_fcr31 = (1 << FCR31_ABS2008) | (1 << FCR31_NAN2008), |
757 | .CP1_fcr31_rw_bitmask = 0x0103FFFF, |
758 | .MSAIR = 0x03 << MSAIR_ProcID, |
759 | .SEGBITS = 48, |
760 | .PABITS = 48, |
761 | .insn_flags = CPU_MIPS64R6 | ASE_MSA, |
762 | .mmu_type = MMU_TYPE_R4000, |
763 | }, |
764 | { |
765 | .name = "Loongson-2E" , |
766 | .CP0_PRid = 0x6302, |
767 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
768 | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | |
769 | (0x1<<5) | (0x1<<4) | (0x1<<1), |
770 | /* Note: Config1 is only used internally, |
771 | Loongson-2E has only Config0. */ |
772 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
773 | .SYNCI_Step = 16, |
774 | .CCRes = 2, |
775 | .CP0_Status_rw_bitmask = 0x35D0FFFF, |
776 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
777 | .CP1_fcr31 = 0, |
778 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
779 | .SEGBITS = 40, |
780 | .PABITS = 40, |
781 | .insn_flags = CPU_LOONGSON2E, |
782 | .mmu_type = MMU_TYPE_R4000, |
783 | }, |
784 | { |
785 | .name = "Loongson-2F" , |
786 | .CP0_PRid = 0x6303, |
787 | /* 64KB I-cache and d-cache. 4 way with 32 bit cache line size. */ |
788 | .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | |
789 | (0x1<<5) | (0x1<<4) | (0x1<<1), |
790 | /* Note: Config1 is only used internally, |
791 | Loongson-2F has only Config0. */ |
792 | .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU), |
793 | .SYNCI_Step = 16, |
794 | .CCRes = 2, |
795 | .CP0_Status_rw_bitmask = 0xF5D0FF1F, /* Bits 7:5 not writable. */ |
796 | .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV), |
797 | .CP1_fcr31 = 0, |
798 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
799 | .SEGBITS = 40, |
800 | .PABITS = 40, |
801 | .insn_flags = CPU_LOONGSON2F, |
802 | .mmu_type = MMU_TYPE_R4000, |
803 | }, |
804 | { |
805 | /* A generic CPU providing MIPS64 DSP R2 ASE features. |
806 | FIXME: Eventually this should be replaced by a real CPU model. */ |
807 | .name = "mips64dspr2" , |
808 | .CP0_PRid = 0x00010000, |
809 | .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | |
810 | (MMU_TYPE_R4000 << CP0C0_MT), |
811 | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | |
812 | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | |
813 | (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | |
814 | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), |
815 | .CP0_Config2 = MIPS_CONFIG2, |
816 | .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | |
817 | (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), |
818 | .CP0_LLAddr_rw_bitmask = 0, |
819 | .CP0_LLAddr_shift = 0, |
820 | .SYNCI_Step = 32, |
821 | .CCRes = 2, |
822 | .CP0_Status_rw_bitmask = 0x37FBFFFF, |
823 | .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | |
824 | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | |
825 | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), |
826 | .CP1_fcr31 = 0, |
827 | .CP1_fcr31_rw_bitmask = 0xFF83FFFF, |
828 | .SEGBITS = 42, |
829 | .PABITS = 36, |
830 | .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2, |
831 | .mmu_type = MMU_TYPE_R4000, |
832 | }, |
833 | |
834 | #endif |
835 | }; |
836 | const int mips_defs_number = ARRAY_SIZE(mips_defs); |
837 | |
838 | void mips_cpu_list(void) |
839 | { |
840 | int i; |
841 | |
842 | for (i = 0; i < ARRAY_SIZE(mips_defs); i++) { |
843 | qemu_printf("MIPS '%s'\n" , mips_defs[i].name); |
844 | } |
845 | } |
846 | |
847 | #ifndef CONFIG_USER_ONLY |
848 | static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
849 | { |
850 | env->tlb->nb_tlb = 1; |
851 | env->tlb->map_address = &no_mmu_map_address; |
852 | } |
853 | |
854 | static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
855 | { |
856 | env->tlb->nb_tlb = 1; |
857 | env->tlb->map_address = &fixed_mmu_map_address; |
858 | } |
859 | |
860 | static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def) |
861 | { |
862 | env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63); |
863 | env->tlb->map_address = &r4k_map_address; |
864 | env->tlb->helper_tlbwi = r4k_helper_tlbwi; |
865 | env->tlb->helper_tlbwr = r4k_helper_tlbwr; |
866 | env->tlb->helper_tlbp = r4k_helper_tlbp; |
867 | env->tlb->helper_tlbr = r4k_helper_tlbr; |
868 | env->tlb->helper_tlbinv = r4k_helper_tlbinv; |
869 | env->tlb->helper_tlbinvf = r4k_helper_tlbinvf; |
870 | } |
871 | |
872 | static void mmu_init (CPUMIPSState *env, const mips_def_t *def) |
873 | { |
874 | env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext)); |
875 | |
876 | switch (def->mmu_type) { |
877 | case MMU_TYPE_NONE: |
878 | no_mmu_init(env, def); |
879 | break; |
880 | case MMU_TYPE_R4000: |
881 | r4k_mmu_init(env, def); |
882 | break; |
883 | case MMU_TYPE_FMT: |
884 | fixed_mmu_init(env, def); |
885 | break; |
886 | case MMU_TYPE_R3000: |
887 | case MMU_TYPE_R6000: |
888 | case MMU_TYPE_R8000: |
889 | default: |
890 | cpu_abort(env_cpu(env), "MMU type not supported\n" ); |
891 | } |
892 | } |
893 | #endif /* CONFIG_USER_ONLY */ |
894 | |
895 | static void fpu_init (CPUMIPSState *env, const mips_def_t *def) |
896 | { |
897 | int i; |
898 | |
899 | for (i = 0; i < MIPS_FPU_MAX; i++) |
900 | env->fpus[i].fcr0 = def->CP1_fcr0; |
901 | |
902 | memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu)); |
903 | } |
904 | |
905 | static void mvp_init (CPUMIPSState *env, const mips_def_t *def) |
906 | { |
907 | env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext)); |
908 | |
909 | /* MVPConf1 implemented, TLB sharable, no gating storage support, |
910 | programmable cache partitioning implemented, number of allocatable |
911 | and sharable TLB entries, MVP has allocatable TCs, 2 VPEs |
912 | implemented, 5 TCs implemented. */ |
913 | env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | |
914 | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | |
915 | // TODO: actually do 2 VPEs. |
916 | // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | |
917 | // (0x04 << CP0MVPC0_PTC); |
918 | (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) | |
919 | (0x00 << CP0MVPC0_PTC); |
920 | #if !defined(CONFIG_USER_ONLY) |
921 | /* Usermode has no TLB support */ |
922 | env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE); |
923 | #endif |
924 | |
925 | /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, |
926 | no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ |
927 | env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | |
928 | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | |
929 | (0x1 << CP0MVPC1_PCP1); |
930 | } |
931 | |
932 | static void msa_reset(CPUMIPSState *env) |
933 | { |
934 | #ifdef CONFIG_USER_ONLY |
935 | /* MSA access enabled */ |
936 | env->CP0_Config5 |= 1 << CP0C5_MSAEn; |
937 | env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); |
938 | #endif |
939 | |
940 | /* MSA CSR: |
941 | - non-signaling floating point exception mode off (NX bit is 0) |
942 | - Cause, Enables, and Flags are all 0 |
943 | - round to nearest / ties to even (RM bits are 0) */ |
944 | env->active_tc.msacsr = 0; |
945 | |
946 | restore_msa_fp_status(env); |
947 | |
948 | /* tininess detected after rounding.*/ |
949 | set_float_detect_tininess(float_tininess_after_rounding, |
950 | &env->active_tc.msa_fp_status); |
951 | |
952 | /* clear float_status exception flags */ |
953 | set_float_exception_flags(0, &env->active_tc.msa_fp_status); |
954 | |
955 | /* clear float_status nan mode */ |
956 | set_default_nan_mode(0, &env->active_tc.msa_fp_status); |
957 | |
958 | /* set proper signanling bit meaning ("1" means "quiet") */ |
959 | set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); |
960 | } |
961 | |