1 | /* |
2 | * PowerPC emulation special registers manipulation helpers for qemu. |
3 | * |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #ifndef HELPER_REGS_H |
21 | #define HELPER_REGS_H |
22 | |
23 | #include "qemu/main-loop.h" |
24 | #include "exec/exec-all.h" |
25 | |
26 | /* Swap temporary saved registers with GPRs */ |
27 | static inline void hreg_swap_gpr_tgpr(CPUPPCState *env) |
28 | { |
29 | target_ulong tmp; |
30 | |
31 | tmp = env->gpr[0]; |
32 | env->gpr[0] = env->tgpr[0]; |
33 | env->tgpr[0] = tmp; |
34 | tmp = env->gpr[1]; |
35 | env->gpr[1] = env->tgpr[1]; |
36 | env->tgpr[1] = tmp; |
37 | tmp = env->gpr[2]; |
38 | env->gpr[2] = env->tgpr[2]; |
39 | env->tgpr[2] = tmp; |
40 | tmp = env->gpr[3]; |
41 | env->gpr[3] = env->tgpr[3]; |
42 | env->tgpr[3] = tmp; |
43 | } |
44 | |
45 | static inline void hreg_compute_mem_idx(CPUPPCState *env) |
46 | { |
47 | /* |
48 | * This is our encoding for server processors. The architecture |
49 | * specifies that there is no such thing as userspace with |
50 | * translation off, however it appears that MacOS does it and some |
51 | * 32-bit CPUs support it. Weird... |
52 | * |
53 | * 0 = Guest User space virtual mode |
54 | * 1 = Guest Kernel space virtual mode |
55 | * 2 = Guest User space real mode |
56 | * 3 = Guest Kernel space real mode |
57 | * 4 = HV User space virtual mode |
58 | * 5 = HV Kernel space virtual mode |
59 | * 6 = HV User space real mode |
60 | * 7 = HV Kernel space real mode |
61 | * |
62 | * For BookE, we need 8 MMU modes as follow: |
63 | * |
64 | * 0 = AS 0 HV User space |
65 | * 1 = AS 0 HV Kernel space |
66 | * 2 = AS 1 HV User space |
67 | * 3 = AS 1 HV Kernel space |
68 | * 4 = AS 0 Guest User space |
69 | * 5 = AS 0 Guest Kernel space |
70 | * 6 = AS 1 Guest User space |
71 | * 7 = AS 1 Guest Kernel space |
72 | */ |
73 | if (env->mmu_model & POWERPC_MMU_BOOKE) { |
74 | env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; |
75 | env->immu_idx += msr_is ? 2 : 0; |
76 | env->dmmu_idx += msr_ds ? 2 : 0; |
77 | env->immu_idx += msr_gs ? 4 : 0; |
78 | env->dmmu_idx += msr_gs ? 4 : 0; |
79 | } else { |
80 | env->immu_idx = env->dmmu_idx = msr_pr ? 0 : 1; |
81 | env->immu_idx += msr_ir ? 0 : 2; |
82 | env->dmmu_idx += msr_dr ? 0 : 2; |
83 | env->immu_idx += msr_hv ? 4 : 0; |
84 | env->dmmu_idx += msr_hv ? 4 : 0; |
85 | } |
86 | } |
87 | |
88 | static inline void hreg_compute_hflags(CPUPPCState *env) |
89 | { |
90 | target_ulong hflags_mask; |
91 | |
92 | /* We 'forget' FE0 & FE1: we'll never generate imprecise exceptions */ |
93 | hflags_mask = (1 << MSR_VR) | (1 << MSR_AP) | (1 << MSR_SA) | |
94 | (1 << MSR_PR) | (1 << MSR_FP) | (1 << MSR_SE) | (1 << MSR_BE) | |
95 | (1 << MSR_LE) | (1 << MSR_VSX) | (1 << MSR_IR) | (1 << MSR_DR); |
96 | hflags_mask |= (1ULL << MSR_CM) | (1ULL << MSR_SF) | MSR_HVB; |
97 | hreg_compute_mem_idx(env); |
98 | env->hflags = env->msr & hflags_mask; |
99 | /* Merge with hflags coming from other registers */ |
100 | env->hflags |= env->hflags_nmsr; |
101 | } |
102 | |
103 | static inline void cpu_interrupt_exittb(CPUState *cs) |
104 | { |
105 | if (!qemu_mutex_iothread_locked()) { |
106 | qemu_mutex_lock_iothread(); |
107 | cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); |
108 | qemu_mutex_unlock_iothread(); |
109 | } else { |
110 | cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); |
111 | } |
112 | } |
113 | |
114 | static inline int hreg_store_msr(CPUPPCState *env, target_ulong value, |
115 | int alter_hv) |
116 | { |
117 | int excp; |
118 | #if !defined(CONFIG_USER_ONLY) |
119 | CPUState *cs = env_cpu(env); |
120 | #endif |
121 | |
122 | excp = 0; |
123 | value &= env->msr_mask; |
124 | #if !defined(CONFIG_USER_ONLY) |
125 | /* Neither mtmsr nor guest state can alter HV */ |
126 | if (!alter_hv || !(env->msr & MSR_HVB)) { |
127 | value &= ~MSR_HVB; |
128 | value |= env->msr & MSR_HVB; |
129 | } |
130 | if (((value >> MSR_IR) & 1) != msr_ir || |
131 | ((value >> MSR_DR) & 1) != msr_dr) { |
132 | cpu_interrupt_exittb(cs); |
133 | } |
134 | if ((env->mmu_model & POWERPC_MMU_BOOKE) && |
135 | ((value >> MSR_GS) & 1) != msr_gs) { |
136 | cpu_interrupt_exittb(cs); |
137 | } |
138 | if (unlikely((env->flags & POWERPC_FLAG_TGPR) && |
139 | ((value ^ env->msr) & (1 << MSR_TGPR)))) { |
140 | /* Swap temporary saved registers with GPRs */ |
141 | hreg_swap_gpr_tgpr(env); |
142 | } |
143 | if (unlikely((value >> MSR_EP) & 1) != msr_ep) { |
144 | /* Change the exception prefix on PowerPC 601 */ |
145 | env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000; |
146 | } |
147 | /* |
148 | * If PR=1 then EE, IR and DR must be 1 |
149 | * |
150 | * Note: We only enforce this on 64-bit server processors. |
151 | * It appears that: |
152 | * - 32-bit implementations supports PR=1 and EE/DR/IR=0 and MacOS |
153 | * exploits it. |
154 | * - 64-bit embedded implementations do not need any operation to be |
155 | * performed when PR is set. |
156 | */ |
157 | if (is_book3s_arch2x(env) && ((value >> MSR_PR) & 1)) { |
158 | value |= (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); |
159 | } |
160 | #endif |
161 | env->msr = value; |
162 | hreg_compute_hflags(env); |
163 | #if !defined(CONFIG_USER_ONLY) |
164 | if (unlikely(msr_pow == 1)) { |
165 | if (!env->pending_interrupts && (*env->check_pow)(env)) { |
166 | cs->halted = 1; |
167 | excp = EXCP_HALTED; |
168 | } |
169 | } |
170 | #endif |
171 | |
172 | return excp; |
173 | } |
174 | |
175 | #if !defined(CONFIG_USER_ONLY) |
176 | static inline void check_tlb_flush(CPUPPCState *env, bool global) |
177 | { |
178 | CPUState *cs = env_cpu(env); |
179 | |
180 | /* Handle global flushes first */ |
181 | if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { |
182 | env->tlb_need_flush &= ~TLB_NEED_GLOBAL_FLUSH; |
183 | env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; |
184 | tlb_flush_all_cpus_synced(cs); |
185 | return; |
186 | } |
187 | |
188 | /* Then handle local ones */ |
189 | if (env->tlb_need_flush & TLB_NEED_LOCAL_FLUSH) { |
190 | env->tlb_need_flush &= ~TLB_NEED_LOCAL_FLUSH; |
191 | tlb_flush(cs); |
192 | } |
193 | } |
194 | #else |
195 | static inline void check_tlb_flush(CPUPPCState *env, bool global) { } |
196 | #endif |
197 | |
198 | #endif /* HELPER_REGS_H */ |
199 | |