1 | /* |
2 | * PowerPC ISAV3 BookS emulation generic mmu helpers for qemu. |
3 | * |
4 | * Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #include "qemu/osdep.h" |
21 | #include "cpu.h" |
22 | #include "mmu-hash64.h" |
23 | #include "mmu-book3s-v3.h" |
24 | #include "mmu-radix64.h" |
25 | |
26 | int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, |
27 | int mmu_idx) |
28 | { |
29 | if (ppc64_v3_radix(cpu)) { /* Guest uses radix */ |
30 | return ppc_radix64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); |
31 | } else { /* Guest uses hash */ |
32 | return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx); |
33 | } |
34 | } |
35 | |
36 | hwaddr ppc64_v3_get_phys_page_debug(PowerPCCPU *cpu, vaddr eaddr) |
37 | { |
38 | if (ppc64_v3_radix(cpu)) { |
39 | return ppc_radix64_get_phys_page_debug(cpu, eaddr); |
40 | } else { |
41 | return ppc_hash64_get_phys_page_debug(cpu, eaddr); |
42 | } |
43 | } |
44 | |
45 | bool ppc64_v3_get_pate(PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) |
46 | { |
47 | uint64_t patb = cpu->env.spr[SPR_PTCR] & PTCR_PATB; |
48 | uint64_t pats = cpu->env.spr[SPR_PTCR] & PTCR_PATS; |
49 | |
50 | /* Calculate number of entries */ |
51 | pats = 1ull << (pats + 12 - 4); |
52 | if (pats <= lpid) { |
53 | return false; |
54 | } |
55 | |
56 | /* Grab entry */ |
57 | patb += 16 * lpid; |
58 | entry->dw0 = ldq_phys(CPU(cpu)->as, patb); |
59 | entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8); |
60 | return true; |
61 | } |
62 | |