1 | #ifndef MMU_HASH32_H |
2 | #define MMU_HASH32_H |
3 | |
4 | #ifndef CONFIG_USER_ONLY |
5 | |
6 | hwaddr get_pteg_offset32(PowerPCCPU *cpu, hwaddr hash); |
7 | hwaddr ppc_hash32_get_phys_page_debug(PowerPCCPU *cpu, target_ulong addr); |
8 | int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, vaddr address, int rw, |
9 | int mmu_idx); |
10 | |
11 | /* |
12 | * Segment register definitions |
13 | */ |
14 | |
15 | #define SR32_T 0x80000000 |
16 | #define SR32_KS 0x40000000 |
17 | #define SR32_KP 0x20000000 |
18 | #define SR32_NX 0x10000000 |
19 | #define SR32_VSID 0x00ffffff |
20 | |
21 | /* |
22 | * Block Address Translation (BAT) definitions |
23 | */ |
24 | |
25 | #define BATU32_BEPI 0xfffe0000 |
26 | #define BATU32_BL 0x00001ffc |
27 | #define BATU32_VS 0x00000002 |
28 | #define BATU32_VP 0x00000001 |
29 | |
30 | |
31 | #define BATL32_BRPN 0xfffe0000 |
32 | #define BATL32_WIMG 0x00000078 |
33 | #define BATL32_PP 0x00000003 |
34 | |
35 | /* PowerPC 601 has slightly different BAT registers */ |
36 | |
37 | #define BATU32_601_KS 0x00000008 |
38 | #define BATU32_601_KP 0x00000004 |
39 | #define BATU32_601_PP 0x00000003 |
40 | |
41 | #define BATL32_601_V 0x00000040 |
42 | #define BATL32_601_BL 0x0000003f |
43 | |
44 | /* |
45 | * Hash page table definitions |
46 | */ |
47 | #define SDR_32_HTABORG 0xFFFF0000UL |
48 | #define SDR_32_HTABMASK 0x000001FFUL |
49 | |
50 | #define HPTES_PER_GROUP 8 |
51 | #define HASH_PTE_SIZE_32 8 |
52 | #define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP) |
53 | |
54 | #define HPTE32_V_VALID 0x80000000 |
55 | #define HPTE32_V_VSID 0x7fffff80 |
56 | #define HPTE32_V_SECONDARY 0x00000040 |
57 | #define HPTE32_V_API 0x0000003f |
58 | #define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf)) |
59 | |
60 | #define HPTE32_R_RPN 0xfffff000 |
61 | #define HPTE32_R_R 0x00000100 |
62 | #define HPTE32_R_C 0x00000080 |
63 | #define HPTE32_R_W 0x00000040 |
64 | #define HPTE32_R_I 0x00000020 |
65 | #define HPTE32_R_M 0x00000010 |
66 | #define HPTE32_R_G 0x00000008 |
67 | #define HPTE32_R_WIMG 0x00000078 |
68 | #define HPTE32_R_PP 0x00000003 |
69 | |
70 | static inline hwaddr ppc_hash32_hpt_base(PowerPCCPU *cpu) |
71 | { |
72 | return cpu->env.spr[SPR_SDR1] & SDR_32_HTABORG; |
73 | } |
74 | |
75 | static inline hwaddr ppc_hash32_hpt_mask(PowerPCCPU *cpu) |
76 | { |
77 | return ((cpu->env.spr[SPR_SDR1] & SDR_32_HTABMASK) << 16) | 0xFFFF; |
78 | } |
79 | |
80 | static inline target_ulong ppc_hash32_load_hpte0(PowerPCCPU *cpu, |
81 | hwaddr pte_offset) |
82 | { |
83 | target_ulong base = ppc_hash32_hpt_base(cpu); |
84 | |
85 | return ldl_phys(CPU(cpu)->as, base + pte_offset); |
86 | } |
87 | |
88 | static inline target_ulong ppc_hash32_load_hpte1(PowerPCCPU *cpu, |
89 | hwaddr pte_offset) |
90 | { |
91 | target_ulong base = ppc_hash32_hpt_base(cpu); |
92 | |
93 | return ldl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2); |
94 | } |
95 | |
96 | static inline void ppc_hash32_store_hpte0(PowerPCCPU *cpu, |
97 | hwaddr pte_offset, target_ulong pte0) |
98 | { |
99 | target_ulong base = ppc_hash32_hpt_base(cpu); |
100 | |
101 | stl_phys(CPU(cpu)->as, base + pte_offset, pte0); |
102 | } |
103 | |
104 | static inline void ppc_hash32_store_hpte1(PowerPCCPU *cpu, |
105 | hwaddr pte_offset, target_ulong pte1) |
106 | { |
107 | target_ulong base = ppc_hash32_hpt_base(cpu); |
108 | |
109 | stl_phys(CPU(cpu)->as, base + pte_offset + HASH_PTE_SIZE_32 / 2, pte1); |
110 | } |
111 | |
112 | typedef struct { |
113 | uint32_t pte0, pte1; |
114 | } ppc_hash_pte32_t; |
115 | |
116 | #endif /* CONFIG_USER_ONLY */ |
117 | |
118 | #endif /* MMU_HASH32_H */ |
119 | |