1 | /* |
2 | * PowerPC emulation for qemu: main translation routines. |
3 | * |
4 | * Copyright (c) 2003-2007 Jocelyn Mayer |
5 | * Copyright (C) 2011 Freescale Semiconductor, Inc. |
6 | * |
7 | * This library is free software; you can redistribute it and/or |
8 | * modify it under the terms of the GNU Lesser General Public |
9 | * License as published by the Free Software Foundation; either |
10 | * version 2 of the License, or (at your option) any later version. |
11 | * |
12 | * This library is distributed in the hope that it will be useful, |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
15 | * Lesser General Public License for more details. |
16 | * |
17 | * You should have received a copy of the GNU Lesser General Public |
18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
19 | */ |
20 | |
21 | #include "qemu/osdep.h" |
22 | #include "cpu.h" |
23 | #include "internal.h" |
24 | #include "disas/disas.h" |
25 | #include "exec/exec-all.h" |
26 | #include "tcg-op.h" |
27 | #include "tcg-op-gvec.h" |
28 | #include "qemu/host-utils.h" |
29 | #include "qemu/main-loop.h" |
30 | #include "exec/cpu_ldst.h" |
31 | |
32 | #include "exec/helper-proto.h" |
33 | #include "exec/helper-gen.h" |
34 | |
35 | #include "trace-tcg.h" |
36 | #include "exec/translator.h" |
37 | #include "exec/log.h" |
38 | #include "qemu/atomic128.h" |
39 | |
40 | |
41 | #define CPU_SINGLE_STEP 0x1 |
42 | #define CPU_BRANCH_STEP 0x2 |
43 | #define GDBSTUB_SINGLE_STEP 0x4 |
44 | |
45 | /* Include definitions for instructions classes and implementations flags */ |
46 | /* #define PPC_DEBUG_DISAS */ |
47 | /* #define DO_PPC_STATISTICS */ |
48 | |
49 | #ifdef PPC_DEBUG_DISAS |
50 | # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__) |
51 | #else |
52 | # define LOG_DISAS(...) do { } while (0) |
53 | #endif |
54 | /*****************************************************************************/ |
55 | /* Code translation helpers */ |
56 | |
57 | /* global register indexes */ |
58 | static char cpu_reg_names[10 * 3 + 22 * 4 /* GPR */ |
59 | + 10 * 4 + 22 * 5 /* SPE GPRh */ |
60 | + 8 * 5 /* CRF */]; |
61 | static TCGv cpu_gpr[32]; |
62 | static TCGv cpu_gprh[32]; |
63 | static TCGv_i32 cpu_crf[8]; |
64 | static TCGv cpu_nip; |
65 | static TCGv cpu_msr; |
66 | static TCGv cpu_ctr; |
67 | static TCGv cpu_lr; |
68 | #if defined(TARGET_PPC64) |
69 | static TCGv cpu_cfar; |
70 | #endif |
71 | static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; |
72 | static TCGv cpu_reserve; |
73 | static TCGv cpu_reserve_val; |
74 | static TCGv cpu_fpscr; |
75 | static TCGv_i32 cpu_access_type; |
76 | |
77 | #include "exec/gen-icount.h" |
78 | |
79 | void ppc_translate_init(void) |
80 | { |
81 | int i; |
82 | char *p; |
83 | size_t cpu_reg_names_size; |
84 | |
85 | p = cpu_reg_names; |
86 | cpu_reg_names_size = sizeof(cpu_reg_names); |
87 | |
88 | for (i = 0; i < 8; i++) { |
89 | snprintf(p, cpu_reg_names_size, "crf%d" , i); |
90 | cpu_crf[i] = tcg_global_mem_new_i32(cpu_env, |
91 | offsetof(CPUPPCState, crf[i]), p); |
92 | p += 5; |
93 | cpu_reg_names_size -= 5; |
94 | } |
95 | |
96 | for (i = 0; i < 32; i++) { |
97 | snprintf(p, cpu_reg_names_size, "r%d" , i); |
98 | cpu_gpr[i] = tcg_global_mem_new(cpu_env, |
99 | offsetof(CPUPPCState, gpr[i]), p); |
100 | p += (i < 10) ? 3 : 4; |
101 | cpu_reg_names_size -= (i < 10) ? 3 : 4; |
102 | snprintf(p, cpu_reg_names_size, "r%dH" , i); |
103 | cpu_gprh[i] = tcg_global_mem_new(cpu_env, |
104 | offsetof(CPUPPCState, gprh[i]), p); |
105 | p += (i < 10) ? 4 : 5; |
106 | cpu_reg_names_size -= (i < 10) ? 4 : 5; |
107 | } |
108 | |
109 | cpu_nip = tcg_global_mem_new(cpu_env, |
110 | offsetof(CPUPPCState, nip), "nip" ); |
111 | |
112 | cpu_msr = tcg_global_mem_new(cpu_env, |
113 | offsetof(CPUPPCState, msr), "msr" ); |
114 | |
115 | cpu_ctr = tcg_global_mem_new(cpu_env, |
116 | offsetof(CPUPPCState, ctr), "ctr" ); |
117 | |
118 | cpu_lr = tcg_global_mem_new(cpu_env, |
119 | offsetof(CPUPPCState, lr), "lr" ); |
120 | |
121 | #if defined(TARGET_PPC64) |
122 | cpu_cfar = tcg_global_mem_new(cpu_env, |
123 | offsetof(CPUPPCState, cfar), "cfar" ); |
124 | #endif |
125 | |
126 | cpu_xer = tcg_global_mem_new(cpu_env, |
127 | offsetof(CPUPPCState, xer), "xer" ); |
128 | cpu_so = tcg_global_mem_new(cpu_env, |
129 | offsetof(CPUPPCState, so), "SO" ); |
130 | cpu_ov = tcg_global_mem_new(cpu_env, |
131 | offsetof(CPUPPCState, ov), "OV" ); |
132 | cpu_ca = tcg_global_mem_new(cpu_env, |
133 | offsetof(CPUPPCState, ca), "CA" ); |
134 | cpu_ov32 = tcg_global_mem_new(cpu_env, |
135 | offsetof(CPUPPCState, ov32), "OV32" ); |
136 | cpu_ca32 = tcg_global_mem_new(cpu_env, |
137 | offsetof(CPUPPCState, ca32), "CA32" ); |
138 | |
139 | cpu_reserve = tcg_global_mem_new(cpu_env, |
140 | offsetof(CPUPPCState, reserve_addr), |
141 | "reserve_addr" ); |
142 | cpu_reserve_val = tcg_global_mem_new(cpu_env, |
143 | offsetof(CPUPPCState, reserve_val), |
144 | "reserve_val" ); |
145 | |
146 | cpu_fpscr = tcg_global_mem_new(cpu_env, |
147 | offsetof(CPUPPCState, fpscr), "fpscr" ); |
148 | |
149 | cpu_access_type = tcg_global_mem_new_i32(cpu_env, |
150 | offsetof(CPUPPCState, access_type), |
151 | "access_type" ); |
152 | } |
153 | |
154 | /* internal defines */ |
155 | struct DisasContext { |
156 | DisasContextBase base; |
157 | uint32_t opcode; |
158 | uint32_t exception; |
159 | /* Routine used to access memory */ |
160 | bool pr, hv, dr, le_mode; |
161 | bool lazy_tlb_flush; |
162 | bool need_access_type; |
163 | int mem_idx; |
164 | int access_type; |
165 | /* Translation flags */ |
166 | MemOp default_tcg_memop_mask; |
167 | #if defined(TARGET_PPC64) |
168 | bool sf_mode; |
169 | bool has_cfar; |
170 | #endif |
171 | bool fpu_enabled; |
172 | bool altivec_enabled; |
173 | bool vsx_enabled; |
174 | bool spe_enabled; |
175 | bool tm_enabled; |
176 | bool gtse; |
177 | ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */ |
178 | int singlestep_enabled; |
179 | uint32_t flags; |
180 | uint64_t insns_flags; |
181 | uint64_t insns_flags2; |
182 | }; |
183 | |
184 | /* Return true iff byteswap is needed in a scalar memop */ |
185 | static inline bool need_byteswap(const DisasContext *ctx) |
186 | { |
187 | #if defined(TARGET_WORDS_BIGENDIAN) |
188 | return ctx->le_mode; |
189 | #else |
190 | return !ctx->le_mode; |
191 | #endif |
192 | } |
193 | |
194 | /* True when active word size < size of target_long. */ |
195 | #ifdef TARGET_PPC64 |
196 | # define NARROW_MODE(C) (!(C)->sf_mode) |
197 | #else |
198 | # define NARROW_MODE(C) 0 |
199 | #endif |
200 | |
201 | struct opc_handler_t { |
202 | /* invalid bits for instruction 1 (Rc(opcode) == 0) */ |
203 | uint32_t inval1; |
204 | /* invalid bits for instruction 2 (Rc(opcode) == 1) */ |
205 | uint32_t inval2; |
206 | /* instruction type */ |
207 | uint64_t type; |
208 | /* extended instruction type */ |
209 | uint64_t type2; |
210 | /* handler */ |
211 | void (*handler)(DisasContext *ctx); |
212 | #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU) |
213 | const char *oname; |
214 | #endif |
215 | #if defined(DO_PPC_STATISTICS) |
216 | uint64_t count; |
217 | #endif |
218 | }; |
219 | |
220 | /* SPR load/store helpers */ |
221 | static inline void gen_load_spr(TCGv t, int reg) |
222 | { |
223 | tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
224 | } |
225 | |
226 | static inline void gen_store_spr(int reg, TCGv t) |
227 | { |
228 | tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg])); |
229 | } |
230 | |
231 | static inline void gen_set_access_type(DisasContext *ctx, int access_type) |
232 | { |
233 | if (ctx->need_access_type && ctx->access_type != access_type) { |
234 | tcg_gen_movi_i32(cpu_access_type, access_type); |
235 | ctx->access_type = access_type; |
236 | } |
237 | } |
238 | |
239 | static inline void gen_update_nip(DisasContext *ctx, target_ulong nip) |
240 | { |
241 | if (NARROW_MODE(ctx)) { |
242 | nip = (uint32_t)nip; |
243 | } |
244 | tcg_gen_movi_tl(cpu_nip, nip); |
245 | } |
246 | |
247 | static void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error) |
248 | { |
249 | TCGv_i32 t0, t1; |
250 | |
251 | /* |
252 | * These are all synchronous exceptions, we set the PC back to the |
253 | * faulting instruction |
254 | */ |
255 | if (ctx->exception == POWERPC_EXCP_NONE) { |
256 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
257 | } |
258 | t0 = tcg_const_i32(excp); |
259 | t1 = tcg_const_i32(error); |
260 | gen_helper_raise_exception_err(cpu_env, t0, t1); |
261 | tcg_temp_free_i32(t0); |
262 | tcg_temp_free_i32(t1); |
263 | ctx->exception = (excp); |
264 | } |
265 | |
266 | static void gen_exception(DisasContext *ctx, uint32_t excp) |
267 | { |
268 | TCGv_i32 t0; |
269 | |
270 | /* |
271 | * These are all synchronous exceptions, we set the PC back to the |
272 | * faulting instruction |
273 | */ |
274 | if (ctx->exception == POWERPC_EXCP_NONE) { |
275 | gen_update_nip(ctx, ctx->base.pc_next - 4); |
276 | } |
277 | t0 = tcg_const_i32(excp); |
278 | gen_helper_raise_exception(cpu_env, t0); |
279 | tcg_temp_free_i32(t0); |
280 | ctx->exception = (excp); |
281 | } |
282 | |
283 | static void gen_exception_nip(DisasContext *ctx, uint32_t excp, |
284 | target_ulong nip) |
285 | { |
286 | TCGv_i32 t0; |
287 | |
288 | gen_update_nip(ctx, nip); |
289 | t0 = tcg_const_i32(excp); |
290 | gen_helper_raise_exception(cpu_env, t0); |
291 | tcg_temp_free_i32(t0); |
292 | ctx->exception = (excp); |
293 | } |
294 | |
295 | /* |
296 | * Tells the caller what is the appropriate exception to generate and prepares |
297 | * SPR registers for this exception. |
298 | * |
299 | * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or |
300 | * POWERPC_EXCP_DEBUG (on BookE). |
301 | */ |
302 | static uint32_t gen_prep_dbgex(DisasContext *ctx) |
303 | { |
304 | if (ctx->flags & POWERPC_FLAG_DE) { |
305 | target_ulong dbsr = 0; |
306 | if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { |
307 | dbsr = DBCR0_ICMP; |
308 | } else { |
309 | /* Must have been branch */ |
310 | dbsr = DBCR0_BRT; |
311 | } |
312 | TCGv t0 = tcg_temp_new(); |
313 | gen_load_spr(t0, SPR_BOOKE_DBSR); |
314 | tcg_gen_ori_tl(t0, t0, dbsr); |
315 | gen_store_spr(SPR_BOOKE_DBSR, t0); |
316 | tcg_temp_free(t0); |
317 | return POWERPC_EXCP_DEBUG; |
318 | } else { |
319 | return POWERPC_EXCP_TRACE; |
320 | } |
321 | } |
322 | |
323 | static void gen_debug_exception(DisasContext *ctx) |
324 | { |
325 | TCGv_i32 t0; |
326 | |
327 | /* |
328 | * These are all synchronous exceptions, we set the PC back to the |
329 | * faulting instruction |
330 | */ |
331 | if ((ctx->exception != POWERPC_EXCP_BRANCH) && |
332 | (ctx->exception != POWERPC_EXCP_SYNC)) { |
333 | gen_update_nip(ctx, ctx->base.pc_next); |
334 | } |
335 | t0 = tcg_const_i32(EXCP_DEBUG); |
336 | gen_helper_raise_exception(cpu_env, t0); |
337 | tcg_temp_free_i32(t0); |
338 | } |
339 | |
340 | static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) |
341 | { |
342 | /* Will be converted to program check if needed */ |
343 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_INVAL | error); |
344 | } |
345 | |
346 | static inline void gen_priv_exception(DisasContext *ctx, uint32_t error) |
347 | { |
348 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_PRIV | error); |
349 | } |
350 | |
351 | static inline void gen_hvpriv_exception(DisasContext *ctx, uint32_t error) |
352 | { |
353 | /* Will be converted to program check if needed */ |
354 | gen_exception_err(ctx, POWERPC_EXCP_HV_EMU, POWERPC_EXCP_PRIV | error); |
355 | } |
356 | |
357 | /* Stop translation */ |
358 | static inline void gen_stop_exception(DisasContext *ctx) |
359 | { |
360 | gen_update_nip(ctx, ctx->base.pc_next); |
361 | ctx->exception = POWERPC_EXCP_STOP; |
362 | } |
363 | |
364 | #ifndef CONFIG_USER_ONLY |
365 | /* No need to update nip here, as execution flow will change */ |
366 | static inline void gen_sync_exception(DisasContext *ctx) |
367 | { |
368 | ctx->exception = POWERPC_EXCP_SYNC; |
369 | } |
370 | #endif |
371 | |
372 | #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ |
373 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE) |
374 | |
375 | #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ |
376 | GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2) |
377 | |
378 | #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ |
379 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE) |
380 | |
381 | #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ |
382 | GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2) |
383 | |
384 | #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ |
385 | GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2) |
386 | |
387 | #define GEN_HANDLER2_E_2(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) \ |
388 | GEN_OPCODE4(name, onam, opc1, opc2, opc3, opc4, inval, typ, typ2) |
389 | |
390 | typedef struct opcode_t { |
391 | unsigned char opc1, opc2, opc3, opc4; |
392 | #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */ |
393 | unsigned char pad[4]; |
394 | #endif |
395 | opc_handler_t handler; |
396 | const char *oname; |
397 | } opcode_t; |
398 | |
399 | /* Helpers for priv. check */ |
400 | #define GEN_PRIV \ |
401 | do { \ |
402 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; \ |
403 | } while (0) |
404 | |
405 | #if defined(CONFIG_USER_ONLY) |
406 | #define CHK_HV GEN_PRIV |
407 | #define CHK_SV GEN_PRIV |
408 | #define CHK_HVRM GEN_PRIV |
409 | #else |
410 | #define CHK_HV \ |
411 | do { \ |
412 | if (unlikely(ctx->pr || !ctx->hv)) { \ |
413 | GEN_PRIV; \ |
414 | } \ |
415 | } while (0) |
416 | #define CHK_SV \ |
417 | do { \ |
418 | if (unlikely(ctx->pr)) { \ |
419 | GEN_PRIV; \ |
420 | } \ |
421 | } while (0) |
422 | #define CHK_HVRM \ |
423 | do { \ |
424 | if (unlikely(ctx->pr || !ctx->hv || ctx->dr)) { \ |
425 | GEN_PRIV; \ |
426 | } \ |
427 | } while (0) |
428 | #endif |
429 | |
430 | #define CHK_NONE |
431 | |
432 | /*****************************************************************************/ |
433 | /* PowerPC instructions table */ |
434 | |
435 | #if defined(DO_PPC_STATISTICS) |
436 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
437 | { \ |
438 | .opc1 = op1, \ |
439 | .opc2 = op2, \ |
440 | .opc3 = op3, \ |
441 | .opc4 = 0xff, \ |
442 | .handler = { \ |
443 | .inval1 = invl, \ |
444 | .type = _typ, \ |
445 | .type2 = _typ2, \ |
446 | .handler = &gen_##name, \ |
447 | .oname = stringify(name), \ |
448 | }, \ |
449 | .oname = stringify(name), \ |
450 | } |
451 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ |
452 | { \ |
453 | .opc1 = op1, \ |
454 | .opc2 = op2, \ |
455 | .opc3 = op3, \ |
456 | .opc4 = 0xff, \ |
457 | .handler = { \ |
458 | .inval1 = invl1, \ |
459 | .inval2 = invl2, \ |
460 | .type = _typ, \ |
461 | .type2 = _typ2, \ |
462 | .handler = &gen_##name, \ |
463 | .oname = stringify(name), \ |
464 | }, \ |
465 | .oname = stringify(name), \ |
466 | } |
467 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
468 | { \ |
469 | .opc1 = op1, \ |
470 | .opc2 = op2, \ |
471 | .opc3 = op3, \ |
472 | .opc4 = 0xff, \ |
473 | .handler = { \ |
474 | .inval1 = invl, \ |
475 | .type = _typ, \ |
476 | .type2 = _typ2, \ |
477 | .handler = &gen_##name, \ |
478 | .oname = onam, \ |
479 | }, \ |
480 | .oname = onam, \ |
481 | } |
482 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
483 | { \ |
484 | .opc1 = op1, \ |
485 | .opc2 = op2, \ |
486 | .opc3 = op3, \ |
487 | .opc4 = op4, \ |
488 | .handler = { \ |
489 | .inval1 = invl, \ |
490 | .type = _typ, \ |
491 | .type2 = _typ2, \ |
492 | .handler = &gen_##name, \ |
493 | .oname = stringify(name), \ |
494 | }, \ |
495 | .oname = stringify(name), \ |
496 | } |
497 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
498 | { \ |
499 | .opc1 = op1, \ |
500 | .opc2 = op2, \ |
501 | .opc3 = op3, \ |
502 | .opc4 = op4, \ |
503 | .handler = { \ |
504 | .inval1 = invl, \ |
505 | .type = _typ, \ |
506 | .type2 = _typ2, \ |
507 | .handler = &gen_##name, \ |
508 | .oname = onam, \ |
509 | }, \ |
510 | .oname = onam, \ |
511 | } |
512 | #else |
513 | #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \ |
514 | { \ |
515 | .opc1 = op1, \ |
516 | .opc2 = op2, \ |
517 | .opc3 = op3, \ |
518 | .opc4 = 0xff, \ |
519 | .handler = { \ |
520 | .inval1 = invl, \ |
521 | .type = _typ, \ |
522 | .type2 = _typ2, \ |
523 | .handler = &gen_##name, \ |
524 | }, \ |
525 | .oname = stringify(name), \ |
526 | } |
527 | #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \ |
528 | { \ |
529 | .opc1 = op1, \ |
530 | .opc2 = op2, \ |
531 | .opc3 = op3, \ |
532 | .opc4 = 0xff, \ |
533 | .handler = { \ |
534 | .inval1 = invl1, \ |
535 | .inval2 = invl2, \ |
536 | .type = _typ, \ |
537 | .type2 = _typ2, \ |
538 | .handler = &gen_##name, \ |
539 | }, \ |
540 | .oname = stringify(name), \ |
541 | } |
542 | #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \ |
543 | { \ |
544 | .opc1 = op1, \ |
545 | .opc2 = op2, \ |
546 | .opc3 = op3, \ |
547 | .opc4 = 0xff, \ |
548 | .handler = { \ |
549 | .inval1 = invl, \ |
550 | .type = _typ, \ |
551 | .type2 = _typ2, \ |
552 | .handler = &gen_##name, \ |
553 | }, \ |
554 | .oname = onam, \ |
555 | } |
556 | #define GEN_OPCODE3(name, op1, op2, op3, op4, invl, _typ, _typ2) \ |
557 | { \ |
558 | .opc1 = op1, \ |
559 | .opc2 = op2, \ |
560 | .opc3 = op3, \ |
561 | .opc4 = op4, \ |
562 | .handler = { \ |
563 | .inval1 = invl, \ |
564 | .type = _typ, \ |
565 | .type2 = _typ2, \ |
566 | .handler = &gen_##name, \ |
567 | }, \ |
568 | .oname = stringify(name), \ |
569 | } |
570 | #define GEN_OPCODE4(name, onam, op1, op2, op3, op4, invl, _typ, _typ2) \ |
571 | { \ |
572 | .opc1 = op1, \ |
573 | .opc2 = op2, \ |
574 | .opc3 = op3, \ |
575 | .opc4 = op4, \ |
576 | .handler = { \ |
577 | .inval1 = invl, \ |
578 | .type = _typ, \ |
579 | .type2 = _typ2, \ |
580 | .handler = &gen_##name, \ |
581 | }, \ |
582 | .oname = onam, \ |
583 | } |
584 | #endif |
585 | |
586 | /* Invalid instruction */ |
587 | static void gen_invalid(DisasContext *ctx) |
588 | { |
589 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
590 | } |
591 | |
592 | static opc_handler_t invalid_handler = { |
593 | .inval1 = 0xFFFFFFFF, |
594 | .inval2 = 0xFFFFFFFF, |
595 | .type = PPC_NONE, |
596 | .type2 = PPC_NONE, |
597 | .handler = gen_invalid, |
598 | }; |
599 | |
600 | /*** Integer comparison ***/ |
601 | |
602 | static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf) |
603 | { |
604 | TCGv t0 = tcg_temp_new(); |
605 | TCGv t1 = tcg_temp_new(); |
606 | TCGv_i32 t = tcg_temp_new_i32(); |
607 | |
608 | tcg_gen_movi_tl(t0, CRF_EQ); |
609 | tcg_gen_movi_tl(t1, CRF_LT); |
610 | tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), |
611 | t0, arg0, arg1, t1, t0); |
612 | tcg_gen_movi_tl(t1, CRF_GT); |
613 | tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), |
614 | t0, arg0, arg1, t1, t0); |
615 | |
616 | tcg_gen_trunc_tl_i32(t, t0); |
617 | tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so); |
618 | tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t); |
619 | |
620 | tcg_temp_free(t0); |
621 | tcg_temp_free(t1); |
622 | tcg_temp_free_i32(t); |
623 | } |
624 | |
625 | static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf) |
626 | { |
627 | TCGv t0 = tcg_const_tl(arg1); |
628 | gen_op_cmp(arg0, t0, s, crf); |
629 | tcg_temp_free(t0); |
630 | } |
631 | |
632 | static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf) |
633 | { |
634 | TCGv t0, t1; |
635 | t0 = tcg_temp_new(); |
636 | t1 = tcg_temp_new(); |
637 | if (s) { |
638 | tcg_gen_ext32s_tl(t0, arg0); |
639 | tcg_gen_ext32s_tl(t1, arg1); |
640 | } else { |
641 | tcg_gen_ext32u_tl(t0, arg0); |
642 | tcg_gen_ext32u_tl(t1, arg1); |
643 | } |
644 | gen_op_cmp(t0, t1, s, crf); |
645 | tcg_temp_free(t1); |
646 | tcg_temp_free(t0); |
647 | } |
648 | |
649 | static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf) |
650 | { |
651 | TCGv t0 = tcg_const_tl(arg1); |
652 | gen_op_cmp32(arg0, t0, s, crf); |
653 | tcg_temp_free(t0); |
654 | } |
655 | |
656 | static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg) |
657 | { |
658 | if (NARROW_MODE(ctx)) { |
659 | gen_op_cmpi32(reg, 0, 1, 0); |
660 | } else { |
661 | gen_op_cmpi(reg, 0, 1, 0); |
662 | } |
663 | } |
664 | |
665 | /* cmp */ |
666 | static void gen_cmp(DisasContext *ctx) |
667 | { |
668 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
669 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
670 | 1, crfD(ctx->opcode)); |
671 | } else { |
672 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
673 | 1, crfD(ctx->opcode)); |
674 | } |
675 | } |
676 | |
677 | /* cmpi */ |
678 | static void gen_cmpi(DisasContext *ctx) |
679 | { |
680 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
681 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
682 | 1, crfD(ctx->opcode)); |
683 | } else { |
684 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode), |
685 | 1, crfD(ctx->opcode)); |
686 | } |
687 | } |
688 | |
689 | /* cmpl */ |
690 | static void gen_cmpl(DisasContext *ctx) |
691 | { |
692 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
693 | gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
694 | 0, crfD(ctx->opcode)); |
695 | } else { |
696 | gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
697 | 0, crfD(ctx->opcode)); |
698 | } |
699 | } |
700 | |
701 | /* cmpli */ |
702 | static void gen_cmpli(DisasContext *ctx) |
703 | { |
704 | if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) { |
705 | gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
706 | 0, crfD(ctx->opcode)); |
707 | } else { |
708 | gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode), |
709 | 0, crfD(ctx->opcode)); |
710 | } |
711 | } |
712 | |
713 | /* cmprb - range comparison: isupper, isaplha, islower*/ |
714 | static void gen_cmprb(DisasContext *ctx) |
715 | { |
716 | TCGv_i32 src1 = tcg_temp_new_i32(); |
717 | TCGv_i32 src2 = tcg_temp_new_i32(); |
718 | TCGv_i32 src2lo = tcg_temp_new_i32(); |
719 | TCGv_i32 src2hi = tcg_temp_new_i32(); |
720 | TCGv_i32 crf = cpu_crf[crfD(ctx->opcode)]; |
721 | |
722 | tcg_gen_trunc_tl_i32(src1, cpu_gpr[rA(ctx->opcode)]); |
723 | tcg_gen_trunc_tl_i32(src2, cpu_gpr[rB(ctx->opcode)]); |
724 | |
725 | tcg_gen_andi_i32(src1, src1, 0xFF); |
726 | tcg_gen_ext8u_i32(src2lo, src2); |
727 | tcg_gen_shri_i32(src2, src2, 8); |
728 | tcg_gen_ext8u_i32(src2hi, src2); |
729 | |
730 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); |
731 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); |
732 | tcg_gen_and_i32(crf, src2lo, src2hi); |
733 | |
734 | if (ctx->opcode & 0x00200000) { |
735 | tcg_gen_shri_i32(src2, src2, 8); |
736 | tcg_gen_ext8u_i32(src2lo, src2); |
737 | tcg_gen_shri_i32(src2, src2, 8); |
738 | tcg_gen_ext8u_i32(src2hi, src2); |
739 | tcg_gen_setcond_i32(TCG_COND_LEU, src2lo, src2lo, src1); |
740 | tcg_gen_setcond_i32(TCG_COND_LEU, src2hi, src1, src2hi); |
741 | tcg_gen_and_i32(src2lo, src2lo, src2hi); |
742 | tcg_gen_or_i32(crf, crf, src2lo); |
743 | } |
744 | tcg_gen_shli_i32(crf, crf, CRF_GT_BIT); |
745 | tcg_temp_free_i32(src1); |
746 | tcg_temp_free_i32(src2); |
747 | tcg_temp_free_i32(src2lo); |
748 | tcg_temp_free_i32(src2hi); |
749 | } |
750 | |
751 | #if defined(TARGET_PPC64) |
752 | /* cmpeqb */ |
753 | static void gen_cmpeqb(DisasContext *ctx) |
754 | { |
755 | gen_helper_cmpeqb(cpu_crf[crfD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
756 | cpu_gpr[rB(ctx->opcode)]); |
757 | } |
758 | #endif |
759 | |
760 | /* isel (PowerPC 2.03 specification) */ |
761 | static void gen_isel(DisasContext *ctx) |
762 | { |
763 | uint32_t bi = rC(ctx->opcode); |
764 | uint32_t mask = 0x08 >> (bi & 0x03); |
765 | TCGv t0 = tcg_temp_new(); |
766 | TCGv zr; |
767 | |
768 | tcg_gen_extu_i32_tl(t0, cpu_crf[bi >> 2]); |
769 | tcg_gen_andi_tl(t0, t0, mask); |
770 | |
771 | zr = tcg_const_tl(0); |
772 | tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rD(ctx->opcode)], t0, zr, |
773 | rA(ctx->opcode) ? cpu_gpr[rA(ctx->opcode)] : zr, |
774 | cpu_gpr[rB(ctx->opcode)]); |
775 | tcg_temp_free(zr); |
776 | tcg_temp_free(t0); |
777 | } |
778 | |
779 | /* cmpb: PowerPC 2.05 specification */ |
780 | static void gen_cmpb(DisasContext *ctx) |
781 | { |
782 | gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
783 | cpu_gpr[rB(ctx->opcode)]); |
784 | } |
785 | |
786 | /*** Integer arithmetic ***/ |
787 | |
788 | static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, |
789 | TCGv arg1, TCGv arg2, int sub) |
790 | { |
791 | TCGv t0 = tcg_temp_new(); |
792 | |
793 | tcg_gen_xor_tl(cpu_ov, arg0, arg2); |
794 | tcg_gen_xor_tl(t0, arg1, arg2); |
795 | if (sub) { |
796 | tcg_gen_and_tl(cpu_ov, cpu_ov, t0); |
797 | } else { |
798 | tcg_gen_andc_tl(cpu_ov, cpu_ov, t0); |
799 | } |
800 | tcg_temp_free(t0); |
801 | if (NARROW_MODE(ctx)) { |
802 | tcg_gen_extract_tl(cpu_ov, cpu_ov, 31, 1); |
803 | if (is_isa300(ctx)) { |
804 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); |
805 | } |
806 | } else { |
807 | if (is_isa300(ctx)) { |
808 | tcg_gen_extract_tl(cpu_ov32, cpu_ov, 31, 1); |
809 | } |
810 | tcg_gen_extract_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1, 1); |
811 | } |
812 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
813 | } |
814 | |
815 | static inline void gen_op_arith_compute_ca32(DisasContext *ctx, |
816 | TCGv res, TCGv arg0, TCGv arg1, |
817 | TCGv ca32, int sub) |
818 | { |
819 | TCGv t0; |
820 | |
821 | if (!is_isa300(ctx)) { |
822 | return; |
823 | } |
824 | |
825 | t0 = tcg_temp_new(); |
826 | if (sub) { |
827 | tcg_gen_eqv_tl(t0, arg0, arg1); |
828 | } else { |
829 | tcg_gen_xor_tl(t0, arg0, arg1); |
830 | } |
831 | tcg_gen_xor_tl(t0, t0, res); |
832 | tcg_gen_extract_tl(ca32, t0, 32, 1); |
833 | tcg_temp_free(t0); |
834 | } |
835 | |
836 | /* Common add function */ |
837 | static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
838 | TCGv arg2, TCGv ca, TCGv ca32, |
839 | bool add_ca, bool compute_ca, |
840 | bool compute_ov, bool compute_rc0) |
841 | { |
842 | TCGv t0 = ret; |
843 | |
844 | if (compute_ca || compute_ov) { |
845 | t0 = tcg_temp_new(); |
846 | } |
847 | |
848 | if (compute_ca) { |
849 | if (NARROW_MODE(ctx)) { |
850 | /* |
851 | * Caution: a non-obvious corner case of the spec is that |
852 | * we must produce the *entire* 64-bit addition, but |
853 | * produce the carry into bit 32. |
854 | */ |
855 | TCGv t1 = tcg_temp_new(); |
856 | tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */ |
857 | tcg_gen_add_tl(t0, arg1, arg2); |
858 | if (add_ca) { |
859 | tcg_gen_add_tl(t0, t0, ca); |
860 | } |
861 | tcg_gen_xor_tl(ca, t0, t1); /* bits changed w/ carry */ |
862 | tcg_temp_free(t1); |
863 | tcg_gen_extract_tl(ca, ca, 32, 1); |
864 | if (is_isa300(ctx)) { |
865 | tcg_gen_mov_tl(ca32, ca); |
866 | } |
867 | } else { |
868 | TCGv zero = tcg_const_tl(0); |
869 | if (add_ca) { |
870 | tcg_gen_add2_tl(t0, ca, arg1, zero, ca, zero); |
871 | tcg_gen_add2_tl(t0, ca, t0, ca, arg2, zero); |
872 | } else { |
873 | tcg_gen_add2_tl(t0, ca, arg1, zero, arg2, zero); |
874 | } |
875 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, ca32, 0); |
876 | tcg_temp_free(zero); |
877 | } |
878 | } else { |
879 | tcg_gen_add_tl(t0, arg1, arg2); |
880 | if (add_ca) { |
881 | tcg_gen_add_tl(t0, t0, ca); |
882 | } |
883 | } |
884 | |
885 | if (compute_ov) { |
886 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0); |
887 | } |
888 | if (unlikely(compute_rc0)) { |
889 | gen_set_Rc0(ctx, t0); |
890 | } |
891 | |
892 | if (t0 != ret) { |
893 | tcg_gen_mov_tl(ret, t0); |
894 | tcg_temp_free(t0); |
895 | } |
896 | } |
897 | /* Add functions with two operands */ |
898 | #define GEN_INT_ARITH_ADD(name, opc3, ca, add_ca, compute_ca, compute_ov) \ |
899 | static void glue(gen_, name)(DisasContext *ctx) \ |
900 | { \ |
901 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
902 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
903 | ca, glue(ca, 32), \ |
904 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
905 | } |
906 | /* Add functions with one operand and one immediate */ |
907 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, ca, \ |
908 | add_ca, compute_ca, compute_ov) \ |
909 | static void glue(gen_, name)(DisasContext *ctx) \ |
910 | { \ |
911 | TCGv t0 = tcg_const_tl(const_val); \ |
912 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \ |
913 | cpu_gpr[rA(ctx->opcode)], t0, \ |
914 | ca, glue(ca, 32), \ |
915 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
916 | tcg_temp_free(t0); \ |
917 | } |
918 | |
919 | /* add add. addo addo. */ |
920 | GEN_INT_ARITH_ADD(add, 0x08, cpu_ca, 0, 0, 0) |
921 | GEN_INT_ARITH_ADD(addo, 0x18, cpu_ca, 0, 0, 1) |
922 | /* addc addc. addco addco. */ |
923 | GEN_INT_ARITH_ADD(addc, 0x00, cpu_ca, 0, 1, 0) |
924 | GEN_INT_ARITH_ADD(addco, 0x10, cpu_ca, 0, 1, 1) |
925 | /* adde adde. addeo addeo. */ |
926 | GEN_INT_ARITH_ADD(adde, 0x04, cpu_ca, 1, 1, 0) |
927 | GEN_INT_ARITH_ADD(addeo, 0x14, cpu_ca, 1, 1, 1) |
928 | /* addme addme. addmeo addmeo. */ |
929 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, cpu_ca, 1, 1, 0) |
930 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, cpu_ca, 1, 1, 1) |
931 | /* addex */ |
932 | GEN_INT_ARITH_ADD(addex, 0x05, cpu_ov, 1, 1, 0); |
933 | /* addze addze. addzeo addzeo.*/ |
934 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, cpu_ca, 1, 1, 0) |
935 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, cpu_ca, 1, 1, 1) |
936 | /* addi */ |
937 | static void gen_addi(DisasContext *ctx) |
938 | { |
939 | target_long simm = SIMM(ctx->opcode); |
940 | |
941 | if (rA(ctx->opcode) == 0) { |
942 | /* li case */ |
943 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm); |
944 | } else { |
945 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
946 | cpu_gpr[rA(ctx->opcode)], simm); |
947 | } |
948 | } |
949 | /* addic addic.*/ |
950 | static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0) |
951 | { |
952 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
953 | gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
954 | c, cpu_ca, cpu_ca32, 0, 1, 0, compute_rc0); |
955 | tcg_temp_free(c); |
956 | } |
957 | |
958 | static void gen_addic(DisasContext *ctx) |
959 | { |
960 | gen_op_addic(ctx, 0); |
961 | } |
962 | |
963 | static void gen_addic_(DisasContext *ctx) |
964 | { |
965 | gen_op_addic(ctx, 1); |
966 | } |
967 | |
968 | /* addis */ |
969 | static void gen_addis(DisasContext *ctx) |
970 | { |
971 | target_long simm = SIMM(ctx->opcode); |
972 | |
973 | if (rA(ctx->opcode) == 0) { |
974 | /* lis case */ |
975 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16); |
976 | } else { |
977 | tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)], |
978 | cpu_gpr[rA(ctx->opcode)], simm << 16); |
979 | } |
980 | } |
981 | |
982 | /* addpcis */ |
983 | static void gen_addpcis(DisasContext *ctx) |
984 | { |
985 | target_long d = DX(ctx->opcode); |
986 | |
987 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], ctx->base.pc_next + (d << 16)); |
988 | } |
989 | |
990 | static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1, |
991 | TCGv arg2, int sign, int compute_ov) |
992 | { |
993 | TCGv_i32 t0 = tcg_temp_new_i32(); |
994 | TCGv_i32 t1 = tcg_temp_new_i32(); |
995 | TCGv_i32 t2 = tcg_temp_new_i32(); |
996 | TCGv_i32 t3 = tcg_temp_new_i32(); |
997 | |
998 | tcg_gen_trunc_tl_i32(t0, arg1); |
999 | tcg_gen_trunc_tl_i32(t1, arg2); |
1000 | if (sign) { |
1001 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1002 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); |
1003 | tcg_gen_and_i32(t2, t2, t3); |
1004 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); |
1005 | tcg_gen_or_i32(t2, t2, t3); |
1006 | tcg_gen_movi_i32(t3, 0); |
1007 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); |
1008 | tcg_gen_div_i32(t3, t0, t1); |
1009 | tcg_gen_extu_i32_tl(ret, t3); |
1010 | } else { |
1011 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t1, 0); |
1012 | tcg_gen_movi_i32(t3, 0); |
1013 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); |
1014 | tcg_gen_divu_i32(t3, t0, t1); |
1015 | tcg_gen_extu_i32_tl(ret, t3); |
1016 | } |
1017 | if (compute_ov) { |
1018 | tcg_gen_extu_i32_tl(cpu_ov, t2); |
1019 | if (is_isa300(ctx)) { |
1020 | tcg_gen_extu_i32_tl(cpu_ov32, t2); |
1021 | } |
1022 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1023 | } |
1024 | tcg_temp_free_i32(t0); |
1025 | tcg_temp_free_i32(t1); |
1026 | tcg_temp_free_i32(t2); |
1027 | tcg_temp_free_i32(t3); |
1028 | |
1029 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1030 | gen_set_Rc0(ctx, ret); |
1031 | } |
1032 | } |
1033 | /* Div functions */ |
1034 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ |
1035 | static void glue(gen_, name)(DisasContext *ctx) \ |
1036 | { \ |
1037 | gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1038 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1039 | sign, compute_ov); \ |
1040 | } |
1041 | /* divwu divwu. divwuo divwuo. */ |
1042 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0); |
1043 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1); |
1044 | /* divw divw. divwo divwo. */ |
1045 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0); |
1046 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1); |
1047 | |
1048 | /* div[wd]eu[o][.] */ |
1049 | #define GEN_DIVE(name, hlpr, compute_ov) \ |
1050 | static void gen_##name(DisasContext *ctx) \ |
1051 | { \ |
1052 | TCGv_i32 t0 = tcg_const_i32(compute_ov); \ |
1053 | gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \ |
1054 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \ |
1055 | tcg_temp_free_i32(t0); \ |
1056 | if (unlikely(Rc(ctx->opcode) != 0)) { \ |
1057 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \ |
1058 | } \ |
1059 | } |
1060 | |
1061 | GEN_DIVE(divweu, divweu, 0); |
1062 | GEN_DIVE(divweuo, divweu, 1); |
1063 | GEN_DIVE(divwe, divwe, 0); |
1064 | GEN_DIVE(divweo, divwe, 1); |
1065 | |
1066 | #if defined(TARGET_PPC64) |
1067 | static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1068 | TCGv arg2, int sign, int compute_ov) |
1069 | { |
1070 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1071 | TCGv_i64 t1 = tcg_temp_new_i64(); |
1072 | TCGv_i64 t2 = tcg_temp_new_i64(); |
1073 | TCGv_i64 t3 = tcg_temp_new_i64(); |
1074 | |
1075 | tcg_gen_mov_i64(t0, arg1); |
1076 | tcg_gen_mov_i64(t1, arg2); |
1077 | if (sign) { |
1078 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1079 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); |
1080 | tcg_gen_and_i64(t2, t2, t3); |
1081 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); |
1082 | tcg_gen_or_i64(t2, t2, t3); |
1083 | tcg_gen_movi_i64(t3, 0); |
1084 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); |
1085 | tcg_gen_div_i64(ret, t0, t1); |
1086 | } else { |
1087 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t1, 0); |
1088 | tcg_gen_movi_i64(t3, 0); |
1089 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); |
1090 | tcg_gen_divu_i64(ret, t0, t1); |
1091 | } |
1092 | if (compute_ov) { |
1093 | tcg_gen_mov_tl(cpu_ov, t2); |
1094 | if (is_isa300(ctx)) { |
1095 | tcg_gen_mov_tl(cpu_ov32, t2); |
1096 | } |
1097 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1098 | } |
1099 | tcg_temp_free_i64(t0); |
1100 | tcg_temp_free_i64(t1); |
1101 | tcg_temp_free_i64(t2); |
1102 | tcg_temp_free_i64(t3); |
1103 | |
1104 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1105 | gen_set_Rc0(ctx, ret); |
1106 | } |
1107 | } |
1108 | |
1109 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
1110 | static void glue(gen_, name)(DisasContext *ctx) \ |
1111 | { \ |
1112 | gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1113 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1114 | sign, compute_ov); \ |
1115 | } |
1116 | /* divdu divdu. divduo divduo. */ |
1117 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0); |
1118 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1); |
1119 | /* divd divd. divdo divdo. */ |
1120 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0); |
1121 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1); |
1122 | |
1123 | GEN_DIVE(divdeu, divdeu, 0); |
1124 | GEN_DIVE(divdeuo, divdeu, 1); |
1125 | GEN_DIVE(divde, divde, 0); |
1126 | GEN_DIVE(divdeo, divde, 1); |
1127 | #endif |
1128 | |
1129 | static inline void gen_op_arith_modw(DisasContext *ctx, TCGv ret, TCGv arg1, |
1130 | TCGv arg2, int sign) |
1131 | { |
1132 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1133 | TCGv_i32 t1 = tcg_temp_new_i32(); |
1134 | |
1135 | tcg_gen_trunc_tl_i32(t0, arg1); |
1136 | tcg_gen_trunc_tl_i32(t1, arg2); |
1137 | if (sign) { |
1138 | TCGv_i32 t2 = tcg_temp_new_i32(); |
1139 | TCGv_i32 t3 = tcg_temp_new_i32(); |
1140 | tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); |
1141 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); |
1142 | tcg_gen_and_i32(t2, t2, t3); |
1143 | tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); |
1144 | tcg_gen_or_i32(t2, t2, t3); |
1145 | tcg_gen_movi_i32(t3, 0); |
1146 | tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); |
1147 | tcg_gen_rem_i32(t3, t0, t1); |
1148 | tcg_gen_ext_i32_tl(ret, t3); |
1149 | tcg_temp_free_i32(t2); |
1150 | tcg_temp_free_i32(t3); |
1151 | } else { |
1152 | TCGv_i32 t2 = tcg_const_i32(1); |
1153 | TCGv_i32 t3 = tcg_const_i32(0); |
1154 | tcg_gen_movcond_i32(TCG_COND_EQ, t1, t1, t3, t2, t1); |
1155 | tcg_gen_remu_i32(t3, t0, t1); |
1156 | tcg_gen_extu_i32_tl(ret, t3); |
1157 | tcg_temp_free_i32(t2); |
1158 | tcg_temp_free_i32(t3); |
1159 | } |
1160 | tcg_temp_free_i32(t0); |
1161 | tcg_temp_free_i32(t1); |
1162 | } |
1163 | |
1164 | #define GEN_INT_ARITH_MODW(name, opc3, sign) \ |
1165 | static void glue(gen_, name)(DisasContext *ctx) \ |
1166 | { \ |
1167 | gen_op_arith_modw(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1168 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1169 | sign); \ |
1170 | } |
1171 | |
1172 | GEN_INT_ARITH_MODW(moduw, 0x08, 0); |
1173 | GEN_INT_ARITH_MODW(modsw, 0x18, 1); |
1174 | |
1175 | #if defined(TARGET_PPC64) |
1176 | static inline void gen_op_arith_modd(DisasContext *ctx, TCGv ret, TCGv arg1, |
1177 | TCGv arg2, int sign) |
1178 | { |
1179 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1180 | TCGv_i64 t1 = tcg_temp_new_i64(); |
1181 | |
1182 | tcg_gen_mov_i64(t0, arg1); |
1183 | tcg_gen_mov_i64(t1, arg2); |
1184 | if (sign) { |
1185 | TCGv_i64 t2 = tcg_temp_new_i64(); |
1186 | TCGv_i64 t3 = tcg_temp_new_i64(); |
1187 | tcg_gen_setcondi_i64(TCG_COND_EQ, t2, t0, INT64_MIN); |
1188 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, -1); |
1189 | tcg_gen_and_i64(t2, t2, t3); |
1190 | tcg_gen_setcondi_i64(TCG_COND_EQ, t3, t1, 0); |
1191 | tcg_gen_or_i64(t2, t2, t3); |
1192 | tcg_gen_movi_i64(t3, 0); |
1193 | tcg_gen_movcond_i64(TCG_COND_NE, t1, t2, t3, t2, t1); |
1194 | tcg_gen_rem_i64(ret, t0, t1); |
1195 | tcg_temp_free_i64(t2); |
1196 | tcg_temp_free_i64(t3); |
1197 | } else { |
1198 | TCGv_i64 t2 = tcg_const_i64(1); |
1199 | TCGv_i64 t3 = tcg_const_i64(0); |
1200 | tcg_gen_movcond_i64(TCG_COND_EQ, t1, t1, t3, t2, t1); |
1201 | tcg_gen_remu_i64(ret, t0, t1); |
1202 | tcg_temp_free_i64(t2); |
1203 | tcg_temp_free_i64(t3); |
1204 | } |
1205 | tcg_temp_free_i64(t0); |
1206 | tcg_temp_free_i64(t1); |
1207 | } |
1208 | |
1209 | #define GEN_INT_ARITH_MODD(name, opc3, sign) \ |
1210 | static void glue(gen_, name)(DisasContext *ctx) \ |
1211 | { \ |
1212 | gen_op_arith_modd(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1213 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1214 | sign); \ |
1215 | } |
1216 | |
1217 | GEN_INT_ARITH_MODD(modud, 0x08, 0); |
1218 | GEN_INT_ARITH_MODD(modsd, 0x18, 1); |
1219 | #endif |
1220 | |
1221 | /* mulhw mulhw. */ |
1222 | static void gen_mulhw(DisasContext *ctx) |
1223 | { |
1224 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1225 | TCGv_i32 t1 = tcg_temp_new_i32(); |
1226 | |
1227 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1228 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); |
1229 | tcg_gen_muls2_i32(t0, t1, t0, t1); |
1230 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); |
1231 | tcg_temp_free_i32(t0); |
1232 | tcg_temp_free_i32(t1); |
1233 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1234 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1235 | } |
1236 | } |
1237 | |
1238 | /* mulhwu mulhwu. */ |
1239 | static void gen_mulhwu(DisasContext *ctx) |
1240 | { |
1241 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1242 | TCGv_i32 t1 = tcg_temp_new_i32(); |
1243 | |
1244 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1245 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); |
1246 | tcg_gen_mulu2_i32(t0, t1, t0, t1); |
1247 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1); |
1248 | tcg_temp_free_i32(t0); |
1249 | tcg_temp_free_i32(t1); |
1250 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1251 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1252 | } |
1253 | } |
1254 | |
1255 | /* mullw mullw. */ |
1256 | static void gen_mullw(DisasContext *ctx) |
1257 | { |
1258 | #if defined(TARGET_PPC64) |
1259 | TCGv_i64 t0, t1; |
1260 | t0 = tcg_temp_new_i64(); |
1261 | t1 = tcg_temp_new_i64(); |
1262 | tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]); |
1263 | tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]); |
1264 | tcg_gen_mul_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1265 | tcg_temp_free(t0); |
1266 | tcg_temp_free(t1); |
1267 | #else |
1268 | tcg_gen_mul_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1269 | cpu_gpr[rB(ctx->opcode)]); |
1270 | #endif |
1271 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1272 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1273 | } |
1274 | } |
1275 | |
1276 | /* mullwo mullwo. */ |
1277 | static void gen_mullwo(DisasContext *ctx) |
1278 | { |
1279 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1280 | TCGv_i32 t1 = tcg_temp_new_i32(); |
1281 | |
1282 | tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); |
1283 | tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); |
1284 | tcg_gen_muls2_i32(t0, t1, t0, t1); |
1285 | #if defined(TARGET_PPC64) |
1286 | tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); |
1287 | #else |
1288 | tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], t0); |
1289 | #endif |
1290 | |
1291 | tcg_gen_sari_i32(t0, t0, 31); |
1292 | tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1); |
1293 | tcg_gen_extu_i32_tl(cpu_ov, t0); |
1294 | if (is_isa300(ctx)) { |
1295 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); |
1296 | } |
1297 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1298 | |
1299 | tcg_temp_free_i32(t0); |
1300 | tcg_temp_free_i32(t1); |
1301 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1302 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1303 | } |
1304 | } |
1305 | |
1306 | /* mulli */ |
1307 | static void gen_mulli(DisasContext *ctx) |
1308 | { |
1309 | tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1310 | SIMM(ctx->opcode)); |
1311 | } |
1312 | |
1313 | #if defined(TARGET_PPC64) |
1314 | /* mulhd mulhd. */ |
1315 | static void gen_mulhd(DisasContext *ctx) |
1316 | { |
1317 | TCGv lo = tcg_temp_new(); |
1318 | tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)], |
1319 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1320 | tcg_temp_free(lo); |
1321 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1322 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1323 | } |
1324 | } |
1325 | |
1326 | /* mulhdu mulhdu. */ |
1327 | static void gen_mulhdu(DisasContext *ctx) |
1328 | { |
1329 | TCGv lo = tcg_temp_new(); |
1330 | tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)], |
1331 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1332 | tcg_temp_free(lo); |
1333 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1334 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1335 | } |
1336 | } |
1337 | |
1338 | /* mulld mulld. */ |
1339 | static void gen_mulld(DisasContext *ctx) |
1340 | { |
1341 | tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1342 | cpu_gpr[rB(ctx->opcode)]); |
1343 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1344 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1345 | } |
1346 | } |
1347 | |
1348 | /* mulldo mulldo. */ |
1349 | static void gen_mulldo(DisasContext *ctx) |
1350 | { |
1351 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1352 | TCGv_i64 t1 = tcg_temp_new_i64(); |
1353 | |
1354 | tcg_gen_muls2_i64(t0, t1, cpu_gpr[rA(ctx->opcode)], |
1355 | cpu_gpr[rB(ctx->opcode)]); |
1356 | tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], t0); |
1357 | |
1358 | tcg_gen_sari_i64(t0, t0, 63); |
1359 | tcg_gen_setcond_i64(TCG_COND_NE, cpu_ov, t0, t1); |
1360 | if (is_isa300(ctx)) { |
1361 | tcg_gen_mov_tl(cpu_ov32, cpu_ov); |
1362 | } |
1363 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
1364 | |
1365 | tcg_temp_free_i64(t0); |
1366 | tcg_temp_free_i64(t1); |
1367 | |
1368 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1369 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1370 | } |
1371 | } |
1372 | #endif |
1373 | |
1374 | /* Common subf function */ |
1375 | static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, |
1376 | TCGv arg2, bool add_ca, bool compute_ca, |
1377 | bool compute_ov, bool compute_rc0) |
1378 | { |
1379 | TCGv t0 = ret; |
1380 | |
1381 | if (compute_ca || compute_ov) { |
1382 | t0 = tcg_temp_new(); |
1383 | } |
1384 | |
1385 | if (compute_ca) { |
1386 | /* dest = ~arg1 + arg2 [+ ca]. */ |
1387 | if (NARROW_MODE(ctx)) { |
1388 | /* |
1389 | * Caution: a non-obvious corner case of the spec is that |
1390 | * we must produce the *entire* 64-bit addition, but |
1391 | * produce the carry into bit 32. |
1392 | */ |
1393 | TCGv inv1 = tcg_temp_new(); |
1394 | TCGv t1 = tcg_temp_new(); |
1395 | tcg_gen_not_tl(inv1, arg1); |
1396 | if (add_ca) { |
1397 | tcg_gen_add_tl(t0, arg2, cpu_ca); |
1398 | } else { |
1399 | tcg_gen_addi_tl(t0, arg2, 1); |
1400 | } |
1401 | tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */ |
1402 | tcg_gen_add_tl(t0, t0, inv1); |
1403 | tcg_temp_free(inv1); |
1404 | tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */ |
1405 | tcg_temp_free(t1); |
1406 | tcg_gen_extract_tl(cpu_ca, cpu_ca, 32, 1); |
1407 | if (is_isa300(ctx)) { |
1408 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); |
1409 | } |
1410 | } else if (add_ca) { |
1411 | TCGv zero, inv1 = tcg_temp_new(); |
1412 | tcg_gen_not_tl(inv1, arg1); |
1413 | zero = tcg_const_tl(0); |
1414 | tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero); |
1415 | tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero); |
1416 | gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, cpu_ca32, 0); |
1417 | tcg_temp_free(zero); |
1418 | tcg_temp_free(inv1); |
1419 | } else { |
1420 | tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1); |
1421 | tcg_gen_sub_tl(t0, arg2, arg1); |
1422 | gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, cpu_ca32, 1); |
1423 | } |
1424 | } else if (add_ca) { |
1425 | /* |
1426 | * Since we're ignoring carry-out, we can simplify the |
1427 | * standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. |
1428 | */ |
1429 | tcg_gen_sub_tl(t0, arg2, arg1); |
1430 | tcg_gen_add_tl(t0, t0, cpu_ca); |
1431 | tcg_gen_subi_tl(t0, t0, 1); |
1432 | } else { |
1433 | tcg_gen_sub_tl(t0, arg2, arg1); |
1434 | } |
1435 | |
1436 | if (compute_ov) { |
1437 | gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1); |
1438 | } |
1439 | if (unlikely(compute_rc0)) { |
1440 | gen_set_Rc0(ctx, t0); |
1441 | } |
1442 | |
1443 | if (t0 != ret) { |
1444 | tcg_gen_mov_tl(ret, t0); |
1445 | tcg_temp_free(t0); |
1446 | } |
1447 | } |
1448 | /* Sub functions with Two operands functions */ |
1449 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ |
1450 | static void glue(gen_, name)(DisasContext *ctx) \ |
1451 | { \ |
1452 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1453 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \ |
1454 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
1455 | } |
1456 | /* Sub functions with one operand and one immediate */ |
1457 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ |
1458 | add_ca, compute_ca, compute_ov) \ |
1459 | static void glue(gen_, name)(DisasContext *ctx) \ |
1460 | { \ |
1461 | TCGv t0 = tcg_const_tl(const_val); \ |
1462 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \ |
1463 | cpu_gpr[rA(ctx->opcode)], t0, \ |
1464 | add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \ |
1465 | tcg_temp_free(t0); \ |
1466 | } |
1467 | /* subf subf. subfo subfo. */ |
1468 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
1469 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
1470 | /* subfc subfc. subfco subfco. */ |
1471 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
1472 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
1473 | /* subfe subfe. subfeo subfo. */ |
1474 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
1475 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
1476 | /* subfme subfme. subfmeo subfmeo. */ |
1477 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
1478 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
1479 | /* subfze subfze. subfzeo subfzeo.*/ |
1480 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
1481 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
1482 | |
1483 | /* subfic */ |
1484 | static void gen_subfic(DisasContext *ctx) |
1485 | { |
1486 | TCGv c = tcg_const_tl(SIMM(ctx->opcode)); |
1487 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1488 | c, 0, 1, 0, 0); |
1489 | tcg_temp_free(c); |
1490 | } |
1491 | |
1492 | /* neg neg. nego nego. */ |
1493 | static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov) |
1494 | { |
1495 | TCGv zero = tcg_const_tl(0); |
1496 | gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
1497 | zero, 0, 0, compute_ov, Rc(ctx->opcode)); |
1498 | tcg_temp_free(zero); |
1499 | } |
1500 | |
1501 | static void gen_neg(DisasContext *ctx) |
1502 | { |
1503 | tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
1504 | if (unlikely(Rc(ctx->opcode))) { |
1505 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
1506 | } |
1507 | } |
1508 | |
1509 | static void gen_nego(DisasContext *ctx) |
1510 | { |
1511 | gen_op_arith_neg(ctx, 1); |
1512 | } |
1513 | |
1514 | /*** Integer logical ***/ |
1515 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
1516 | static void glue(gen_, name)(DisasContext *ctx) \ |
1517 | { \ |
1518 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \ |
1519 | cpu_gpr[rB(ctx->opcode)]); \ |
1520 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1521 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1522 | } |
1523 | |
1524 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
1525 | static void glue(gen_, name)(DisasContext *ctx) \ |
1526 | { \ |
1527 | tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \ |
1528 | if (unlikely(Rc(ctx->opcode) != 0)) \ |
1529 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \ |
1530 | } |
1531 | |
1532 | /* and & and. */ |
1533 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER); |
1534 | /* andc & andc. */ |
1535 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER); |
1536 | |
1537 | /* andi. */ |
1538 | static void gen_andi_(DisasContext *ctx) |
1539 | { |
1540 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1541 | UIMM(ctx->opcode)); |
1542 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1543 | } |
1544 | |
1545 | /* andis. */ |
1546 | static void gen_andis_(DisasContext *ctx) |
1547 | { |
1548 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1549 | UIMM(ctx->opcode) << 16); |
1550 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1551 | } |
1552 | |
1553 | /* cntlzw */ |
1554 | static void gen_cntlzw(DisasContext *ctx) |
1555 | { |
1556 | TCGv_i32 t = tcg_temp_new_i32(); |
1557 | |
1558 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); |
1559 | tcg_gen_clzi_i32(t, t, 32); |
1560 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); |
1561 | tcg_temp_free_i32(t); |
1562 | |
1563 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1564 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1565 | } |
1566 | } |
1567 | |
1568 | /* cnttzw */ |
1569 | static void gen_cnttzw(DisasContext *ctx) |
1570 | { |
1571 | TCGv_i32 t = tcg_temp_new_i32(); |
1572 | |
1573 | tcg_gen_trunc_tl_i32(t, cpu_gpr[rS(ctx->opcode)]); |
1574 | tcg_gen_ctzi_i32(t, t, 32); |
1575 | tcg_gen_extu_i32_tl(cpu_gpr[rA(ctx->opcode)], t); |
1576 | tcg_temp_free_i32(t); |
1577 | |
1578 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1579 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1580 | } |
1581 | } |
1582 | |
1583 | /* eqv & eqv. */ |
1584 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER); |
1585 | /* extsb & extsb. */ |
1586 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER); |
1587 | /* extsh & extsh. */ |
1588 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER); |
1589 | /* nand & nand. */ |
1590 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER); |
1591 | /* nor & nor. */ |
1592 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER); |
1593 | |
1594 | #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
1595 | static void gen_pause(DisasContext *ctx) |
1596 | { |
1597 | TCGv_i32 t0 = tcg_const_i32(0); |
1598 | tcg_gen_st_i32(t0, cpu_env, |
1599 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); |
1600 | tcg_temp_free_i32(t0); |
1601 | |
1602 | /* Stop translation, this gives other CPUs a chance to run */ |
1603 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
1604 | } |
1605 | #endif /* defined(TARGET_PPC64) */ |
1606 | |
1607 | /* or & or. */ |
1608 | static void gen_or(DisasContext *ctx) |
1609 | { |
1610 | int rs, ra, rb; |
1611 | |
1612 | rs = rS(ctx->opcode); |
1613 | ra = rA(ctx->opcode); |
1614 | rb = rB(ctx->opcode); |
1615 | /* Optimisation for mr. ri case */ |
1616 | if (rs != ra || rs != rb) { |
1617 | if (rs != rb) { |
1618 | tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]); |
1619 | } else { |
1620 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]); |
1621 | } |
1622 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1623 | gen_set_Rc0(ctx, cpu_gpr[ra]); |
1624 | } |
1625 | } else if (unlikely(Rc(ctx->opcode) != 0)) { |
1626 | gen_set_Rc0(ctx, cpu_gpr[rs]); |
1627 | #if defined(TARGET_PPC64) |
1628 | } else if (rs != 0) { /* 0 is nop */ |
1629 | int prio = 0; |
1630 | |
1631 | switch (rs) { |
1632 | case 1: |
1633 | /* Set process priority to low */ |
1634 | prio = 2; |
1635 | break; |
1636 | case 6: |
1637 | /* Set process priority to medium-low */ |
1638 | prio = 3; |
1639 | break; |
1640 | case 2: |
1641 | /* Set process priority to normal */ |
1642 | prio = 4; |
1643 | break; |
1644 | #if !defined(CONFIG_USER_ONLY) |
1645 | case 31: |
1646 | if (!ctx->pr) { |
1647 | /* Set process priority to very low */ |
1648 | prio = 1; |
1649 | } |
1650 | break; |
1651 | case 5: |
1652 | if (!ctx->pr) { |
1653 | /* Set process priority to medium-hight */ |
1654 | prio = 5; |
1655 | } |
1656 | break; |
1657 | case 3: |
1658 | if (!ctx->pr) { |
1659 | /* Set process priority to high */ |
1660 | prio = 6; |
1661 | } |
1662 | break; |
1663 | case 7: |
1664 | if (ctx->hv && !ctx->pr) { |
1665 | /* Set process priority to very high */ |
1666 | prio = 7; |
1667 | } |
1668 | break; |
1669 | #endif |
1670 | default: |
1671 | break; |
1672 | } |
1673 | if (prio) { |
1674 | TCGv t0 = tcg_temp_new(); |
1675 | gen_load_spr(t0, SPR_PPR); |
1676 | tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL); |
1677 | tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50); |
1678 | gen_store_spr(SPR_PPR, t0); |
1679 | tcg_temp_free(t0); |
1680 | } |
1681 | #if !defined(CONFIG_USER_ONLY) |
1682 | /* |
1683 | * Pause out of TCG otherwise spin loops with smt_low eat too |
1684 | * much CPU and the kernel hangs. This applies to all |
1685 | * encodings other than no-op, e.g., miso(rs=26), yield(27), |
1686 | * mdoio(29), mdoom(30), and all currently undefined. |
1687 | */ |
1688 | gen_pause(ctx); |
1689 | #endif |
1690 | #endif |
1691 | } |
1692 | } |
1693 | /* orc & orc. */ |
1694 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER); |
1695 | |
1696 | /* xor & xor. */ |
1697 | static void gen_xor(DisasContext *ctx) |
1698 | { |
1699 | /* Optimisation for "set to zero" case */ |
1700 | if (rS(ctx->opcode) != rB(ctx->opcode)) { |
1701 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1702 | cpu_gpr[rB(ctx->opcode)]); |
1703 | } else { |
1704 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
1705 | } |
1706 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1707 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1708 | } |
1709 | } |
1710 | |
1711 | /* ori */ |
1712 | static void gen_ori(DisasContext *ctx) |
1713 | { |
1714 | target_ulong uimm = UIMM(ctx->opcode); |
1715 | |
1716 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1717 | return; |
1718 | } |
1719 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1720 | } |
1721 | |
1722 | /* oris */ |
1723 | static void gen_oris(DisasContext *ctx) |
1724 | { |
1725 | target_ulong uimm = UIMM(ctx->opcode); |
1726 | |
1727 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1728 | /* NOP */ |
1729 | return; |
1730 | } |
1731 | tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1732 | uimm << 16); |
1733 | } |
1734 | |
1735 | /* xori */ |
1736 | static void gen_xori(DisasContext *ctx) |
1737 | { |
1738 | target_ulong uimm = UIMM(ctx->opcode); |
1739 | |
1740 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1741 | /* NOP */ |
1742 | return; |
1743 | } |
1744 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm); |
1745 | } |
1746 | |
1747 | /* xoris */ |
1748 | static void gen_xoris(DisasContext *ctx) |
1749 | { |
1750 | target_ulong uimm = UIMM(ctx->opcode); |
1751 | |
1752 | if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) { |
1753 | /* NOP */ |
1754 | return; |
1755 | } |
1756 | tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], |
1757 | uimm << 16); |
1758 | } |
1759 | |
1760 | /* popcntb : PowerPC 2.03 specification */ |
1761 | static void gen_popcntb(DisasContext *ctx) |
1762 | { |
1763 | gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1764 | } |
1765 | |
1766 | static void gen_popcntw(DisasContext *ctx) |
1767 | { |
1768 | #if defined(TARGET_PPC64) |
1769 | gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1770 | #else |
1771 | tcg_gen_ctpop_i32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1772 | #endif |
1773 | } |
1774 | |
1775 | #if defined(TARGET_PPC64) |
1776 | /* popcntd: PowerPC 2.06 specification */ |
1777 | static void gen_popcntd(DisasContext *ctx) |
1778 | { |
1779 | tcg_gen_ctpop_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); |
1780 | } |
1781 | #endif |
1782 | |
1783 | /* prtyw: PowerPC 2.05 specification */ |
1784 | static void gen_prtyw(DisasContext *ctx) |
1785 | { |
1786 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; |
1787 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; |
1788 | TCGv t0 = tcg_temp_new(); |
1789 | tcg_gen_shri_tl(t0, rs, 16); |
1790 | tcg_gen_xor_tl(ra, rs, t0); |
1791 | tcg_gen_shri_tl(t0, ra, 8); |
1792 | tcg_gen_xor_tl(ra, ra, t0); |
1793 | tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL); |
1794 | tcg_temp_free(t0); |
1795 | } |
1796 | |
1797 | #if defined(TARGET_PPC64) |
1798 | /* prtyd: PowerPC 2.05 specification */ |
1799 | static void gen_prtyd(DisasContext *ctx) |
1800 | { |
1801 | TCGv ra = cpu_gpr[rA(ctx->opcode)]; |
1802 | TCGv rs = cpu_gpr[rS(ctx->opcode)]; |
1803 | TCGv t0 = tcg_temp_new(); |
1804 | tcg_gen_shri_tl(t0, rs, 32); |
1805 | tcg_gen_xor_tl(ra, rs, t0); |
1806 | tcg_gen_shri_tl(t0, ra, 16); |
1807 | tcg_gen_xor_tl(ra, ra, t0); |
1808 | tcg_gen_shri_tl(t0, ra, 8); |
1809 | tcg_gen_xor_tl(ra, ra, t0); |
1810 | tcg_gen_andi_tl(ra, ra, 1); |
1811 | tcg_temp_free(t0); |
1812 | } |
1813 | #endif |
1814 | |
1815 | #if defined(TARGET_PPC64) |
1816 | /* bpermd */ |
1817 | static void gen_bpermd(DisasContext *ctx) |
1818 | { |
1819 | gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)], |
1820 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
1821 | } |
1822 | #endif |
1823 | |
1824 | #if defined(TARGET_PPC64) |
1825 | /* extsw & extsw. */ |
1826 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B); |
1827 | |
1828 | /* cntlzd */ |
1829 | static void gen_cntlzd(DisasContext *ctx) |
1830 | { |
1831 | tcg_gen_clzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
1832 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1833 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1834 | } |
1835 | } |
1836 | |
1837 | /* cnttzd */ |
1838 | static void gen_cnttzd(DisasContext *ctx) |
1839 | { |
1840 | tcg_gen_ctzi_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], 64); |
1841 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1842 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
1843 | } |
1844 | } |
1845 | |
1846 | /* darn */ |
1847 | static void gen_darn(DisasContext *ctx) |
1848 | { |
1849 | int l = L(ctx->opcode); |
1850 | |
1851 | if (l > 2) { |
1852 | tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); |
1853 | } else { |
1854 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
1855 | gen_io_start(); |
1856 | } |
1857 | if (l == 0) { |
1858 | gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); |
1859 | } else { |
1860 | /* Return 64-bit random for both CRN and RRN */ |
1861 | gen_helper_darn64(cpu_gpr[rD(ctx->opcode)]); |
1862 | } |
1863 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
1864 | gen_stop_exception(ctx); |
1865 | } |
1866 | } |
1867 | } |
1868 | #endif |
1869 | |
1870 | /*** Integer rotate ***/ |
1871 | |
1872 | /* rlwimi & rlwimi. */ |
1873 | static void gen_rlwimi(DisasContext *ctx) |
1874 | { |
1875 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1876 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; |
1877 | uint32_t sh = SH(ctx->opcode); |
1878 | uint32_t mb = MB(ctx->opcode); |
1879 | uint32_t me = ME(ctx->opcode); |
1880 | |
1881 | if (sh == (31 - me) && mb <= me) { |
1882 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); |
1883 | } else { |
1884 | target_ulong mask; |
1885 | TCGv t1; |
1886 | |
1887 | #if defined(TARGET_PPC64) |
1888 | mb += 32; |
1889 | me += 32; |
1890 | #endif |
1891 | mask = MASK(mb, me); |
1892 | |
1893 | t1 = tcg_temp_new(); |
1894 | if (mask <= 0xffffffffu) { |
1895 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1896 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1897 | tcg_gen_rotli_i32(t0, t0, sh); |
1898 | tcg_gen_extu_i32_tl(t1, t0); |
1899 | tcg_temp_free_i32(t0); |
1900 | } else { |
1901 | #if defined(TARGET_PPC64) |
1902 | tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32); |
1903 | tcg_gen_rotli_i64(t1, t1, sh); |
1904 | #else |
1905 | g_assert_not_reached(); |
1906 | #endif |
1907 | } |
1908 | |
1909 | tcg_gen_andi_tl(t1, t1, mask); |
1910 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); |
1911 | tcg_gen_or_tl(t_ra, t_ra, t1); |
1912 | tcg_temp_free(t1); |
1913 | } |
1914 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1915 | gen_set_Rc0(ctx, t_ra); |
1916 | } |
1917 | } |
1918 | |
1919 | /* rlwinm & rlwinm. */ |
1920 | static void gen_rlwinm(DisasContext *ctx) |
1921 | { |
1922 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1923 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; |
1924 | int sh = SH(ctx->opcode); |
1925 | int mb = MB(ctx->opcode); |
1926 | int me = ME(ctx->opcode); |
1927 | int len = me - mb + 1; |
1928 | int rsh = (32 - sh) & 31; |
1929 | |
1930 | if (sh != 0 && len > 0 && me == (31 - sh)) { |
1931 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); |
1932 | } else if (me == 31 && rsh + len <= 32) { |
1933 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); |
1934 | } else { |
1935 | target_ulong mask; |
1936 | #if defined(TARGET_PPC64) |
1937 | mb += 32; |
1938 | me += 32; |
1939 | #endif |
1940 | mask = MASK(mb, me); |
1941 | if (sh == 0) { |
1942 | tcg_gen_andi_tl(t_ra, t_rs, mask); |
1943 | } else if (mask <= 0xffffffffu) { |
1944 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1945 | tcg_gen_trunc_tl_i32(t0, t_rs); |
1946 | tcg_gen_rotli_i32(t0, t0, sh); |
1947 | tcg_gen_andi_i32(t0, t0, mask); |
1948 | tcg_gen_extu_i32_tl(t_ra, t0); |
1949 | tcg_temp_free_i32(t0); |
1950 | } else { |
1951 | #if defined(TARGET_PPC64) |
1952 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); |
1953 | tcg_gen_rotli_i64(t_ra, t_ra, sh); |
1954 | tcg_gen_andi_i64(t_ra, t_ra, mask); |
1955 | #else |
1956 | g_assert_not_reached(); |
1957 | #endif |
1958 | } |
1959 | } |
1960 | if (unlikely(Rc(ctx->opcode) != 0)) { |
1961 | gen_set_Rc0(ctx, t_ra); |
1962 | } |
1963 | } |
1964 | |
1965 | /* rlwnm & rlwnm. */ |
1966 | static void gen_rlwnm(DisasContext *ctx) |
1967 | { |
1968 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
1969 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; |
1970 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; |
1971 | uint32_t mb = MB(ctx->opcode); |
1972 | uint32_t me = ME(ctx->opcode); |
1973 | target_ulong mask; |
1974 | |
1975 | #if defined(TARGET_PPC64) |
1976 | mb += 32; |
1977 | me += 32; |
1978 | #endif |
1979 | mask = MASK(mb, me); |
1980 | |
1981 | if (mask <= 0xffffffffu) { |
1982 | TCGv_i32 t0 = tcg_temp_new_i32(); |
1983 | TCGv_i32 t1 = tcg_temp_new_i32(); |
1984 | tcg_gen_trunc_tl_i32(t0, t_rb); |
1985 | tcg_gen_trunc_tl_i32(t1, t_rs); |
1986 | tcg_gen_andi_i32(t0, t0, 0x1f); |
1987 | tcg_gen_rotl_i32(t1, t1, t0); |
1988 | tcg_gen_extu_i32_tl(t_ra, t1); |
1989 | tcg_temp_free_i32(t0); |
1990 | tcg_temp_free_i32(t1); |
1991 | } else { |
1992 | #if defined(TARGET_PPC64) |
1993 | TCGv_i64 t0 = tcg_temp_new_i64(); |
1994 | tcg_gen_andi_i64(t0, t_rb, 0x1f); |
1995 | tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32); |
1996 | tcg_gen_rotl_i64(t_ra, t_ra, t0); |
1997 | tcg_temp_free_i64(t0); |
1998 | #else |
1999 | g_assert_not_reached(); |
2000 | #endif |
2001 | } |
2002 | |
2003 | tcg_gen_andi_tl(t_ra, t_ra, mask); |
2004 | |
2005 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2006 | gen_set_Rc0(ctx, t_ra); |
2007 | } |
2008 | } |
2009 | |
2010 | #if defined(TARGET_PPC64) |
2011 | #define GEN_PPC64_R2(name, opc1, opc2) \ |
2012 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
2013 | { \ |
2014 | gen_##name(ctx, 0); \ |
2015 | } \ |
2016 | \ |
2017 | static void glue(gen_, name##1)(DisasContext *ctx) \ |
2018 | { \ |
2019 | gen_##name(ctx, 1); \ |
2020 | } |
2021 | #define GEN_PPC64_R4(name, opc1, opc2) \ |
2022 | static void glue(gen_, name##0)(DisasContext *ctx) \ |
2023 | { \ |
2024 | gen_##name(ctx, 0, 0); \ |
2025 | } \ |
2026 | \ |
2027 | static void glue(gen_, name##1)(DisasContext *ctx) \ |
2028 | { \ |
2029 | gen_##name(ctx, 0, 1); \ |
2030 | } \ |
2031 | \ |
2032 | static void glue(gen_, name##2)(DisasContext *ctx) \ |
2033 | { \ |
2034 | gen_##name(ctx, 1, 0); \ |
2035 | } \ |
2036 | \ |
2037 | static void glue(gen_, name##3)(DisasContext *ctx) \ |
2038 | { \ |
2039 | gen_##name(ctx, 1, 1); \ |
2040 | } |
2041 | |
2042 | static void gen_rldinm(DisasContext *ctx, int mb, int me, int sh) |
2043 | { |
2044 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2045 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; |
2046 | int len = me - mb + 1; |
2047 | int rsh = (64 - sh) & 63; |
2048 | |
2049 | if (sh != 0 && len > 0 && me == (63 - sh)) { |
2050 | tcg_gen_deposit_z_tl(t_ra, t_rs, sh, len); |
2051 | } else if (me == 63 && rsh + len <= 64) { |
2052 | tcg_gen_extract_tl(t_ra, t_rs, rsh, len); |
2053 | } else { |
2054 | tcg_gen_rotli_tl(t_ra, t_rs, sh); |
2055 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); |
2056 | } |
2057 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2058 | gen_set_Rc0(ctx, t_ra); |
2059 | } |
2060 | } |
2061 | |
2062 | /* rldicl - rldicl. */ |
2063 | static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn) |
2064 | { |
2065 | uint32_t sh, mb; |
2066 | |
2067 | sh = SH(ctx->opcode) | (shn << 5); |
2068 | mb = MB(ctx->opcode) | (mbn << 5); |
2069 | gen_rldinm(ctx, mb, 63, sh); |
2070 | } |
2071 | GEN_PPC64_R4(rldicl, 0x1E, 0x00); |
2072 | |
2073 | /* rldicr - rldicr. */ |
2074 | static inline void gen_rldicr(DisasContext *ctx, int men, int shn) |
2075 | { |
2076 | uint32_t sh, me; |
2077 | |
2078 | sh = SH(ctx->opcode) | (shn << 5); |
2079 | me = MB(ctx->opcode) | (men << 5); |
2080 | gen_rldinm(ctx, 0, me, sh); |
2081 | } |
2082 | GEN_PPC64_R4(rldicr, 0x1E, 0x02); |
2083 | |
2084 | /* rldic - rldic. */ |
2085 | static inline void gen_rldic(DisasContext *ctx, int mbn, int shn) |
2086 | { |
2087 | uint32_t sh, mb; |
2088 | |
2089 | sh = SH(ctx->opcode) | (shn << 5); |
2090 | mb = MB(ctx->opcode) | (mbn << 5); |
2091 | gen_rldinm(ctx, mb, 63 - sh, sh); |
2092 | } |
2093 | GEN_PPC64_R4(rldic, 0x1E, 0x04); |
2094 | |
2095 | static void gen_rldnm(DisasContext *ctx, int mb, int me) |
2096 | { |
2097 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2098 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; |
2099 | TCGv t_rb = cpu_gpr[rB(ctx->opcode)]; |
2100 | TCGv t0; |
2101 | |
2102 | t0 = tcg_temp_new(); |
2103 | tcg_gen_andi_tl(t0, t_rb, 0x3f); |
2104 | tcg_gen_rotl_tl(t_ra, t_rs, t0); |
2105 | tcg_temp_free(t0); |
2106 | |
2107 | tcg_gen_andi_tl(t_ra, t_ra, MASK(mb, me)); |
2108 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2109 | gen_set_Rc0(ctx, t_ra); |
2110 | } |
2111 | } |
2112 | |
2113 | /* rldcl - rldcl. */ |
2114 | static inline void gen_rldcl(DisasContext *ctx, int mbn) |
2115 | { |
2116 | uint32_t mb; |
2117 | |
2118 | mb = MB(ctx->opcode) | (mbn << 5); |
2119 | gen_rldnm(ctx, mb, 63); |
2120 | } |
2121 | GEN_PPC64_R2(rldcl, 0x1E, 0x08); |
2122 | |
2123 | /* rldcr - rldcr. */ |
2124 | static inline void gen_rldcr(DisasContext *ctx, int men) |
2125 | { |
2126 | uint32_t me; |
2127 | |
2128 | me = MB(ctx->opcode) | (men << 5); |
2129 | gen_rldnm(ctx, 0, me); |
2130 | } |
2131 | GEN_PPC64_R2(rldcr, 0x1E, 0x09); |
2132 | |
2133 | /* rldimi - rldimi. */ |
2134 | static void gen_rldimi(DisasContext *ctx, int mbn, int shn) |
2135 | { |
2136 | TCGv t_ra = cpu_gpr[rA(ctx->opcode)]; |
2137 | TCGv t_rs = cpu_gpr[rS(ctx->opcode)]; |
2138 | uint32_t sh = SH(ctx->opcode) | (shn << 5); |
2139 | uint32_t mb = MB(ctx->opcode) | (mbn << 5); |
2140 | uint32_t me = 63 - sh; |
2141 | |
2142 | if (mb <= me) { |
2143 | tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1); |
2144 | } else { |
2145 | target_ulong mask = MASK(mb, me); |
2146 | TCGv t1 = tcg_temp_new(); |
2147 | |
2148 | tcg_gen_rotli_tl(t1, t_rs, sh); |
2149 | tcg_gen_andi_tl(t1, t1, mask); |
2150 | tcg_gen_andi_tl(t_ra, t_ra, ~mask); |
2151 | tcg_gen_or_tl(t_ra, t_ra, t1); |
2152 | tcg_temp_free(t1); |
2153 | } |
2154 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2155 | gen_set_Rc0(ctx, t_ra); |
2156 | } |
2157 | } |
2158 | GEN_PPC64_R4(rldimi, 0x1E, 0x06); |
2159 | #endif |
2160 | |
2161 | /*** Integer shift ***/ |
2162 | |
2163 | /* slw & slw. */ |
2164 | static void gen_slw(DisasContext *ctx) |
2165 | { |
2166 | TCGv t0, t1; |
2167 | |
2168 | t0 = tcg_temp_new(); |
2169 | /* AND rS with a mask that is 0 when rB >= 0x20 */ |
2170 | #if defined(TARGET_PPC64) |
2171 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); |
2172 | tcg_gen_sari_tl(t0, t0, 0x3f); |
2173 | #else |
2174 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); |
2175 | tcg_gen_sari_tl(t0, t0, 0x1f); |
2176 | #endif |
2177 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
2178 | t1 = tcg_temp_new(); |
2179 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2180 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
2181 | tcg_temp_free(t1); |
2182 | tcg_temp_free(t0); |
2183 | tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
2184 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2185 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2186 | } |
2187 | } |
2188 | |
2189 | /* sraw & sraw. */ |
2190 | static void gen_sraw(DisasContext *ctx) |
2191 | { |
2192 | gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env, |
2193 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2194 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2195 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2196 | } |
2197 | } |
2198 | |
2199 | /* srawi & srawi. */ |
2200 | static void gen_srawi(DisasContext *ctx) |
2201 | { |
2202 | int sh = SH(ctx->opcode); |
2203 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2204 | TCGv src = cpu_gpr[rS(ctx->opcode)]; |
2205 | if (sh == 0) { |
2206 | tcg_gen_ext32s_tl(dst, src); |
2207 | tcg_gen_movi_tl(cpu_ca, 0); |
2208 | if (is_isa300(ctx)) { |
2209 | tcg_gen_movi_tl(cpu_ca32, 0); |
2210 | } |
2211 | } else { |
2212 | TCGv t0; |
2213 | tcg_gen_ext32s_tl(dst, src); |
2214 | tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1); |
2215 | t0 = tcg_temp_new(); |
2216 | tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1); |
2217 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); |
2218 | tcg_temp_free(t0); |
2219 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); |
2220 | if (is_isa300(ctx)) { |
2221 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); |
2222 | } |
2223 | tcg_gen_sari_tl(dst, dst, sh); |
2224 | } |
2225 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2226 | gen_set_Rc0(ctx, dst); |
2227 | } |
2228 | } |
2229 | |
2230 | /* srw & srw. */ |
2231 | static void gen_srw(DisasContext *ctx) |
2232 | { |
2233 | TCGv t0, t1; |
2234 | |
2235 | t0 = tcg_temp_new(); |
2236 | /* AND rS with a mask that is 0 when rB >= 0x20 */ |
2237 | #if defined(TARGET_PPC64) |
2238 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a); |
2239 | tcg_gen_sari_tl(t0, t0, 0x3f); |
2240 | #else |
2241 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a); |
2242 | tcg_gen_sari_tl(t0, t0, 0x1f); |
2243 | #endif |
2244 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
2245 | tcg_gen_ext32u_tl(t0, t0); |
2246 | t1 = tcg_temp_new(); |
2247 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f); |
2248 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
2249 | tcg_temp_free(t1); |
2250 | tcg_temp_free(t0); |
2251 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2252 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2253 | } |
2254 | } |
2255 | |
2256 | #if defined(TARGET_PPC64) |
2257 | /* sld & sld. */ |
2258 | static void gen_sld(DisasContext *ctx) |
2259 | { |
2260 | TCGv t0, t1; |
2261 | |
2262 | t0 = tcg_temp_new(); |
2263 | /* AND rS with a mask that is 0 when rB >= 0x40 */ |
2264 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); |
2265 | tcg_gen_sari_tl(t0, t0, 0x3f); |
2266 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
2267 | t1 = tcg_temp_new(); |
2268 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); |
2269 | tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
2270 | tcg_temp_free(t1); |
2271 | tcg_temp_free(t0); |
2272 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2273 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2274 | } |
2275 | } |
2276 | |
2277 | /* srad & srad. */ |
2278 | static void gen_srad(DisasContext *ctx) |
2279 | { |
2280 | gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env, |
2281 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2282 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2283 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2284 | } |
2285 | } |
2286 | /* sradi & sradi. */ |
2287 | static inline void gen_sradi(DisasContext *ctx, int n) |
2288 | { |
2289 | int sh = SH(ctx->opcode) + (n << 5); |
2290 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2291 | TCGv src = cpu_gpr[rS(ctx->opcode)]; |
2292 | if (sh == 0) { |
2293 | tcg_gen_mov_tl(dst, src); |
2294 | tcg_gen_movi_tl(cpu_ca, 0); |
2295 | if (is_isa300(ctx)) { |
2296 | tcg_gen_movi_tl(cpu_ca32, 0); |
2297 | } |
2298 | } else { |
2299 | TCGv t0; |
2300 | tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1); |
2301 | t0 = tcg_temp_new(); |
2302 | tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1); |
2303 | tcg_gen_and_tl(cpu_ca, cpu_ca, t0); |
2304 | tcg_temp_free(t0); |
2305 | tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0); |
2306 | if (is_isa300(ctx)) { |
2307 | tcg_gen_mov_tl(cpu_ca32, cpu_ca); |
2308 | } |
2309 | tcg_gen_sari_tl(dst, src, sh); |
2310 | } |
2311 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2312 | gen_set_Rc0(ctx, dst); |
2313 | } |
2314 | } |
2315 | |
2316 | static void gen_sradi0(DisasContext *ctx) |
2317 | { |
2318 | gen_sradi(ctx, 0); |
2319 | } |
2320 | |
2321 | static void gen_sradi1(DisasContext *ctx) |
2322 | { |
2323 | gen_sradi(ctx, 1); |
2324 | } |
2325 | |
2326 | /* extswsli & extswsli. */ |
2327 | static inline void gen_extswsli(DisasContext *ctx, int n) |
2328 | { |
2329 | int sh = SH(ctx->opcode) + (n << 5); |
2330 | TCGv dst = cpu_gpr[rA(ctx->opcode)]; |
2331 | TCGv src = cpu_gpr[rS(ctx->opcode)]; |
2332 | |
2333 | tcg_gen_ext32s_tl(dst, src); |
2334 | tcg_gen_shli_tl(dst, dst, sh); |
2335 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2336 | gen_set_Rc0(ctx, dst); |
2337 | } |
2338 | } |
2339 | |
2340 | static void gen_extswsli0(DisasContext *ctx) |
2341 | { |
2342 | gen_extswsli(ctx, 0); |
2343 | } |
2344 | |
2345 | static void gen_extswsli1(DisasContext *ctx) |
2346 | { |
2347 | gen_extswsli(ctx, 1); |
2348 | } |
2349 | |
2350 | /* srd & srd. */ |
2351 | static void gen_srd(DisasContext *ctx) |
2352 | { |
2353 | TCGv t0, t1; |
2354 | |
2355 | t0 = tcg_temp_new(); |
2356 | /* AND rS with a mask that is 0 when rB >= 0x40 */ |
2357 | tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39); |
2358 | tcg_gen_sari_tl(t0, t0, 0x3f); |
2359 | tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
2360 | t1 = tcg_temp_new(); |
2361 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f); |
2362 | tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
2363 | tcg_temp_free(t1); |
2364 | tcg_temp_free(t0); |
2365 | if (unlikely(Rc(ctx->opcode) != 0)) { |
2366 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
2367 | } |
2368 | } |
2369 | #endif |
2370 | |
2371 | /*** Addressing modes ***/ |
2372 | /* Register indirect with immediate index : EA = (rA|0) + SIMM */ |
2373 | static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA, |
2374 | target_long maskl) |
2375 | { |
2376 | target_long simm = SIMM(ctx->opcode); |
2377 | |
2378 | simm &= ~maskl; |
2379 | if (rA(ctx->opcode) == 0) { |
2380 | if (NARROW_MODE(ctx)) { |
2381 | simm = (uint32_t)simm; |
2382 | } |
2383 | tcg_gen_movi_tl(EA, simm); |
2384 | } else if (likely(simm != 0)) { |
2385 | tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm); |
2386 | if (NARROW_MODE(ctx)) { |
2387 | tcg_gen_ext32u_tl(EA, EA); |
2388 | } |
2389 | } else { |
2390 | if (NARROW_MODE(ctx)) { |
2391 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2392 | } else { |
2393 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2394 | } |
2395 | } |
2396 | } |
2397 | |
2398 | static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA) |
2399 | { |
2400 | if (rA(ctx->opcode) == 0) { |
2401 | if (NARROW_MODE(ctx)) { |
2402 | tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2403 | } else { |
2404 | tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]); |
2405 | } |
2406 | } else { |
2407 | tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
2408 | if (NARROW_MODE(ctx)) { |
2409 | tcg_gen_ext32u_tl(EA, EA); |
2410 | } |
2411 | } |
2412 | } |
2413 | |
2414 | static inline void gen_addr_register(DisasContext *ctx, TCGv EA) |
2415 | { |
2416 | if (rA(ctx->opcode) == 0) { |
2417 | tcg_gen_movi_tl(EA, 0); |
2418 | } else if (NARROW_MODE(ctx)) { |
2419 | tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2420 | } else { |
2421 | tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]); |
2422 | } |
2423 | } |
2424 | |
2425 | static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1, |
2426 | target_long val) |
2427 | { |
2428 | tcg_gen_addi_tl(ret, arg1, val); |
2429 | if (NARROW_MODE(ctx)) { |
2430 | tcg_gen_ext32u_tl(ret, ret); |
2431 | } |
2432 | } |
2433 | |
2434 | static inline void gen_align_no_le(DisasContext *ctx) |
2435 | { |
2436 | gen_exception_err(ctx, POWERPC_EXCP_ALIGN, |
2437 | (ctx->opcode & 0x03FF0000) | POWERPC_EXCP_ALIGN_LE); |
2438 | } |
2439 | |
2440 | /*** Integer load ***/ |
2441 | #define DEF_MEMOP(op) ((op) | ctx->default_tcg_memop_mask) |
2442 | #define BSWAP_MEMOP(op) ((op) | (ctx->default_tcg_memop_mask ^ MO_BSWAP)) |
2443 | |
2444 | #define GEN_QEMU_LOAD_TL(ldop, op) \ |
2445 | static void glue(gen_qemu_, ldop)(DisasContext *ctx, \ |
2446 | TCGv val, \ |
2447 | TCGv addr) \ |
2448 | { \ |
2449 | tcg_gen_qemu_ld_tl(val, addr, ctx->mem_idx, op); \ |
2450 | } |
2451 | |
2452 | GEN_QEMU_LOAD_TL(ld8u, DEF_MEMOP(MO_UB)) |
2453 | GEN_QEMU_LOAD_TL(ld16u, DEF_MEMOP(MO_UW)) |
2454 | GEN_QEMU_LOAD_TL(ld16s, DEF_MEMOP(MO_SW)) |
2455 | GEN_QEMU_LOAD_TL(ld32u, DEF_MEMOP(MO_UL)) |
2456 | GEN_QEMU_LOAD_TL(ld32s, DEF_MEMOP(MO_SL)) |
2457 | |
2458 | GEN_QEMU_LOAD_TL(ld16ur, BSWAP_MEMOP(MO_UW)) |
2459 | GEN_QEMU_LOAD_TL(ld32ur, BSWAP_MEMOP(MO_UL)) |
2460 | |
2461 | #define GEN_QEMU_LOAD_64(ldop, op) \ |
2462 | static void glue(gen_qemu_, glue(ldop, _i64))(DisasContext *ctx, \ |
2463 | TCGv_i64 val, \ |
2464 | TCGv addr) \ |
2465 | { \ |
2466 | tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, op); \ |
2467 | } |
2468 | |
2469 | GEN_QEMU_LOAD_64(ld8u, DEF_MEMOP(MO_UB)) |
2470 | GEN_QEMU_LOAD_64(ld16u, DEF_MEMOP(MO_UW)) |
2471 | GEN_QEMU_LOAD_64(ld32u, DEF_MEMOP(MO_UL)) |
2472 | GEN_QEMU_LOAD_64(ld32s, DEF_MEMOP(MO_SL)) |
2473 | GEN_QEMU_LOAD_64(ld64, DEF_MEMOP(MO_Q)) |
2474 | |
2475 | #if defined(TARGET_PPC64) |
2476 | GEN_QEMU_LOAD_64(ld64ur, BSWAP_MEMOP(MO_Q)) |
2477 | #endif |
2478 | |
2479 | #define GEN_QEMU_STORE_TL(stop, op) \ |
2480 | static void glue(gen_qemu_, stop)(DisasContext *ctx, \ |
2481 | TCGv val, \ |
2482 | TCGv addr) \ |
2483 | { \ |
2484 | tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, op); \ |
2485 | } |
2486 | |
2487 | GEN_QEMU_STORE_TL(st8, DEF_MEMOP(MO_UB)) |
2488 | GEN_QEMU_STORE_TL(st16, DEF_MEMOP(MO_UW)) |
2489 | GEN_QEMU_STORE_TL(st32, DEF_MEMOP(MO_UL)) |
2490 | |
2491 | GEN_QEMU_STORE_TL(st16r, BSWAP_MEMOP(MO_UW)) |
2492 | GEN_QEMU_STORE_TL(st32r, BSWAP_MEMOP(MO_UL)) |
2493 | |
2494 | #define GEN_QEMU_STORE_64(stop, op) \ |
2495 | static void glue(gen_qemu_, glue(stop, _i64))(DisasContext *ctx, \ |
2496 | TCGv_i64 val, \ |
2497 | TCGv addr) \ |
2498 | { \ |
2499 | tcg_gen_qemu_st_i64(val, addr, ctx->mem_idx, op); \ |
2500 | } |
2501 | |
2502 | GEN_QEMU_STORE_64(st8, DEF_MEMOP(MO_UB)) |
2503 | GEN_QEMU_STORE_64(st16, DEF_MEMOP(MO_UW)) |
2504 | GEN_QEMU_STORE_64(st32, DEF_MEMOP(MO_UL)) |
2505 | GEN_QEMU_STORE_64(st64, DEF_MEMOP(MO_Q)) |
2506 | |
2507 | #if defined(TARGET_PPC64) |
2508 | GEN_QEMU_STORE_64(st64r, BSWAP_MEMOP(MO_Q)) |
2509 | #endif |
2510 | |
2511 | #define GEN_LD(name, ldop, opc, type) \ |
2512 | static void glue(gen_, name)(DisasContext *ctx) \ |
2513 | { \ |
2514 | TCGv EA; \ |
2515 | gen_set_access_type(ctx, ACCESS_INT); \ |
2516 | EA = tcg_temp_new(); \ |
2517 | gen_addr_imm_index(ctx, EA, 0); \ |
2518 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2519 | tcg_temp_free(EA); \ |
2520 | } |
2521 | |
2522 | #define GEN_LDU(name, ldop, opc, type) \ |
2523 | static void glue(gen_, name##u)(DisasContext *ctx) \ |
2524 | { \ |
2525 | TCGv EA; \ |
2526 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2527 | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2528 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2529 | return; \ |
2530 | } \ |
2531 | gen_set_access_type(ctx, ACCESS_INT); \ |
2532 | EA = tcg_temp_new(); \ |
2533 | if (type == PPC_64B) \ |
2534 | gen_addr_imm_index(ctx, EA, 0x03); \ |
2535 | else \ |
2536 | gen_addr_imm_index(ctx, EA, 0); \ |
2537 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2538 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2539 | tcg_temp_free(EA); \ |
2540 | } |
2541 | |
2542 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
2543 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2544 | { \ |
2545 | TCGv EA; \ |
2546 | if (unlikely(rA(ctx->opcode) == 0 || \ |
2547 | rA(ctx->opcode) == rD(ctx->opcode))) { \ |
2548 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2549 | return; \ |
2550 | } \ |
2551 | gen_set_access_type(ctx, ACCESS_INT); \ |
2552 | EA = tcg_temp_new(); \ |
2553 | gen_addr_reg_index(ctx, EA); \ |
2554 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2555 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2556 | tcg_temp_free(EA); \ |
2557 | } |
2558 | |
2559 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
2560 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2561 | { \ |
2562 | TCGv EA; \ |
2563 | chk; \ |
2564 | gen_set_access_type(ctx, ACCESS_INT); \ |
2565 | EA = tcg_temp_new(); \ |
2566 | gen_addr_reg_index(ctx, EA); \ |
2567 | gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \ |
2568 | tcg_temp_free(EA); \ |
2569 | } |
2570 | |
2571 | #define GEN_LDX(name, ldop, opc2, opc3, type) \ |
2572 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2573 | |
2574 | #define GEN_LDX_HVRM(name, ldop, opc2, opc3, type) \ |
2575 | GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE, CHK_HVRM) |
2576 | |
2577 | #define GEN_LDS(name, ldop, op, type) \ |
2578 | GEN_LD(name, ldop, op | 0x20, type); \ |
2579 | GEN_LDU(name, ldop, op | 0x21, type); \ |
2580 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \ |
2581 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
2582 | |
2583 | /* lbz lbzu lbzux lbzx */ |
2584 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER); |
2585 | /* lha lhau lhaux lhax */ |
2586 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER); |
2587 | /* lhz lhzu lhzux lhzx */ |
2588 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER); |
2589 | /* lwz lwzu lwzux lwzx */ |
2590 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER); |
2591 | |
2592 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ |
2593 | static void glue(gen_, name##epx)(DisasContext *ctx) \ |
2594 | { \ |
2595 | TCGv EA; \ |
2596 | CHK_SV; \ |
2597 | gen_set_access_type(ctx, ACCESS_INT); \ |
2598 | EA = tcg_temp_new(); \ |
2599 | gen_addr_reg_index(ctx, EA); \ |
2600 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_LOAD, ldop);\ |
2601 | tcg_temp_free(EA); \ |
2602 | } |
2603 | |
2604 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) |
2605 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) |
2606 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) |
2607 | #if defined(TARGET_PPC64) |
2608 | GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) |
2609 | #endif |
2610 | |
2611 | #if defined(TARGET_PPC64) |
2612 | /* lwaux */ |
2613 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B); |
2614 | /* lwax */ |
2615 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B); |
2616 | /* ldux */ |
2617 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B); |
2618 | /* ldx */ |
2619 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B); |
2620 | |
2621 | /* CI load/store variants */ |
2622 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
2623 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x15, PPC_CILDST) |
2624 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) |
2625 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) |
2626 | |
2627 | static void gen_ld(DisasContext *ctx) |
2628 | { |
2629 | TCGv EA; |
2630 | if (Rc(ctx->opcode)) { |
2631 | if (unlikely(rA(ctx->opcode) == 0 || |
2632 | rA(ctx->opcode) == rD(ctx->opcode))) { |
2633 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2634 | return; |
2635 | } |
2636 | } |
2637 | gen_set_access_type(ctx, ACCESS_INT); |
2638 | EA = tcg_temp_new(); |
2639 | gen_addr_imm_index(ctx, EA, 0x03); |
2640 | if (ctx->opcode & 0x02) { |
2641 | /* lwa (lwau is undefined) */ |
2642 | gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2643 | } else { |
2644 | /* ld - ldu */ |
2645 | gen_qemu_ld64_i64(ctx, cpu_gpr[rD(ctx->opcode)], EA); |
2646 | } |
2647 | if (Rc(ctx->opcode)) { |
2648 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2649 | } |
2650 | tcg_temp_free(EA); |
2651 | } |
2652 | |
2653 | /* lq */ |
2654 | static void gen_lq(DisasContext *ctx) |
2655 | { |
2656 | int ra, rd; |
2657 | TCGv EA, hi, lo; |
2658 | |
2659 | /* lq is a legal user mode instruction starting in ISA 2.07 */ |
2660 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2661 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2662 | |
2663 | if (!legal_in_user_mode && ctx->pr) { |
2664 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2665 | return; |
2666 | } |
2667 | |
2668 | if (!le_is_supported && ctx->le_mode) { |
2669 | gen_align_no_le(ctx); |
2670 | return; |
2671 | } |
2672 | ra = rA(ctx->opcode); |
2673 | rd = rD(ctx->opcode); |
2674 | if (unlikely((rd & 1) || rd == ra)) { |
2675 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2676 | return; |
2677 | } |
2678 | |
2679 | gen_set_access_type(ctx, ACCESS_INT); |
2680 | EA = tcg_temp_new(); |
2681 | gen_addr_imm_index(ctx, EA, 0x0F); |
2682 | |
2683 | /* Note that the low part is always in RD+1, even in LE mode. */ |
2684 | lo = cpu_gpr[rd + 1]; |
2685 | hi = cpu_gpr[rd]; |
2686 | |
2687 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
2688 | if (HAVE_ATOMIC128) { |
2689 | TCGv_i32 oi = tcg_temp_new_i32(); |
2690 | if (ctx->le_mode) { |
2691 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); |
2692 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); |
2693 | } else { |
2694 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); |
2695 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); |
2696 | } |
2697 | tcg_temp_free_i32(oi); |
2698 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); |
2699 | } else { |
2700 | /* Restart with exclusive lock. */ |
2701 | gen_helper_exit_atomic(cpu_env); |
2702 | ctx->base.is_jmp = DISAS_NORETURN; |
2703 | } |
2704 | } else if (ctx->le_mode) { |
2705 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ); |
2706 | gen_addr_add(ctx, EA, EA, 8); |
2707 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
2708 | } else { |
2709 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
2710 | gen_addr_add(ctx, EA, EA, 8); |
2711 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
2712 | } |
2713 | tcg_temp_free(EA); |
2714 | } |
2715 | #endif |
2716 | |
2717 | /*** Integer store ***/ |
2718 | #define GEN_ST(name, stop, opc, type) \ |
2719 | static void glue(gen_, name)(DisasContext *ctx) \ |
2720 | { \ |
2721 | TCGv EA; \ |
2722 | gen_set_access_type(ctx, ACCESS_INT); \ |
2723 | EA = tcg_temp_new(); \ |
2724 | gen_addr_imm_index(ctx, EA, 0); \ |
2725 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2726 | tcg_temp_free(EA); \ |
2727 | } |
2728 | |
2729 | #define GEN_STU(name, stop, opc, type) \ |
2730 | static void glue(gen_, stop##u)(DisasContext *ctx) \ |
2731 | { \ |
2732 | TCGv EA; \ |
2733 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2734 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2735 | return; \ |
2736 | } \ |
2737 | gen_set_access_type(ctx, ACCESS_INT); \ |
2738 | EA = tcg_temp_new(); \ |
2739 | if (type == PPC_64B) \ |
2740 | gen_addr_imm_index(ctx, EA, 0x03); \ |
2741 | else \ |
2742 | gen_addr_imm_index(ctx, EA, 0); \ |
2743 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2744 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2745 | tcg_temp_free(EA); \ |
2746 | } |
2747 | |
2748 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
2749 | static void glue(gen_, name##ux)(DisasContext *ctx) \ |
2750 | { \ |
2751 | TCGv EA; \ |
2752 | if (unlikely(rA(ctx->opcode) == 0)) { \ |
2753 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \ |
2754 | return; \ |
2755 | } \ |
2756 | gen_set_access_type(ctx, ACCESS_INT); \ |
2757 | EA = tcg_temp_new(); \ |
2758 | gen_addr_reg_index(ctx, EA); \ |
2759 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2760 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \ |
2761 | tcg_temp_free(EA); \ |
2762 | } |
2763 | |
2764 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
2765 | static void glue(gen_, name##x)(DisasContext *ctx) \ |
2766 | { \ |
2767 | TCGv EA; \ |
2768 | chk; \ |
2769 | gen_set_access_type(ctx, ACCESS_INT); \ |
2770 | EA = tcg_temp_new(); \ |
2771 | gen_addr_reg_index(ctx, EA); \ |
2772 | gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \ |
2773 | tcg_temp_free(EA); \ |
2774 | } |
2775 | #define GEN_STX(name, stop, opc2, opc3, type) \ |
2776 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_NONE) |
2777 | |
2778 | #define GEN_STX_HVRM(name, stop, opc2, opc3, type) \ |
2779 | GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE, CHK_HVRM) |
2780 | |
2781 | #define GEN_STS(name, stop, op, type) \ |
2782 | GEN_ST(name, stop, op | 0x20, type); \ |
2783 | GEN_STU(name, stop, op | 0x21, type); \ |
2784 | GEN_STUX(name, stop, 0x17, op | 0x01, type); \ |
2785 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
2786 | |
2787 | /* stb stbu stbux stbx */ |
2788 | GEN_STS(stb, st8, 0x06, PPC_INTEGER); |
2789 | /* sth sthu sthux sthx */ |
2790 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER); |
2791 | /* stw stwu stwux stwx */ |
2792 | GEN_STS(stw, st32, 0x04, PPC_INTEGER); |
2793 | |
2794 | #define GEN_STEPX(name, stop, opc2, opc3) \ |
2795 | static void glue(gen_, name##epx)(DisasContext *ctx) \ |
2796 | { \ |
2797 | TCGv EA; \ |
2798 | CHK_SV; \ |
2799 | gen_set_access_type(ctx, ACCESS_INT); \ |
2800 | EA = tcg_temp_new(); \ |
2801 | gen_addr_reg_index(ctx, EA); \ |
2802 | tcg_gen_qemu_st_tl( \ |
2803 | cpu_gpr[rD(ctx->opcode)], EA, PPC_TLB_EPID_STORE, stop); \ |
2804 | tcg_temp_free(EA); \ |
2805 | } |
2806 | |
2807 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) |
2808 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) |
2809 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) |
2810 | #if defined(TARGET_PPC64) |
2811 | GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1d, 0x04) |
2812 | #endif |
2813 | |
2814 | #if defined(TARGET_PPC64) |
2815 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B); |
2816 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B); |
2817 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
2818 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
2819 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) |
2820 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) |
2821 | |
2822 | static void gen_std(DisasContext *ctx) |
2823 | { |
2824 | int rs; |
2825 | TCGv EA; |
2826 | |
2827 | rs = rS(ctx->opcode); |
2828 | if ((ctx->opcode & 0x3) == 0x2) { /* stq */ |
2829 | bool legal_in_user_mode = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2830 | bool le_is_supported = (ctx->insns_flags2 & PPC2_LSQ_ISA207) != 0; |
2831 | TCGv hi, lo; |
2832 | |
2833 | if (!(ctx->insns_flags & PPC_64BX)) { |
2834 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2835 | } |
2836 | |
2837 | if (!legal_in_user_mode && ctx->pr) { |
2838 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); |
2839 | return; |
2840 | } |
2841 | |
2842 | if (!le_is_supported && ctx->le_mode) { |
2843 | gen_align_no_le(ctx); |
2844 | return; |
2845 | } |
2846 | |
2847 | if (unlikely(rs & 1)) { |
2848 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2849 | return; |
2850 | } |
2851 | gen_set_access_type(ctx, ACCESS_INT); |
2852 | EA = tcg_temp_new(); |
2853 | gen_addr_imm_index(ctx, EA, 0x03); |
2854 | |
2855 | /* Note that the low part is always in RS+1, even in LE mode. */ |
2856 | lo = cpu_gpr[rs + 1]; |
2857 | hi = cpu_gpr[rs]; |
2858 | |
2859 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
2860 | if (HAVE_ATOMIC128) { |
2861 | TCGv_i32 oi = tcg_temp_new_i32(); |
2862 | if (ctx->le_mode) { |
2863 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ, ctx->mem_idx)); |
2864 | gen_helper_stq_le_parallel(cpu_env, EA, lo, hi, oi); |
2865 | } else { |
2866 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ, ctx->mem_idx)); |
2867 | gen_helper_stq_be_parallel(cpu_env, EA, lo, hi, oi); |
2868 | } |
2869 | tcg_temp_free_i32(oi); |
2870 | } else { |
2871 | /* Restart with exclusive lock. */ |
2872 | gen_helper_exit_atomic(cpu_env); |
2873 | ctx->base.is_jmp = DISAS_NORETURN; |
2874 | } |
2875 | } else if (ctx->le_mode) { |
2876 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_LEQ); |
2877 | gen_addr_add(ctx, EA, EA, 8); |
2878 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
2879 | } else { |
2880 | tcg_gen_qemu_st_i64(hi, EA, ctx->mem_idx, MO_BEQ); |
2881 | gen_addr_add(ctx, EA, EA, 8); |
2882 | tcg_gen_qemu_st_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
2883 | } |
2884 | tcg_temp_free(EA); |
2885 | } else { |
2886 | /* std / stdu */ |
2887 | if (Rc(ctx->opcode)) { |
2888 | if (unlikely(rA(ctx->opcode) == 0)) { |
2889 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
2890 | return; |
2891 | } |
2892 | } |
2893 | gen_set_access_type(ctx, ACCESS_INT); |
2894 | EA = tcg_temp_new(); |
2895 | gen_addr_imm_index(ctx, EA, 0x03); |
2896 | gen_qemu_st64_i64(ctx, cpu_gpr[rs], EA); |
2897 | if (Rc(ctx->opcode)) { |
2898 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); |
2899 | } |
2900 | tcg_temp_free(EA); |
2901 | } |
2902 | } |
2903 | #endif |
2904 | /*** Integer load and store with byte reverse ***/ |
2905 | |
2906 | /* lhbrx */ |
2907 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER); |
2908 | |
2909 | /* lwbrx */ |
2910 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER); |
2911 | |
2912 | #if defined(TARGET_PPC64) |
2913 | /* ldbrx */ |
2914 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE); |
2915 | /* stdbrx */ |
2916 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE); |
2917 | #endif /* TARGET_PPC64 */ |
2918 | |
2919 | /* sthbrx */ |
2920 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER); |
2921 | /* stwbrx */ |
2922 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER); |
2923 | |
2924 | /*** Integer load and store multiple ***/ |
2925 | |
2926 | /* lmw */ |
2927 | static void gen_lmw(DisasContext *ctx) |
2928 | { |
2929 | TCGv t0; |
2930 | TCGv_i32 t1; |
2931 | |
2932 | if (ctx->le_mode) { |
2933 | gen_align_no_le(ctx); |
2934 | return; |
2935 | } |
2936 | gen_set_access_type(ctx, ACCESS_INT); |
2937 | t0 = tcg_temp_new(); |
2938 | t1 = tcg_const_i32(rD(ctx->opcode)); |
2939 | gen_addr_imm_index(ctx, t0, 0); |
2940 | gen_helper_lmw(cpu_env, t0, t1); |
2941 | tcg_temp_free(t0); |
2942 | tcg_temp_free_i32(t1); |
2943 | } |
2944 | |
2945 | /* stmw */ |
2946 | static void gen_stmw(DisasContext *ctx) |
2947 | { |
2948 | TCGv t0; |
2949 | TCGv_i32 t1; |
2950 | |
2951 | if (ctx->le_mode) { |
2952 | gen_align_no_le(ctx); |
2953 | return; |
2954 | } |
2955 | gen_set_access_type(ctx, ACCESS_INT); |
2956 | t0 = tcg_temp_new(); |
2957 | t1 = tcg_const_i32(rS(ctx->opcode)); |
2958 | gen_addr_imm_index(ctx, t0, 0); |
2959 | gen_helper_stmw(cpu_env, t0, t1); |
2960 | tcg_temp_free(t0); |
2961 | tcg_temp_free_i32(t1); |
2962 | } |
2963 | |
2964 | /*** Integer load and store strings ***/ |
2965 | |
2966 | /* lswi */ |
2967 | /* |
2968 | * PowerPC32 specification says we must generate an exception if rA is |
2969 | * in the range of registers to be loaded. In an other hand, IBM says |
2970 | * this is valid, but rA won't be loaded. For now, I'll follow the |
2971 | * spec... |
2972 | */ |
2973 | static void gen_lswi(DisasContext *ctx) |
2974 | { |
2975 | TCGv t0; |
2976 | TCGv_i32 t1, t2; |
2977 | int nb = NB(ctx->opcode); |
2978 | int start = rD(ctx->opcode); |
2979 | int ra = rA(ctx->opcode); |
2980 | int nr; |
2981 | |
2982 | if (ctx->le_mode) { |
2983 | gen_align_no_le(ctx); |
2984 | return; |
2985 | } |
2986 | if (nb == 0) { |
2987 | nb = 32; |
2988 | } |
2989 | nr = DIV_ROUND_UP(nb, 4); |
2990 | if (unlikely(lsw_reg_in_range(start, nr, ra))) { |
2991 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX); |
2992 | return; |
2993 | } |
2994 | gen_set_access_type(ctx, ACCESS_INT); |
2995 | t0 = tcg_temp_new(); |
2996 | gen_addr_register(ctx, t0); |
2997 | t1 = tcg_const_i32(nb); |
2998 | t2 = tcg_const_i32(start); |
2999 | gen_helper_lsw(cpu_env, t0, t1, t2); |
3000 | tcg_temp_free(t0); |
3001 | tcg_temp_free_i32(t1); |
3002 | tcg_temp_free_i32(t2); |
3003 | } |
3004 | |
3005 | /* lswx */ |
3006 | static void gen_lswx(DisasContext *ctx) |
3007 | { |
3008 | TCGv t0; |
3009 | TCGv_i32 t1, t2, t3; |
3010 | |
3011 | if (ctx->le_mode) { |
3012 | gen_align_no_le(ctx); |
3013 | return; |
3014 | } |
3015 | gen_set_access_type(ctx, ACCESS_INT); |
3016 | t0 = tcg_temp_new(); |
3017 | gen_addr_reg_index(ctx, t0); |
3018 | t1 = tcg_const_i32(rD(ctx->opcode)); |
3019 | t2 = tcg_const_i32(rA(ctx->opcode)); |
3020 | t3 = tcg_const_i32(rB(ctx->opcode)); |
3021 | gen_helper_lswx(cpu_env, t0, t1, t2, t3); |
3022 | tcg_temp_free(t0); |
3023 | tcg_temp_free_i32(t1); |
3024 | tcg_temp_free_i32(t2); |
3025 | tcg_temp_free_i32(t3); |
3026 | } |
3027 | |
3028 | /* stswi */ |
3029 | static void gen_stswi(DisasContext *ctx) |
3030 | { |
3031 | TCGv t0; |
3032 | TCGv_i32 t1, t2; |
3033 | int nb = NB(ctx->opcode); |
3034 | |
3035 | if (ctx->le_mode) { |
3036 | gen_align_no_le(ctx); |
3037 | return; |
3038 | } |
3039 | gen_set_access_type(ctx, ACCESS_INT); |
3040 | t0 = tcg_temp_new(); |
3041 | gen_addr_register(ctx, t0); |
3042 | if (nb == 0) { |
3043 | nb = 32; |
3044 | } |
3045 | t1 = tcg_const_i32(nb); |
3046 | t2 = tcg_const_i32(rS(ctx->opcode)); |
3047 | gen_helper_stsw(cpu_env, t0, t1, t2); |
3048 | tcg_temp_free(t0); |
3049 | tcg_temp_free_i32(t1); |
3050 | tcg_temp_free_i32(t2); |
3051 | } |
3052 | |
3053 | /* stswx */ |
3054 | static void gen_stswx(DisasContext *ctx) |
3055 | { |
3056 | TCGv t0; |
3057 | TCGv_i32 t1, t2; |
3058 | |
3059 | if (ctx->le_mode) { |
3060 | gen_align_no_le(ctx); |
3061 | return; |
3062 | } |
3063 | gen_set_access_type(ctx, ACCESS_INT); |
3064 | t0 = tcg_temp_new(); |
3065 | gen_addr_reg_index(ctx, t0); |
3066 | t1 = tcg_temp_new_i32(); |
3067 | tcg_gen_trunc_tl_i32(t1, cpu_xer); |
3068 | tcg_gen_andi_i32(t1, t1, 0x7F); |
3069 | t2 = tcg_const_i32(rS(ctx->opcode)); |
3070 | gen_helper_stsw(cpu_env, t0, t1, t2); |
3071 | tcg_temp_free(t0); |
3072 | tcg_temp_free_i32(t1); |
3073 | tcg_temp_free_i32(t2); |
3074 | } |
3075 | |
3076 | /*** Memory synchronisation ***/ |
3077 | /* eieio */ |
3078 | static void gen_eieio(DisasContext *ctx) |
3079 | { |
3080 | TCGBar bar = TCG_MO_LD_ST; |
3081 | |
3082 | /* |
3083 | * POWER9 has a eieio instruction variant using bit 6 as a hint to |
3084 | * tell the CPU it is a store-forwarding barrier. |
3085 | */ |
3086 | if (ctx->opcode & 0x2000000) { |
3087 | /* |
3088 | * ISA says that "Reserved fields in instructions are ignored |
3089 | * by the processor". So ignore the bit 6 on non-POWER9 CPU but |
3090 | * as this is not an instruction software should be using, |
3091 | * complain to the user. |
3092 | */ |
3093 | if (!(ctx->insns_flags2 & PPC2_ISA300)) { |
3094 | qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @" |
3095 | TARGET_FMT_lx "\n" , ctx->base.pc_next - 4); |
3096 | } else { |
3097 | bar = TCG_MO_ST_LD; |
3098 | } |
3099 | } |
3100 | |
3101 | tcg_gen_mb(bar | TCG_BAR_SC); |
3102 | } |
3103 | |
3104 | #if !defined(CONFIG_USER_ONLY) |
3105 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) |
3106 | { |
3107 | TCGv_i32 t; |
3108 | TCGLabel *l; |
3109 | |
3110 | if (!ctx->lazy_tlb_flush) { |
3111 | return; |
3112 | } |
3113 | l = gen_new_label(); |
3114 | t = tcg_temp_new_i32(); |
3115 | tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
3116 | tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, l); |
3117 | if (global) { |
3118 | gen_helper_check_tlb_flush_global(cpu_env); |
3119 | } else { |
3120 | gen_helper_check_tlb_flush_local(cpu_env); |
3121 | } |
3122 | gen_set_label(l); |
3123 | tcg_temp_free_i32(t); |
3124 | } |
3125 | #else |
3126 | static inline void gen_check_tlb_flush(DisasContext *ctx, bool global) { } |
3127 | #endif |
3128 | |
3129 | /* isync */ |
3130 | static void gen_isync(DisasContext *ctx) |
3131 | { |
3132 | /* |
3133 | * We need to check for a pending TLB flush. This can only happen in |
3134 | * kernel mode however so check MSR_PR |
3135 | */ |
3136 | if (!ctx->pr) { |
3137 | gen_check_tlb_flush(ctx, false); |
3138 | } |
3139 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
3140 | gen_stop_exception(ctx); |
3141 | } |
3142 | |
3143 | #define MEMOP_GET_SIZE(x) (1 << ((x) & MO_SIZE)) |
3144 | |
3145 | static void gen_load_locked(DisasContext *ctx, MemOp memop) |
3146 | { |
3147 | TCGv gpr = cpu_gpr[rD(ctx->opcode)]; |
3148 | TCGv t0 = tcg_temp_new(); |
3149 | |
3150 | gen_set_access_type(ctx, ACCESS_RES); |
3151 | gen_addr_reg_index(ctx, t0); |
3152 | tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, memop | MO_ALIGN); |
3153 | tcg_gen_mov_tl(cpu_reserve, t0); |
3154 | tcg_gen_mov_tl(cpu_reserve_val, gpr); |
3155 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); |
3156 | tcg_temp_free(t0); |
3157 | } |
3158 | |
3159 | #define LARX(name, memop) \ |
3160 | static void gen_##name(DisasContext *ctx) \ |
3161 | { \ |
3162 | gen_load_locked(ctx, memop); \ |
3163 | } |
3164 | |
3165 | /* lwarx */ |
3166 | LARX(lbarx, DEF_MEMOP(MO_UB)) |
3167 | LARX(lharx, DEF_MEMOP(MO_UW)) |
3168 | LARX(lwarx, DEF_MEMOP(MO_UL)) |
3169 | |
3170 | static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop, |
3171 | TCGv EA, TCGCond cond, int addend) |
3172 | { |
3173 | TCGv t = tcg_temp_new(); |
3174 | TCGv t2 = tcg_temp_new(); |
3175 | TCGv u = tcg_temp_new(); |
3176 | |
3177 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); |
3178 | tcg_gen_addi_tl(t2, EA, MEMOP_GET_SIZE(memop)); |
3179 | tcg_gen_qemu_ld_tl(t2, t2, ctx->mem_idx, memop); |
3180 | tcg_gen_addi_tl(u, t, addend); |
3181 | |
3182 | /* E.g. for fetch and increment bounded... */ |
3183 | /* mem(EA,s) = (t != t2 ? u = t + 1 : t) */ |
3184 | tcg_gen_movcond_tl(cond, u, t, t2, u, t); |
3185 | tcg_gen_qemu_st_tl(u, EA, ctx->mem_idx, memop); |
3186 | |
3187 | /* RT = (t != t2 ? t : u = 1<<(s*8-1)) */ |
3188 | tcg_gen_movi_tl(u, 1 << (MEMOP_GET_SIZE(memop) * 8 - 1)); |
3189 | tcg_gen_movcond_tl(cond, cpu_gpr[rD(ctx->opcode)], t, t2, t, u); |
3190 | |
3191 | tcg_temp_free(t); |
3192 | tcg_temp_free(t2); |
3193 | tcg_temp_free(u); |
3194 | } |
3195 | |
3196 | static void gen_ld_atomic(DisasContext *ctx, MemOp memop) |
3197 | { |
3198 | uint32_t gpr_FC = FC(ctx->opcode); |
3199 | TCGv EA = tcg_temp_new(); |
3200 | int rt = rD(ctx->opcode); |
3201 | bool need_serial; |
3202 | TCGv src, dst; |
3203 | |
3204 | gen_addr_register(ctx, EA); |
3205 | dst = cpu_gpr[rt]; |
3206 | src = cpu_gpr[(rt + 1) & 31]; |
3207 | |
3208 | need_serial = false; |
3209 | memop |= MO_ALIGN; |
3210 | switch (gpr_FC) { |
3211 | case 0: /* Fetch and add */ |
3212 | tcg_gen_atomic_fetch_add_tl(dst, EA, src, ctx->mem_idx, memop); |
3213 | break; |
3214 | case 1: /* Fetch and xor */ |
3215 | tcg_gen_atomic_fetch_xor_tl(dst, EA, src, ctx->mem_idx, memop); |
3216 | break; |
3217 | case 2: /* Fetch and or */ |
3218 | tcg_gen_atomic_fetch_or_tl(dst, EA, src, ctx->mem_idx, memop); |
3219 | break; |
3220 | case 3: /* Fetch and 'and' */ |
3221 | tcg_gen_atomic_fetch_and_tl(dst, EA, src, ctx->mem_idx, memop); |
3222 | break; |
3223 | case 4: /* Fetch and max unsigned */ |
3224 | tcg_gen_atomic_fetch_umax_tl(dst, EA, src, ctx->mem_idx, memop); |
3225 | break; |
3226 | case 5: /* Fetch and max signed */ |
3227 | tcg_gen_atomic_fetch_smax_tl(dst, EA, src, ctx->mem_idx, memop); |
3228 | break; |
3229 | case 6: /* Fetch and min unsigned */ |
3230 | tcg_gen_atomic_fetch_umin_tl(dst, EA, src, ctx->mem_idx, memop); |
3231 | break; |
3232 | case 7: /* Fetch and min signed */ |
3233 | tcg_gen_atomic_fetch_smin_tl(dst, EA, src, ctx->mem_idx, memop); |
3234 | break; |
3235 | case 8: /* Swap */ |
3236 | tcg_gen_atomic_xchg_tl(dst, EA, src, ctx->mem_idx, memop); |
3237 | break; |
3238 | |
3239 | case 16: /* Compare and swap not equal */ |
3240 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3241 | need_serial = true; |
3242 | } else { |
3243 | TCGv t0 = tcg_temp_new(); |
3244 | TCGv t1 = tcg_temp_new(); |
3245 | |
3246 | tcg_gen_qemu_ld_tl(t0, EA, ctx->mem_idx, memop); |
3247 | if ((memop & MO_SIZE) == MO_64 || TARGET_LONG_BITS == 32) { |
3248 | tcg_gen_mov_tl(t1, src); |
3249 | } else { |
3250 | tcg_gen_ext32u_tl(t1, src); |
3251 | } |
3252 | tcg_gen_movcond_tl(TCG_COND_NE, t1, t0, t1, |
3253 | cpu_gpr[(rt + 2) & 31], t0); |
3254 | tcg_gen_qemu_st_tl(t1, EA, ctx->mem_idx, memop); |
3255 | tcg_gen_mov_tl(dst, t0); |
3256 | |
3257 | tcg_temp_free(t0); |
3258 | tcg_temp_free(t1); |
3259 | } |
3260 | break; |
3261 | |
3262 | case 24: /* Fetch and increment bounded */ |
3263 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3264 | need_serial = true; |
3265 | } else { |
3266 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, 1); |
3267 | } |
3268 | break; |
3269 | case 25: /* Fetch and increment equal */ |
3270 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3271 | need_serial = true; |
3272 | } else { |
3273 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_EQ, 1); |
3274 | } |
3275 | break; |
3276 | case 28: /* Fetch and decrement bounded */ |
3277 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3278 | need_serial = true; |
3279 | } else { |
3280 | gen_fetch_inc_conditional(ctx, memop, EA, TCG_COND_NE, -1); |
3281 | } |
3282 | break; |
3283 | |
3284 | default: |
3285 | /* invoke data storage error handler */ |
3286 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); |
3287 | } |
3288 | tcg_temp_free(EA); |
3289 | |
3290 | if (need_serial) { |
3291 | /* Restart with exclusive lock. */ |
3292 | gen_helper_exit_atomic(cpu_env); |
3293 | ctx->base.is_jmp = DISAS_NORETURN; |
3294 | } |
3295 | } |
3296 | |
3297 | static void gen_lwat(DisasContext *ctx) |
3298 | { |
3299 | gen_ld_atomic(ctx, DEF_MEMOP(MO_UL)); |
3300 | } |
3301 | |
3302 | #ifdef TARGET_PPC64 |
3303 | static void gen_ldat(DisasContext *ctx) |
3304 | { |
3305 | gen_ld_atomic(ctx, DEF_MEMOP(MO_Q)); |
3306 | } |
3307 | #endif |
3308 | |
3309 | static void gen_st_atomic(DisasContext *ctx, MemOp memop) |
3310 | { |
3311 | uint32_t gpr_FC = FC(ctx->opcode); |
3312 | TCGv EA = tcg_temp_new(); |
3313 | TCGv src, discard; |
3314 | |
3315 | gen_addr_register(ctx, EA); |
3316 | src = cpu_gpr[rD(ctx->opcode)]; |
3317 | discard = tcg_temp_new(); |
3318 | |
3319 | memop |= MO_ALIGN; |
3320 | switch (gpr_FC) { |
3321 | case 0: /* add and Store */ |
3322 | tcg_gen_atomic_add_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3323 | break; |
3324 | case 1: /* xor and Store */ |
3325 | tcg_gen_atomic_xor_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3326 | break; |
3327 | case 2: /* Or and Store */ |
3328 | tcg_gen_atomic_or_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3329 | break; |
3330 | case 3: /* 'and' and Store */ |
3331 | tcg_gen_atomic_and_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3332 | break; |
3333 | case 4: /* Store max unsigned */ |
3334 | tcg_gen_atomic_umax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3335 | break; |
3336 | case 5: /* Store max signed */ |
3337 | tcg_gen_atomic_smax_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3338 | break; |
3339 | case 6: /* Store min unsigned */ |
3340 | tcg_gen_atomic_umin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3341 | break; |
3342 | case 7: /* Store min signed */ |
3343 | tcg_gen_atomic_smin_fetch_tl(discard, EA, src, ctx->mem_idx, memop); |
3344 | break; |
3345 | case 24: /* Store twin */ |
3346 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3347 | /* Restart with exclusive lock. */ |
3348 | gen_helper_exit_atomic(cpu_env); |
3349 | ctx->base.is_jmp = DISAS_NORETURN; |
3350 | } else { |
3351 | TCGv t = tcg_temp_new(); |
3352 | TCGv t2 = tcg_temp_new(); |
3353 | TCGv s = tcg_temp_new(); |
3354 | TCGv s2 = tcg_temp_new(); |
3355 | TCGv ea_plus_s = tcg_temp_new(); |
3356 | |
3357 | tcg_gen_qemu_ld_tl(t, EA, ctx->mem_idx, memop); |
3358 | tcg_gen_addi_tl(ea_plus_s, EA, MEMOP_GET_SIZE(memop)); |
3359 | tcg_gen_qemu_ld_tl(t2, ea_plus_s, ctx->mem_idx, memop); |
3360 | tcg_gen_movcond_tl(TCG_COND_EQ, s, t, t2, src, t); |
3361 | tcg_gen_movcond_tl(TCG_COND_EQ, s2, t, t2, src, t2); |
3362 | tcg_gen_qemu_st_tl(s, EA, ctx->mem_idx, memop); |
3363 | tcg_gen_qemu_st_tl(s2, ea_plus_s, ctx->mem_idx, memop); |
3364 | |
3365 | tcg_temp_free(ea_plus_s); |
3366 | tcg_temp_free(s2); |
3367 | tcg_temp_free(s); |
3368 | tcg_temp_free(t2); |
3369 | tcg_temp_free(t); |
3370 | } |
3371 | break; |
3372 | default: |
3373 | /* invoke data storage error handler */ |
3374 | gen_exception_err(ctx, POWERPC_EXCP_DSI, POWERPC_EXCP_INVAL); |
3375 | } |
3376 | tcg_temp_free(discard); |
3377 | tcg_temp_free(EA); |
3378 | } |
3379 | |
3380 | static void gen_stwat(DisasContext *ctx) |
3381 | { |
3382 | gen_st_atomic(ctx, DEF_MEMOP(MO_UL)); |
3383 | } |
3384 | |
3385 | #ifdef TARGET_PPC64 |
3386 | static void gen_stdat(DisasContext *ctx) |
3387 | { |
3388 | gen_st_atomic(ctx, DEF_MEMOP(MO_Q)); |
3389 | } |
3390 | #endif |
3391 | |
3392 | static void gen_conditional_store(DisasContext *ctx, MemOp memop) |
3393 | { |
3394 | TCGLabel *l1 = gen_new_label(); |
3395 | TCGLabel *l2 = gen_new_label(); |
3396 | TCGv t0 = tcg_temp_new(); |
3397 | int reg = rS(ctx->opcode); |
3398 | |
3399 | gen_set_access_type(ctx, ACCESS_RES); |
3400 | gen_addr_reg_index(ctx, t0); |
3401 | tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1); |
3402 | tcg_temp_free(t0); |
3403 | |
3404 | t0 = tcg_temp_new(); |
3405 | tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val, |
3406 | cpu_gpr[reg], ctx->mem_idx, |
3407 | DEF_MEMOP(memop) | MO_ALIGN); |
3408 | tcg_gen_setcond_tl(TCG_COND_EQ, t0, t0, cpu_reserve_val); |
3409 | tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); |
3410 | tcg_gen_or_tl(t0, t0, cpu_so); |
3411 | tcg_gen_trunc_tl_i32(cpu_crf[0], t0); |
3412 | tcg_temp_free(t0); |
3413 | tcg_gen_br(l2); |
3414 | |
3415 | gen_set_label(l1); |
3416 | |
3417 | /* |
3418 | * Address mismatch implies failure. But we still need to provide |
3419 | * the memory barrier semantics of the instruction. |
3420 | */ |
3421 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); |
3422 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3423 | |
3424 | gen_set_label(l2); |
3425 | tcg_gen_movi_tl(cpu_reserve, -1); |
3426 | } |
3427 | |
3428 | #define STCX(name, memop) \ |
3429 | static void gen_##name(DisasContext *ctx) \ |
3430 | { \ |
3431 | gen_conditional_store(ctx, memop); \ |
3432 | } |
3433 | |
3434 | STCX(stbcx_, DEF_MEMOP(MO_UB)) |
3435 | STCX(sthcx_, DEF_MEMOP(MO_UW)) |
3436 | STCX(stwcx_, DEF_MEMOP(MO_UL)) |
3437 | |
3438 | #if defined(TARGET_PPC64) |
3439 | /* ldarx */ |
3440 | LARX(ldarx, DEF_MEMOP(MO_Q)) |
3441 | /* stdcx. */ |
3442 | STCX(stdcx_, DEF_MEMOP(MO_Q)) |
3443 | |
3444 | /* lqarx */ |
3445 | static void gen_lqarx(DisasContext *ctx) |
3446 | { |
3447 | int rd = rD(ctx->opcode); |
3448 | TCGv EA, hi, lo; |
3449 | |
3450 | if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) || |
3451 | (rd == rB(ctx->opcode)))) { |
3452 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3453 | return; |
3454 | } |
3455 | |
3456 | gen_set_access_type(ctx, ACCESS_RES); |
3457 | EA = tcg_temp_new(); |
3458 | gen_addr_reg_index(ctx, EA); |
3459 | |
3460 | /* Note that the low part is always in RD+1, even in LE mode. */ |
3461 | lo = cpu_gpr[rd + 1]; |
3462 | hi = cpu_gpr[rd]; |
3463 | |
3464 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3465 | if (HAVE_ATOMIC128) { |
3466 | TCGv_i32 oi = tcg_temp_new_i32(); |
3467 | if (ctx->le_mode) { |
3468 | tcg_gen_movi_i32(oi, make_memop_idx(MO_LEQ | MO_ALIGN_16, |
3469 | ctx->mem_idx)); |
3470 | gen_helper_lq_le_parallel(lo, cpu_env, EA, oi); |
3471 | } else { |
3472 | tcg_gen_movi_i32(oi, make_memop_idx(MO_BEQ | MO_ALIGN_16, |
3473 | ctx->mem_idx)); |
3474 | gen_helper_lq_be_parallel(lo, cpu_env, EA, oi); |
3475 | } |
3476 | tcg_temp_free_i32(oi); |
3477 | tcg_gen_ld_i64(hi, cpu_env, offsetof(CPUPPCState, retxh)); |
3478 | } else { |
3479 | /* Restart with exclusive lock. */ |
3480 | gen_helper_exit_atomic(cpu_env); |
3481 | ctx->base.is_jmp = DISAS_NORETURN; |
3482 | tcg_temp_free(EA); |
3483 | return; |
3484 | } |
3485 | } else if (ctx->le_mode) { |
3486 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_LEQ | MO_ALIGN_16); |
3487 | tcg_gen_mov_tl(cpu_reserve, EA); |
3488 | gen_addr_add(ctx, EA, EA, 8); |
3489 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_LEQ); |
3490 | } else { |
3491 | tcg_gen_qemu_ld_i64(hi, EA, ctx->mem_idx, MO_BEQ | MO_ALIGN_16); |
3492 | tcg_gen_mov_tl(cpu_reserve, EA); |
3493 | gen_addr_add(ctx, EA, EA, 8); |
3494 | tcg_gen_qemu_ld_i64(lo, EA, ctx->mem_idx, MO_BEQ); |
3495 | } |
3496 | tcg_temp_free(EA); |
3497 | |
3498 | tcg_gen_st_tl(hi, cpu_env, offsetof(CPUPPCState, reserve_val)); |
3499 | tcg_gen_st_tl(lo, cpu_env, offsetof(CPUPPCState, reserve_val2)); |
3500 | } |
3501 | |
3502 | /* stqcx. */ |
3503 | static void gen_stqcx_(DisasContext *ctx) |
3504 | { |
3505 | int rs = rS(ctx->opcode); |
3506 | TCGv EA, hi, lo; |
3507 | |
3508 | if (unlikely(rs & 1)) { |
3509 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3510 | return; |
3511 | } |
3512 | |
3513 | gen_set_access_type(ctx, ACCESS_RES); |
3514 | EA = tcg_temp_new(); |
3515 | gen_addr_reg_index(ctx, EA); |
3516 | |
3517 | /* Note that the low part is always in RS+1, even in LE mode. */ |
3518 | lo = cpu_gpr[rs + 1]; |
3519 | hi = cpu_gpr[rs]; |
3520 | |
3521 | if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { |
3522 | if (HAVE_CMPXCHG128) { |
3523 | TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_Q) | MO_ALIGN_16); |
3524 | if (ctx->le_mode) { |
3525 | gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, |
3526 | EA, lo, hi, oi); |
3527 | } else { |
3528 | gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, |
3529 | EA, lo, hi, oi); |
3530 | } |
3531 | tcg_temp_free_i32(oi); |
3532 | } else { |
3533 | /* Restart with exclusive lock. */ |
3534 | gen_helper_exit_atomic(cpu_env); |
3535 | ctx->base.is_jmp = DISAS_NORETURN; |
3536 | } |
3537 | tcg_temp_free(EA); |
3538 | } else { |
3539 | TCGLabel *lab_fail = gen_new_label(); |
3540 | TCGLabel *lab_over = gen_new_label(); |
3541 | TCGv_i64 t0 = tcg_temp_new_i64(); |
3542 | TCGv_i64 t1 = tcg_temp_new_i64(); |
3543 | |
3544 | tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); |
3545 | tcg_temp_free(EA); |
3546 | |
3547 | gen_qemu_ld64_i64(ctx, t0, cpu_reserve); |
3548 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode |
3549 | ? offsetof(CPUPPCState, reserve_val2) |
3550 | : offsetof(CPUPPCState, reserve_val))); |
3551 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); |
3552 | |
3553 | tcg_gen_addi_i64(t0, cpu_reserve, 8); |
3554 | gen_qemu_ld64_i64(ctx, t0, t0); |
3555 | tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode |
3556 | ? offsetof(CPUPPCState, reserve_val) |
3557 | : offsetof(CPUPPCState, reserve_val2))); |
3558 | tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); |
3559 | |
3560 | /* Success */ |
3561 | gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); |
3562 | tcg_gen_addi_i64(t0, cpu_reserve, 8); |
3563 | gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); |
3564 | |
3565 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3566 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
3567 | tcg_gen_br(lab_over); |
3568 | |
3569 | gen_set_label(lab_fail); |
3570 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
3571 | |
3572 | gen_set_label(lab_over); |
3573 | tcg_gen_movi_tl(cpu_reserve, -1); |
3574 | tcg_temp_free_i64(t0); |
3575 | tcg_temp_free_i64(t1); |
3576 | } |
3577 | } |
3578 | #endif /* defined(TARGET_PPC64) */ |
3579 | |
3580 | /* sync */ |
3581 | static void gen_sync(DisasContext *ctx) |
3582 | { |
3583 | uint32_t l = (ctx->opcode >> 21) & 3; |
3584 | |
3585 | /* |
3586 | * We may need to check for a pending TLB flush. |
3587 | * |
3588 | * We do this on ptesync (l == 2) on ppc64 and any sync pn ppc32. |
3589 | * |
3590 | * Additionally, this can only happen in kernel mode however so |
3591 | * check MSR_PR as well. |
3592 | */ |
3593 | if (((l == 2) || !(ctx->insns_flags & PPC_64B)) && !ctx->pr) { |
3594 | gen_check_tlb_flush(ctx, true); |
3595 | } |
3596 | tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); |
3597 | } |
3598 | |
3599 | /* wait */ |
3600 | static void gen_wait(DisasContext *ctx) |
3601 | { |
3602 | TCGv_i32 t0 = tcg_const_i32(1); |
3603 | tcg_gen_st_i32(t0, cpu_env, |
3604 | -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted)); |
3605 | tcg_temp_free_i32(t0); |
3606 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3607 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
3608 | } |
3609 | |
3610 | #if defined(TARGET_PPC64) |
3611 | static void gen_doze(DisasContext *ctx) |
3612 | { |
3613 | #if defined(CONFIG_USER_ONLY) |
3614 | GEN_PRIV; |
3615 | #else |
3616 | TCGv_i32 t; |
3617 | |
3618 | CHK_HV; |
3619 | t = tcg_const_i32(PPC_PM_DOZE); |
3620 | gen_helper_pminsn(cpu_env, t); |
3621 | tcg_temp_free_i32(t); |
3622 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3623 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
3624 | #endif /* defined(CONFIG_USER_ONLY) */ |
3625 | } |
3626 | |
3627 | static void gen_nap(DisasContext *ctx) |
3628 | { |
3629 | #if defined(CONFIG_USER_ONLY) |
3630 | GEN_PRIV; |
3631 | #else |
3632 | TCGv_i32 t; |
3633 | |
3634 | CHK_HV; |
3635 | t = tcg_const_i32(PPC_PM_NAP); |
3636 | gen_helper_pminsn(cpu_env, t); |
3637 | tcg_temp_free_i32(t); |
3638 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3639 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
3640 | #endif /* defined(CONFIG_USER_ONLY) */ |
3641 | } |
3642 | |
3643 | static void gen_stop(DisasContext *ctx) |
3644 | { |
3645 | #if defined(CONFIG_USER_ONLY) |
3646 | GEN_PRIV; |
3647 | #else |
3648 | TCGv_i32 t; |
3649 | |
3650 | CHK_HV; |
3651 | t = tcg_const_i32(PPC_PM_STOP); |
3652 | gen_helper_pminsn(cpu_env, t); |
3653 | tcg_temp_free_i32(t); |
3654 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3655 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
3656 | #endif /* defined(CONFIG_USER_ONLY) */ |
3657 | } |
3658 | |
3659 | static void gen_sleep(DisasContext *ctx) |
3660 | { |
3661 | #if defined(CONFIG_USER_ONLY) |
3662 | GEN_PRIV; |
3663 | #else |
3664 | TCGv_i32 t; |
3665 | |
3666 | CHK_HV; |
3667 | t = tcg_const_i32(PPC_PM_SLEEP); |
3668 | gen_helper_pminsn(cpu_env, t); |
3669 | tcg_temp_free_i32(t); |
3670 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3671 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
3672 | #endif /* defined(CONFIG_USER_ONLY) */ |
3673 | } |
3674 | |
3675 | static void gen_rvwinkle(DisasContext *ctx) |
3676 | { |
3677 | #if defined(CONFIG_USER_ONLY) |
3678 | GEN_PRIV; |
3679 | #else |
3680 | TCGv_i32 t; |
3681 | |
3682 | CHK_HV; |
3683 | t = tcg_const_i32(PPC_PM_RVWINKLE); |
3684 | gen_helper_pminsn(cpu_env, t); |
3685 | tcg_temp_free_i32(t); |
3686 | /* Stop translation, as the CPU is supposed to sleep from now */ |
3687 | gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); |
3688 | #endif /* defined(CONFIG_USER_ONLY) */ |
3689 | } |
3690 | #endif /* #if defined(TARGET_PPC64) */ |
3691 | |
3692 | static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) |
3693 | { |
3694 | #if defined(TARGET_PPC64) |
3695 | if (ctx->has_cfar) { |
3696 | tcg_gen_movi_tl(cpu_cfar, nip); |
3697 | } |
3698 | #endif |
3699 | } |
3700 | |
3701 | static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) |
3702 | { |
3703 | if (unlikely(ctx->singlestep_enabled)) { |
3704 | return false; |
3705 | } |
3706 | |
3707 | #ifndef CONFIG_USER_ONLY |
3708 | return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); |
3709 | #else |
3710 | return true; |
3711 | #endif |
3712 | } |
3713 | |
3714 | static void gen_lookup_and_goto_ptr(DisasContext *ctx) |
3715 | { |
3716 | int sse = ctx->singlestep_enabled; |
3717 | if (unlikely(sse)) { |
3718 | if (sse & GDBSTUB_SINGLE_STEP) { |
3719 | gen_debug_exception(ctx); |
3720 | } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) { |
3721 | uint32_t excp = gen_prep_dbgex(ctx); |
3722 | gen_exception(ctx, excp); |
3723 | } |
3724 | tcg_gen_exit_tb(NULL, 0); |
3725 | } else { |
3726 | tcg_gen_lookup_and_goto_ptr(); |
3727 | } |
3728 | } |
3729 | |
3730 | /*** Branch ***/ |
3731 | static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) |
3732 | { |
3733 | if (NARROW_MODE(ctx)) { |
3734 | dest = (uint32_t) dest; |
3735 | } |
3736 | if (use_goto_tb(ctx, dest)) { |
3737 | tcg_gen_goto_tb(n); |
3738 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
3739 | tcg_gen_exit_tb(ctx->base.tb, n); |
3740 | } else { |
3741 | tcg_gen_movi_tl(cpu_nip, dest & ~3); |
3742 | gen_lookup_and_goto_ptr(ctx); |
3743 | } |
3744 | } |
3745 | |
3746 | static inline void gen_setlr(DisasContext *ctx, target_ulong nip) |
3747 | { |
3748 | if (NARROW_MODE(ctx)) { |
3749 | nip = (uint32_t)nip; |
3750 | } |
3751 | tcg_gen_movi_tl(cpu_lr, nip); |
3752 | } |
3753 | |
3754 | /* b ba bl bla */ |
3755 | static void gen_b(DisasContext *ctx) |
3756 | { |
3757 | target_ulong li, target; |
3758 | |
3759 | ctx->exception = POWERPC_EXCP_BRANCH; |
3760 | /* sign extend LI */ |
3761 | li = LI(ctx->opcode); |
3762 | li = (li ^ 0x02000000) - 0x02000000; |
3763 | if (likely(AA(ctx->opcode) == 0)) { |
3764 | target = ctx->base.pc_next + li - 4; |
3765 | } else { |
3766 | target = li; |
3767 | } |
3768 | if (LK(ctx->opcode)) { |
3769 | gen_setlr(ctx, ctx->base.pc_next); |
3770 | } |
3771 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
3772 | gen_goto_tb(ctx, 0, target); |
3773 | } |
3774 | |
3775 | #define BCOND_IM 0 |
3776 | #define BCOND_LR 1 |
3777 | #define BCOND_CTR 2 |
3778 | #define BCOND_TAR 3 |
3779 | |
3780 | static void gen_bcond(DisasContext *ctx, int type) |
3781 | { |
3782 | uint32_t bo = BO(ctx->opcode); |
3783 | TCGLabel *l1; |
3784 | TCGv target; |
3785 | ctx->exception = POWERPC_EXCP_BRANCH; |
3786 | |
3787 | if (type == BCOND_LR || type == BCOND_CTR || type == BCOND_TAR) { |
3788 | target = tcg_temp_local_new(); |
3789 | if (type == BCOND_CTR) { |
3790 | tcg_gen_mov_tl(target, cpu_ctr); |
3791 | } else if (type == BCOND_TAR) { |
3792 | gen_load_spr(target, SPR_TAR); |
3793 | } else { |
3794 | tcg_gen_mov_tl(target, cpu_lr); |
3795 | } |
3796 | } else { |
3797 | target = NULL; |
3798 | } |
3799 | if (LK(ctx->opcode)) { |
3800 | gen_setlr(ctx, ctx->base.pc_next); |
3801 | } |
3802 | l1 = gen_new_label(); |
3803 | if ((bo & 0x4) == 0) { |
3804 | /* Decrement and test CTR */ |
3805 | TCGv temp = tcg_temp_new(); |
3806 | |
3807 | if (type == BCOND_CTR) { |
3808 | /* |
3809 | * All ISAs up to v3 describe this form of bcctr as invalid but |
3810 | * some processors, ie. 64-bit server processors compliant with |
3811 | * arch 2.x, do implement a "test and decrement" logic instead, |
3812 | * as described in their respective UMs. This logic involves CTR |
3813 | * to act as both the branch target and a counter, which makes |
3814 | * it basically useless and thus never used in real code. |
3815 | * |
3816 | * This form was hence chosen to trigger extra micro-architectural |
3817 | * side-effect on real HW needed for the Spectre v2 workaround. |
3818 | * It is up to guests that implement such workaround, ie. linux, to |
3819 | * use this form in a way it just triggers the side-effect without |
3820 | * doing anything else harmful. |
3821 | */ |
3822 | if (unlikely(!is_book3s_arch2x(ctx))) { |
3823 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3824 | tcg_temp_free(temp); |
3825 | tcg_temp_free(target); |
3826 | return; |
3827 | } |
3828 | |
3829 | if (NARROW_MODE(ctx)) { |
3830 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
3831 | } else { |
3832 | tcg_gen_mov_tl(temp, cpu_ctr); |
3833 | } |
3834 | if (bo & 0x2) { |
3835 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); |
3836 | } else { |
3837 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
3838 | } |
3839 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
3840 | } else { |
3841 | tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1); |
3842 | if (NARROW_MODE(ctx)) { |
3843 | tcg_gen_ext32u_tl(temp, cpu_ctr); |
3844 | } else { |
3845 | tcg_gen_mov_tl(temp, cpu_ctr); |
3846 | } |
3847 | if (bo & 0x2) { |
3848 | tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1); |
3849 | } else { |
3850 | tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1); |
3851 | } |
3852 | } |
3853 | tcg_temp_free(temp); |
3854 | } |
3855 | if ((bo & 0x10) == 0) { |
3856 | /* Test CR */ |
3857 | uint32_t bi = BI(ctx->opcode); |
3858 | uint32_t mask = 0x08 >> (bi & 0x03); |
3859 | TCGv_i32 temp = tcg_temp_new_i32(); |
3860 | |
3861 | if (bo & 0x8) { |
3862 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3863 | tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1); |
3864 | } else { |
3865 | tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask); |
3866 | tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1); |
3867 | } |
3868 | tcg_temp_free_i32(temp); |
3869 | } |
3870 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
3871 | if (type == BCOND_IM) { |
3872 | target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); |
3873 | if (likely(AA(ctx->opcode) == 0)) { |
3874 | gen_goto_tb(ctx, 0, ctx->base.pc_next + li - 4); |
3875 | } else { |
3876 | gen_goto_tb(ctx, 0, li); |
3877 | } |
3878 | } else { |
3879 | if (NARROW_MODE(ctx)) { |
3880 | tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3); |
3881 | } else { |
3882 | tcg_gen_andi_tl(cpu_nip, target, ~3); |
3883 | } |
3884 | gen_lookup_and_goto_ptr(ctx); |
3885 | tcg_temp_free(target); |
3886 | } |
3887 | if ((bo & 0x14) != 0x14) { |
3888 | /* fallthrough case */ |
3889 | gen_set_label(l1); |
3890 | gen_goto_tb(ctx, 1, ctx->base.pc_next); |
3891 | } |
3892 | } |
3893 | |
3894 | static void gen_bc(DisasContext *ctx) |
3895 | { |
3896 | gen_bcond(ctx, BCOND_IM); |
3897 | } |
3898 | |
3899 | static void gen_bcctr(DisasContext *ctx) |
3900 | { |
3901 | gen_bcond(ctx, BCOND_CTR); |
3902 | } |
3903 | |
3904 | static void gen_bclr(DisasContext *ctx) |
3905 | { |
3906 | gen_bcond(ctx, BCOND_LR); |
3907 | } |
3908 | |
3909 | static void gen_bctar(DisasContext *ctx) |
3910 | { |
3911 | gen_bcond(ctx, BCOND_TAR); |
3912 | } |
3913 | |
3914 | /*** Condition register logical ***/ |
3915 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
3916 | static void glue(gen_, name)(DisasContext *ctx) \ |
3917 | { \ |
3918 | uint8_t bitmask; \ |
3919 | int sh; \ |
3920 | TCGv_i32 t0, t1; \ |
3921 | sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \ |
3922 | t0 = tcg_temp_new_i32(); \ |
3923 | if (sh > 0) \ |
3924 | tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \ |
3925 | else if (sh < 0) \ |
3926 | tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \ |
3927 | else \ |
3928 | tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \ |
3929 | t1 = tcg_temp_new_i32(); \ |
3930 | sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \ |
3931 | if (sh > 0) \ |
3932 | tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \ |
3933 | else if (sh < 0) \ |
3934 | tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \ |
3935 | else \ |
3936 | tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \ |
3937 | tcg_op(t0, t0, t1); \ |
3938 | bitmask = 0x08 >> (crbD(ctx->opcode) & 0x03); \ |
3939 | tcg_gen_andi_i32(t0, t0, bitmask); \ |
3940 | tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \ |
3941 | tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \ |
3942 | tcg_temp_free_i32(t0); \ |
3943 | tcg_temp_free_i32(t1); \ |
3944 | } |
3945 | |
3946 | /* crand */ |
3947 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08); |
3948 | /* crandc */ |
3949 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04); |
3950 | /* creqv */ |
3951 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09); |
3952 | /* crnand */ |
3953 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07); |
3954 | /* crnor */ |
3955 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01); |
3956 | /* cror */ |
3957 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E); |
3958 | /* crorc */ |
3959 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D); |
3960 | /* crxor */ |
3961 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06); |
3962 | |
3963 | /* mcrf */ |
3964 | static void gen_mcrf(DisasContext *ctx) |
3965 | { |
3966 | tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]); |
3967 | } |
3968 | |
3969 | /*** System linkage ***/ |
3970 | |
3971 | /* rfi (supervisor only) */ |
3972 | static void gen_rfi(DisasContext *ctx) |
3973 | { |
3974 | #if defined(CONFIG_USER_ONLY) |
3975 | GEN_PRIV; |
3976 | #else |
3977 | /* |
3978 | * This instruction doesn't exist anymore on 64-bit server |
3979 | * processors compliant with arch 2.x |
3980 | */ |
3981 | if (is_book3s_arch2x(ctx)) { |
3982 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
3983 | return; |
3984 | } |
3985 | /* Restore CPU state */ |
3986 | CHK_SV; |
3987 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
3988 | gen_io_start(); |
3989 | } |
3990 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
3991 | gen_helper_rfi(cpu_env); |
3992 | gen_sync_exception(ctx); |
3993 | #endif |
3994 | } |
3995 | |
3996 | #if defined(TARGET_PPC64) |
3997 | static void gen_rfid(DisasContext *ctx) |
3998 | { |
3999 | #if defined(CONFIG_USER_ONLY) |
4000 | GEN_PRIV; |
4001 | #else |
4002 | /* Restore CPU state */ |
4003 | CHK_SV; |
4004 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4005 | gen_io_start(); |
4006 | } |
4007 | gen_update_cfar(ctx, ctx->base.pc_next - 4); |
4008 | gen_helper_rfid(cpu_env); |
4009 | gen_sync_exception(ctx); |
4010 | #endif |
4011 | } |
4012 | |
4013 | static void gen_hrfid(DisasContext *ctx) |
4014 | { |
4015 | #if defined(CONFIG_USER_ONLY) |
4016 | GEN_PRIV; |
4017 | #else |
4018 | /* Restore CPU state */ |
4019 | CHK_HV; |
4020 | gen_helper_hrfid(cpu_env); |
4021 | gen_sync_exception(ctx); |
4022 | #endif |
4023 | } |
4024 | #endif |
4025 | |
4026 | /* sc */ |
4027 | #if defined(CONFIG_USER_ONLY) |
4028 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER |
4029 | #else |
4030 | #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL |
4031 | #endif |
4032 | static void gen_sc(DisasContext *ctx) |
4033 | { |
4034 | uint32_t lev; |
4035 | |
4036 | lev = (ctx->opcode >> 5) & 0x7F; |
4037 | gen_exception_err(ctx, POWERPC_SYSCALL, lev); |
4038 | } |
4039 | |
4040 | /*** Trap ***/ |
4041 | |
4042 | /* Check for unconditional traps (always or never) */ |
4043 | static bool check_unconditional_trap(DisasContext *ctx) |
4044 | { |
4045 | /* Trap never */ |
4046 | if (TO(ctx->opcode) == 0) { |
4047 | return true; |
4048 | } |
4049 | /* Trap always */ |
4050 | if (TO(ctx->opcode) == 31) { |
4051 | gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP); |
4052 | return true; |
4053 | } |
4054 | return false; |
4055 | } |
4056 | |
4057 | /* tw */ |
4058 | static void gen_tw(DisasContext *ctx) |
4059 | { |
4060 | TCGv_i32 t0; |
4061 | |
4062 | if (check_unconditional_trap(ctx)) { |
4063 | return; |
4064 | } |
4065 | t0 = tcg_const_i32(TO(ctx->opcode)); |
4066 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4067 | t0); |
4068 | tcg_temp_free_i32(t0); |
4069 | } |
4070 | |
4071 | /* twi */ |
4072 | static void gen_twi(DisasContext *ctx) |
4073 | { |
4074 | TCGv t0; |
4075 | TCGv_i32 t1; |
4076 | |
4077 | if (check_unconditional_trap(ctx)) { |
4078 | return; |
4079 | } |
4080 | t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4081 | t1 = tcg_const_i32(TO(ctx->opcode)); |
4082 | gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
4083 | tcg_temp_free(t0); |
4084 | tcg_temp_free_i32(t1); |
4085 | } |
4086 | |
4087 | #if defined(TARGET_PPC64) |
4088 | /* td */ |
4089 | static void gen_td(DisasContext *ctx) |
4090 | { |
4091 | TCGv_i32 t0; |
4092 | |
4093 | if (check_unconditional_trap(ctx)) { |
4094 | return; |
4095 | } |
4096 | t0 = tcg_const_i32(TO(ctx->opcode)); |
4097 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
4098 | t0); |
4099 | tcg_temp_free_i32(t0); |
4100 | } |
4101 | |
4102 | /* tdi */ |
4103 | static void gen_tdi(DisasContext *ctx) |
4104 | { |
4105 | TCGv t0; |
4106 | TCGv_i32 t1; |
4107 | |
4108 | if (check_unconditional_trap(ctx)) { |
4109 | return; |
4110 | } |
4111 | t0 = tcg_const_tl(SIMM(ctx->opcode)); |
4112 | t1 = tcg_const_i32(TO(ctx->opcode)); |
4113 | gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1); |
4114 | tcg_temp_free(t0); |
4115 | tcg_temp_free_i32(t1); |
4116 | } |
4117 | #endif |
4118 | |
4119 | /*** Processor control ***/ |
4120 | |
4121 | static void gen_read_xer(DisasContext *ctx, TCGv dst) |
4122 | { |
4123 | TCGv t0 = tcg_temp_new(); |
4124 | TCGv t1 = tcg_temp_new(); |
4125 | TCGv t2 = tcg_temp_new(); |
4126 | tcg_gen_mov_tl(dst, cpu_xer); |
4127 | tcg_gen_shli_tl(t0, cpu_so, XER_SO); |
4128 | tcg_gen_shli_tl(t1, cpu_ov, XER_OV); |
4129 | tcg_gen_shli_tl(t2, cpu_ca, XER_CA); |
4130 | tcg_gen_or_tl(t0, t0, t1); |
4131 | tcg_gen_or_tl(dst, dst, t2); |
4132 | tcg_gen_or_tl(dst, dst, t0); |
4133 | if (is_isa300(ctx)) { |
4134 | tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32); |
4135 | tcg_gen_or_tl(dst, dst, t0); |
4136 | tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32); |
4137 | tcg_gen_or_tl(dst, dst, t0); |
4138 | } |
4139 | tcg_temp_free(t0); |
4140 | tcg_temp_free(t1); |
4141 | tcg_temp_free(t2); |
4142 | } |
4143 | |
4144 | static void gen_write_xer(TCGv src) |
4145 | { |
4146 | /* Write all flags, while reading back check for isa300 */ |
4147 | tcg_gen_andi_tl(cpu_xer, src, |
4148 | ~((1u << XER_SO) | |
4149 | (1u << XER_OV) | (1u << XER_OV32) | |
4150 | (1u << XER_CA) | (1u << XER_CA32))); |
4151 | tcg_gen_extract_tl(cpu_ov32, src, XER_OV32, 1); |
4152 | tcg_gen_extract_tl(cpu_ca32, src, XER_CA32, 1); |
4153 | tcg_gen_extract_tl(cpu_so, src, XER_SO, 1); |
4154 | tcg_gen_extract_tl(cpu_ov, src, XER_OV, 1); |
4155 | tcg_gen_extract_tl(cpu_ca, src, XER_CA, 1); |
4156 | } |
4157 | |
4158 | /* mcrxr */ |
4159 | static void gen_mcrxr(DisasContext *ctx) |
4160 | { |
4161 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4162 | TCGv_i32 t1 = tcg_temp_new_i32(); |
4163 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; |
4164 | |
4165 | tcg_gen_trunc_tl_i32(t0, cpu_so); |
4166 | tcg_gen_trunc_tl_i32(t1, cpu_ov); |
4167 | tcg_gen_trunc_tl_i32(dst, cpu_ca); |
4168 | tcg_gen_shli_i32(t0, t0, 3); |
4169 | tcg_gen_shli_i32(t1, t1, 2); |
4170 | tcg_gen_shli_i32(dst, dst, 1); |
4171 | tcg_gen_or_i32(dst, dst, t0); |
4172 | tcg_gen_or_i32(dst, dst, t1); |
4173 | tcg_temp_free_i32(t0); |
4174 | tcg_temp_free_i32(t1); |
4175 | |
4176 | tcg_gen_movi_tl(cpu_so, 0); |
4177 | tcg_gen_movi_tl(cpu_ov, 0); |
4178 | tcg_gen_movi_tl(cpu_ca, 0); |
4179 | } |
4180 | |
4181 | #ifdef TARGET_PPC64 |
4182 | /* mcrxrx */ |
4183 | static void gen_mcrxrx(DisasContext *ctx) |
4184 | { |
4185 | TCGv t0 = tcg_temp_new(); |
4186 | TCGv t1 = tcg_temp_new(); |
4187 | TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)]; |
4188 | |
4189 | /* copy OV and OV32 */ |
4190 | tcg_gen_shli_tl(t0, cpu_ov, 1); |
4191 | tcg_gen_or_tl(t0, t0, cpu_ov32); |
4192 | tcg_gen_shli_tl(t0, t0, 2); |
4193 | /* copy CA and CA32 */ |
4194 | tcg_gen_shli_tl(t1, cpu_ca, 1); |
4195 | tcg_gen_or_tl(t1, t1, cpu_ca32); |
4196 | tcg_gen_or_tl(t0, t0, t1); |
4197 | tcg_gen_trunc_tl_i32(dst, t0); |
4198 | tcg_temp_free(t0); |
4199 | tcg_temp_free(t1); |
4200 | } |
4201 | #endif |
4202 | |
4203 | /* mfcr mfocrf */ |
4204 | static void gen_mfcr(DisasContext *ctx) |
4205 | { |
4206 | uint32_t crm, crn; |
4207 | |
4208 | if (likely(ctx->opcode & 0x00100000)) { |
4209 | crm = CRM(ctx->opcode); |
4210 | if (likely(crm && ((crm & (crm - 1)) == 0))) { |
4211 | crn = ctz32(crm); |
4212 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); |
4213 | tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], |
4214 | cpu_gpr[rD(ctx->opcode)], crn * 4); |
4215 | } |
4216 | } else { |
4217 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4218 | tcg_gen_mov_i32(t0, cpu_crf[0]); |
4219 | tcg_gen_shli_i32(t0, t0, 4); |
4220 | tcg_gen_or_i32(t0, t0, cpu_crf[1]); |
4221 | tcg_gen_shli_i32(t0, t0, 4); |
4222 | tcg_gen_or_i32(t0, t0, cpu_crf[2]); |
4223 | tcg_gen_shli_i32(t0, t0, 4); |
4224 | tcg_gen_or_i32(t0, t0, cpu_crf[3]); |
4225 | tcg_gen_shli_i32(t0, t0, 4); |
4226 | tcg_gen_or_i32(t0, t0, cpu_crf[4]); |
4227 | tcg_gen_shli_i32(t0, t0, 4); |
4228 | tcg_gen_or_i32(t0, t0, cpu_crf[5]); |
4229 | tcg_gen_shli_i32(t0, t0, 4); |
4230 | tcg_gen_or_i32(t0, t0, cpu_crf[6]); |
4231 | tcg_gen_shli_i32(t0, t0, 4); |
4232 | tcg_gen_or_i32(t0, t0, cpu_crf[7]); |
4233 | tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4234 | tcg_temp_free_i32(t0); |
4235 | } |
4236 | } |
4237 | |
4238 | /* mfmsr */ |
4239 | static void gen_mfmsr(DisasContext *ctx) |
4240 | { |
4241 | CHK_SV; |
4242 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr); |
4243 | } |
4244 | |
4245 | static void spr_noaccess(DisasContext *ctx, int gprn, int sprn) |
4246 | { |
4247 | #if 0 |
4248 | sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5); |
4249 | printf("ERROR: try to access SPR %d !\n" , sprn); |
4250 | #endif |
4251 | } |
4252 | #define SPR_NOACCESS (&spr_noaccess) |
4253 | |
4254 | /* mfspr */ |
4255 | static inline void gen_op_mfspr(DisasContext *ctx) |
4256 | { |
4257 | void (*read_cb)(DisasContext *ctx, int gprn, int sprn); |
4258 | uint32_t sprn = SPR(ctx->opcode); |
4259 | |
4260 | #if defined(CONFIG_USER_ONLY) |
4261 | read_cb = ctx->spr_cb[sprn].uea_read; |
4262 | #else |
4263 | if (ctx->pr) { |
4264 | read_cb = ctx->spr_cb[sprn].uea_read; |
4265 | } else if (ctx->hv) { |
4266 | read_cb = ctx->spr_cb[sprn].hea_read; |
4267 | } else { |
4268 | read_cb = ctx->spr_cb[sprn].oea_read; |
4269 | } |
4270 | #endif |
4271 | if (likely(read_cb != NULL)) { |
4272 | if (likely(read_cb != SPR_NOACCESS)) { |
4273 | (*read_cb)(ctx, rD(ctx->opcode), sprn); |
4274 | } else { |
4275 | /* Privilege exception */ |
4276 | /* |
4277 | * This is a hack to avoid warnings when running Linux: |
4278 | * this OS breaks the PowerPC virtualisation model, |
4279 | * allowing userland application to read the PVR |
4280 | */ |
4281 | if (sprn != SPR_PVR) { |
4282 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to read privileged spr " |
4283 | "%d (0x%03x) at " TARGET_FMT_lx "\n" , sprn, sprn, |
4284 | ctx->base.pc_next - 4); |
4285 | } |
4286 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4287 | } |
4288 | } else { |
4289 | /* ISA 2.07 defines these as no-ops */ |
4290 | if ((ctx->insns_flags2 & PPC2_ISA207S) && |
4291 | (sprn >= 808 && sprn <= 811)) { |
4292 | /* This is a nop */ |
4293 | return; |
4294 | } |
4295 | /* Not defined */ |
4296 | qemu_log_mask(LOG_GUEST_ERROR, |
4297 | "Trying to read invalid spr %d (0x%03x) at " |
4298 | TARGET_FMT_lx "\n" , sprn, sprn, ctx->base.pc_next - 4); |
4299 | |
4300 | /* |
4301 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can |
4302 | * generate a priv, a hv emu or a no-op |
4303 | */ |
4304 | if (sprn & 0x10) { |
4305 | if (ctx->pr) { |
4306 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
4307 | } |
4308 | } else { |
4309 | if (ctx->pr || sprn == 0 || sprn == 4 || sprn == 5 || sprn == 6) { |
4310 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
4311 | } |
4312 | } |
4313 | } |
4314 | } |
4315 | |
4316 | static void gen_mfspr(DisasContext *ctx) |
4317 | { |
4318 | gen_op_mfspr(ctx); |
4319 | } |
4320 | |
4321 | /* mftb */ |
4322 | static void gen_mftb(DisasContext *ctx) |
4323 | { |
4324 | gen_op_mfspr(ctx); |
4325 | } |
4326 | |
4327 | /* mtcrf mtocrf*/ |
4328 | static void gen_mtcrf(DisasContext *ctx) |
4329 | { |
4330 | uint32_t crm, crn; |
4331 | |
4332 | crm = CRM(ctx->opcode); |
4333 | if (likely((ctx->opcode & 0x00100000))) { |
4334 | if (crm && ((crm & (crm - 1)) == 0)) { |
4335 | TCGv_i32 temp = tcg_temp_new_i32(); |
4336 | crn = ctz32(crm); |
4337 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
4338 | tcg_gen_shri_i32(temp, temp, crn * 4); |
4339 | tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); |
4340 | tcg_temp_free_i32(temp); |
4341 | } |
4342 | } else { |
4343 | TCGv_i32 temp = tcg_temp_new_i32(); |
4344 | tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]); |
4345 | for (crn = 0 ; crn < 8 ; crn++) { |
4346 | if (crm & (1 << crn)) { |
4347 | tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4); |
4348 | tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf); |
4349 | } |
4350 | } |
4351 | tcg_temp_free_i32(temp); |
4352 | } |
4353 | } |
4354 | |
4355 | /* mtmsr */ |
4356 | #if defined(TARGET_PPC64) |
4357 | static void gen_mtmsrd(DisasContext *ctx) |
4358 | { |
4359 | CHK_SV; |
4360 | |
4361 | #if !defined(CONFIG_USER_ONLY) |
4362 | if (ctx->opcode & 0x00010000) { |
4363 | /* Special form that does not need any synchronisation */ |
4364 | TCGv t0 = tcg_temp_new(); |
4365 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], |
4366 | (1 << MSR_RI) | (1 << MSR_EE)); |
4367 | tcg_gen_andi_tl(cpu_msr, cpu_msr, |
4368 | ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
4369 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4370 | tcg_temp_free(t0); |
4371 | } else { |
4372 | /* |
4373 | * XXX: we need to update nip before the store if we enter |
4374 | * power saving mode, we will exit the loop directly from |
4375 | * ppc_store_msr |
4376 | */ |
4377 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4378 | gen_io_start(); |
4379 | } |
4380 | gen_update_nip(ctx, ctx->base.pc_next); |
4381 | gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]); |
4382 | /* Must stop the translation as machine state (may have) changed */ |
4383 | /* Note that mtmsr is not always defined as context-synchronizing */ |
4384 | gen_stop_exception(ctx); |
4385 | } |
4386 | #endif /* !defined(CONFIG_USER_ONLY) */ |
4387 | } |
4388 | #endif /* defined(TARGET_PPC64) */ |
4389 | |
4390 | static void gen_mtmsr(DisasContext *ctx) |
4391 | { |
4392 | CHK_SV; |
4393 | |
4394 | #if !defined(CONFIG_USER_ONLY) |
4395 | if (ctx->opcode & 0x00010000) { |
4396 | /* Special form that does not need any synchronisation */ |
4397 | TCGv t0 = tcg_temp_new(); |
4398 | tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], |
4399 | (1 << MSR_RI) | (1 << MSR_EE)); |
4400 | tcg_gen_andi_tl(cpu_msr, cpu_msr, |
4401 | ~(target_ulong)((1 << MSR_RI) | (1 << MSR_EE))); |
4402 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
4403 | tcg_temp_free(t0); |
4404 | } else { |
4405 | TCGv msr = tcg_temp_new(); |
4406 | |
4407 | /* |
4408 | * XXX: we need to update nip before the store if we enter |
4409 | * power saving mode, we will exit the loop directly from |
4410 | * ppc_store_msr |
4411 | */ |
4412 | if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { |
4413 | gen_io_start(); |
4414 | } |
4415 | gen_update_nip(ctx, ctx->base.pc_next); |
4416 | #if defined(TARGET_PPC64) |
4417 | tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32); |
4418 | #else |
4419 | tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]); |
4420 | #endif |
4421 | gen_helper_store_msr(cpu_env, msr); |
4422 | tcg_temp_free(msr); |
4423 | /* Must stop the translation as machine state (may have) changed */ |
4424 | /* Note that mtmsr is not always defined as context-synchronizing */ |
4425 | gen_stop_exception(ctx); |
4426 | } |
4427 | #endif |
4428 | } |
4429 | |
4430 | /* mtspr */ |
4431 | static void gen_mtspr(DisasContext *ctx) |
4432 | { |
4433 | void (*write_cb)(DisasContext *ctx, int sprn, int gprn); |
4434 | uint32_t sprn = SPR(ctx->opcode); |
4435 | |
4436 | #if defined(CONFIG_USER_ONLY) |
4437 | write_cb = ctx->spr_cb[sprn].uea_write; |
4438 | #else |
4439 | if (ctx->pr) { |
4440 | write_cb = ctx->spr_cb[sprn].uea_write; |
4441 | } else if (ctx->hv) { |
4442 | write_cb = ctx->spr_cb[sprn].hea_write; |
4443 | } else { |
4444 | write_cb = ctx->spr_cb[sprn].oea_write; |
4445 | } |
4446 | #endif |
4447 | if (likely(write_cb != NULL)) { |
4448 | if (likely(write_cb != SPR_NOACCESS)) { |
4449 | (*write_cb)(ctx, sprn, rS(ctx->opcode)); |
4450 | } else { |
4451 | /* Privilege exception */ |
4452 | qemu_log_mask(LOG_GUEST_ERROR, "Trying to write privileged spr " |
4453 | "%d (0x%03x) at " TARGET_FMT_lx "\n" , sprn, sprn, |
4454 | ctx->base.pc_next - 4); |
4455 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4456 | } |
4457 | } else { |
4458 | /* ISA 2.07 defines these as no-ops */ |
4459 | if ((ctx->insns_flags2 & PPC2_ISA207S) && |
4460 | (sprn >= 808 && sprn <= 811)) { |
4461 | /* This is a nop */ |
4462 | return; |
4463 | } |
4464 | |
4465 | /* Not defined */ |
4466 | qemu_log_mask(LOG_GUEST_ERROR, |
4467 | "Trying to write invalid spr %d (0x%03x) at " |
4468 | TARGET_FMT_lx "\n" , sprn, sprn, ctx->base.pc_next - 4); |
4469 | |
4470 | |
4471 | /* |
4472 | * The behaviour depends on MSR:PR and SPR# bit 0x10, it can |
4473 | * generate a priv, a hv emu or a no-op |
4474 | */ |
4475 | if (sprn & 0x10) { |
4476 | if (ctx->pr) { |
4477 | gen_priv_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
4478 | } |
4479 | } else { |
4480 | if (ctx->pr || sprn == 0) { |
4481 | gen_hvpriv_exception(ctx, POWERPC_EXCP_INVAL_SPR); |
4482 | } |
4483 | } |
4484 | } |
4485 | } |
4486 | |
4487 | #if defined(TARGET_PPC64) |
4488 | /* setb */ |
4489 | static void gen_setb(DisasContext *ctx) |
4490 | { |
4491 | TCGv_i32 t0 = tcg_temp_new_i32(); |
4492 | TCGv_i32 t8 = tcg_temp_new_i32(); |
4493 | TCGv_i32 tm1 = tcg_temp_new_i32(); |
4494 | int crf = crfS(ctx->opcode); |
4495 | |
4496 | tcg_gen_setcondi_i32(TCG_COND_GEU, t0, cpu_crf[crf], 4); |
4497 | tcg_gen_movi_i32(t8, 8); |
4498 | tcg_gen_movi_i32(tm1, -1); |
4499 | tcg_gen_movcond_i32(TCG_COND_GEU, t0, cpu_crf[crf], t8, tm1, t0); |
4500 | tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0); |
4501 | |
4502 | tcg_temp_free_i32(t0); |
4503 | tcg_temp_free_i32(t8); |
4504 | tcg_temp_free_i32(tm1); |
4505 | } |
4506 | #endif |
4507 | |
4508 | /*** Cache management ***/ |
4509 | |
4510 | /* dcbf */ |
4511 | static void gen_dcbf(DisasContext *ctx) |
4512 | { |
4513 | /* XXX: specification says this is treated as a load by the MMU */ |
4514 | TCGv t0; |
4515 | gen_set_access_type(ctx, ACCESS_CACHE); |
4516 | t0 = tcg_temp_new(); |
4517 | gen_addr_reg_index(ctx, t0); |
4518 | gen_qemu_ld8u(ctx, t0, t0); |
4519 | tcg_temp_free(t0); |
4520 | } |
4521 | |
4522 | /* dcbfep (external PID dcbf) */ |
4523 | static void gen_dcbfep(DisasContext *ctx) |
4524 | { |
4525 | /* XXX: specification says this is treated as a load by the MMU */ |
4526 | TCGv t0; |
4527 | CHK_SV; |
4528 | gen_set_access_type(ctx, ACCESS_CACHE); |
4529 | t0 = tcg_temp_new(); |
4530 | gen_addr_reg_index(ctx, t0); |
4531 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); |
4532 | tcg_temp_free(t0); |
4533 | } |
4534 | |
4535 | /* dcbi (Supervisor only) */ |
4536 | static void gen_dcbi(DisasContext *ctx) |
4537 | { |
4538 | #if defined(CONFIG_USER_ONLY) |
4539 | GEN_PRIV; |
4540 | #else |
4541 | TCGv EA, val; |
4542 | |
4543 | CHK_SV; |
4544 | EA = tcg_temp_new(); |
4545 | gen_set_access_type(ctx, ACCESS_CACHE); |
4546 | gen_addr_reg_index(ctx, EA); |
4547 | val = tcg_temp_new(); |
4548 | /* XXX: specification says this should be treated as a store by the MMU */ |
4549 | gen_qemu_ld8u(ctx, val, EA); |
4550 | gen_qemu_st8(ctx, val, EA); |
4551 | tcg_temp_free(val); |
4552 | tcg_temp_free(EA); |
4553 | #endif /* defined(CONFIG_USER_ONLY) */ |
4554 | } |
4555 | |
4556 | /* dcdst */ |
4557 | static void gen_dcbst(DisasContext *ctx) |
4558 | { |
4559 | /* XXX: specification say this is treated as a load by the MMU */ |
4560 | TCGv t0; |
4561 | gen_set_access_type(ctx, ACCESS_CACHE); |
4562 | t0 = tcg_temp_new(); |
4563 | gen_addr_reg_index(ctx, t0); |
4564 | gen_qemu_ld8u(ctx, t0, t0); |
4565 | tcg_temp_free(t0); |
4566 | } |
4567 | |
4568 | /* dcbstep (dcbstep External PID version) */ |
4569 | static void gen_dcbstep(DisasContext *ctx) |
4570 | { |
4571 | /* XXX: specification say this is treated as a load by the MMU */ |
4572 | TCGv t0; |
4573 | gen_set_access_type(ctx, ACCESS_CACHE); |
4574 | t0 = tcg_temp_new(); |
4575 | gen_addr_reg_index(ctx, t0); |
4576 | tcg_gen_qemu_ld_tl(t0, t0, PPC_TLB_EPID_LOAD, DEF_MEMOP(MO_UB)); |
4577 | tcg_temp_free(t0); |
4578 | } |
4579 | |
4580 | /* dcbt */ |
4581 | static void gen_dcbt(DisasContext *ctx) |
4582 | { |
4583 | /* |
4584 | * interpreted as no-op |
4585 | * XXX: specification say this is treated as a load by the MMU but |
4586 | * does not generate any exception |
4587 | */ |
4588 | } |
4589 | |
4590 | /* dcbtep */ |
4591 | static void gen_dcbtep(DisasContext *ctx) |
4592 | { |
4593 | /* |
4594 | * interpreted as no-op |
4595 | * XXX: specification say this is treated as a load by the MMU but |
4596 | * does not generate any exception |
4597 | */ |
4598 | } |
4599 | |
4600 | /* dcbtst */ |
4601 | static void gen_dcbtst(DisasContext *ctx) |
4602 | { |
4603 | /* |
4604 | * interpreted as no-op |
4605 | * XXX: specification say this is treated as a load by the MMU but |
4606 | * does not generate any exception |
4607 | */ |
4608 | } |
4609 | |
4610 | /* dcbtstep */ |
4611 | static void gen_dcbtstep(DisasContext *ctx) |
4612 | { |
4613 | /* |
4614 | * interpreted as no-op |
4615 | * XXX: specification say this is treated as a load by the MMU but |
4616 | * does not generate any exception |
4617 | */ |
4618 | } |
4619 | |
4620 | /* dcbtls */ |
4621 | static void gen_dcbtls(DisasContext *ctx) |
4622 | { |
4623 | /* Always fails locking the cache */ |
4624 | TCGv t0 = tcg_temp_new(); |
4625 | gen_load_spr(t0, SPR_Exxx_L1CSR0); |
4626 | tcg_gen_ori_tl(t0, t0, L1CSR0_CUL); |
4627 | gen_store_spr(SPR_Exxx_L1CSR0, t0); |
4628 | tcg_temp_free(t0); |
4629 | } |
4630 | |
4631 | /* dcbz */ |
4632 | static void gen_dcbz(DisasContext *ctx) |
4633 | { |
4634 | TCGv tcgv_addr; |
4635 | TCGv_i32 tcgv_op; |
4636 | |
4637 | gen_set_access_type(ctx, ACCESS_CACHE); |
4638 | tcgv_addr = tcg_temp_new(); |
4639 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
4640 | gen_addr_reg_index(ctx, tcgv_addr); |
4641 | gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_op); |
4642 | tcg_temp_free(tcgv_addr); |
4643 | tcg_temp_free_i32(tcgv_op); |
4644 | } |
4645 | |
4646 | /* dcbzep */ |
4647 | static void gen_dcbzep(DisasContext *ctx) |
4648 | { |
4649 | TCGv tcgv_addr; |
4650 | TCGv_i32 tcgv_op; |
4651 | |
4652 | gen_set_access_type(ctx, ACCESS_CACHE); |
4653 | tcgv_addr = tcg_temp_new(); |
4654 | tcgv_op = tcg_const_i32(ctx->opcode & 0x03FF000); |
4655 | gen_addr_reg_index(ctx, tcgv_addr); |
4656 | gen_helper_dcbzep(cpu_env, tcgv_addr, tcgv_op); |
4657 | tcg_temp_free(tcgv_addr); |
4658 | tcg_temp_free_i32(tcgv_op); |
4659 | } |
4660 | |
4661 | /* dst / dstt */ |
4662 | static void gen_dst(DisasContext *ctx) |
4663 | { |
4664 | if (rA(ctx->opcode) == 0) { |
4665 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
4666 | } else { |
4667 | /* interpreted as no-op */ |
4668 | } |
4669 | } |
4670 | |
4671 | /* dstst /dststt */ |
4672 | static void gen_dstst(DisasContext *ctx) |
4673 | { |
4674 | if (rA(ctx->opcode) == 0) { |
4675 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
4676 | } else { |
4677 | /* interpreted as no-op */ |
4678 | } |
4679 | |
4680 | } |
4681 | |
4682 | /* dss / dssall */ |
4683 | static void gen_dss(DisasContext *ctx) |
4684 | { |
4685 | /* interpreted as no-op */ |
4686 | } |
4687 | |
4688 | /* icbi */ |
4689 | static void gen_icbi(DisasContext *ctx) |
4690 | { |
4691 | TCGv t0; |
4692 | gen_set_access_type(ctx, ACCESS_CACHE); |
4693 | t0 = tcg_temp_new(); |
4694 | gen_addr_reg_index(ctx, t0); |
4695 | gen_helper_icbi(cpu_env, t0); |
4696 | tcg_temp_free(t0); |
4697 | } |
4698 | |
4699 | /* icbiep */ |
4700 | static void gen_icbiep(DisasContext *ctx) |
4701 | { |
4702 | TCGv t0; |
4703 | gen_set_access_type(ctx, ACCESS_CACHE); |
4704 | t0 = tcg_temp_new(); |
4705 | gen_addr_reg_index(ctx, t0); |
4706 | gen_helper_icbiep(cpu_env, t0); |
4707 | tcg_temp_free(t0); |
4708 | } |
4709 | |
4710 | /* Optional: */ |
4711 | /* dcba */ |
4712 | static void gen_dcba(DisasContext *ctx) |
4713 | { |
4714 | /* |
4715 | * interpreted as no-op |
4716 | * XXX: specification say this is treated as a store by the MMU |
4717 | * but does not generate any exception |
4718 | */ |
4719 | } |
4720 | |
4721 | /*** Segment register manipulation ***/ |
4722 | /* Supervisor only: */ |
4723 | |
4724 | /* mfsr */ |
4725 | static void gen_mfsr(DisasContext *ctx) |
4726 | { |
4727 | #if defined(CONFIG_USER_ONLY) |
4728 | GEN_PRIV; |
4729 | #else |
4730 | TCGv t0; |
4731 | |
4732 | CHK_SV; |
4733 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4734 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4735 | tcg_temp_free(t0); |
4736 | #endif /* defined(CONFIG_USER_ONLY) */ |
4737 | } |
4738 | |
4739 | /* mfsrin */ |
4740 | static void gen_mfsrin(DisasContext *ctx) |
4741 | { |
4742 | #if defined(CONFIG_USER_ONLY) |
4743 | GEN_PRIV; |
4744 | #else |
4745 | TCGv t0; |
4746 | |
4747 | CHK_SV; |
4748 | t0 = tcg_temp_new(); |
4749 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
4750 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4751 | tcg_temp_free(t0); |
4752 | #endif /* defined(CONFIG_USER_ONLY) */ |
4753 | } |
4754 | |
4755 | /* mtsr */ |
4756 | static void gen_mtsr(DisasContext *ctx) |
4757 | { |
4758 | #if defined(CONFIG_USER_ONLY) |
4759 | GEN_PRIV; |
4760 | #else |
4761 | TCGv t0; |
4762 | |
4763 | CHK_SV; |
4764 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4765 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
4766 | tcg_temp_free(t0); |
4767 | #endif /* defined(CONFIG_USER_ONLY) */ |
4768 | } |
4769 | |
4770 | /* mtsrin */ |
4771 | static void gen_mtsrin(DisasContext *ctx) |
4772 | { |
4773 | #if defined(CONFIG_USER_ONLY) |
4774 | GEN_PRIV; |
4775 | #else |
4776 | TCGv t0; |
4777 | CHK_SV; |
4778 | |
4779 | t0 = tcg_temp_new(); |
4780 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
4781 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); |
4782 | tcg_temp_free(t0); |
4783 | #endif /* defined(CONFIG_USER_ONLY) */ |
4784 | } |
4785 | |
4786 | #if defined(TARGET_PPC64) |
4787 | /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */ |
4788 | |
4789 | /* mfsr */ |
4790 | static void gen_mfsr_64b(DisasContext *ctx) |
4791 | { |
4792 | #if defined(CONFIG_USER_ONLY) |
4793 | GEN_PRIV; |
4794 | #else |
4795 | TCGv t0; |
4796 | |
4797 | CHK_SV; |
4798 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4799 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4800 | tcg_temp_free(t0); |
4801 | #endif /* defined(CONFIG_USER_ONLY) */ |
4802 | } |
4803 | |
4804 | /* mfsrin */ |
4805 | static void gen_mfsrin_64b(DisasContext *ctx) |
4806 | { |
4807 | #if defined(CONFIG_USER_ONLY) |
4808 | GEN_PRIV; |
4809 | #else |
4810 | TCGv t0; |
4811 | |
4812 | CHK_SV; |
4813 | t0 = tcg_temp_new(); |
4814 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
4815 | gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
4816 | tcg_temp_free(t0); |
4817 | #endif /* defined(CONFIG_USER_ONLY) */ |
4818 | } |
4819 | |
4820 | /* mtsr */ |
4821 | static void gen_mtsr_64b(DisasContext *ctx) |
4822 | { |
4823 | #if defined(CONFIG_USER_ONLY) |
4824 | GEN_PRIV; |
4825 | #else |
4826 | TCGv t0; |
4827 | |
4828 | CHK_SV; |
4829 | t0 = tcg_const_tl(SR(ctx->opcode)); |
4830 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
4831 | tcg_temp_free(t0); |
4832 | #endif /* defined(CONFIG_USER_ONLY) */ |
4833 | } |
4834 | |
4835 | /* mtsrin */ |
4836 | static void gen_mtsrin_64b(DisasContext *ctx) |
4837 | { |
4838 | #if defined(CONFIG_USER_ONLY) |
4839 | GEN_PRIV; |
4840 | #else |
4841 | TCGv t0; |
4842 | |
4843 | CHK_SV; |
4844 | t0 = tcg_temp_new(); |
4845 | tcg_gen_extract_tl(t0, cpu_gpr[rB(ctx->opcode)], 28, 4); |
4846 | gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); |
4847 | tcg_temp_free(t0); |
4848 | #endif /* defined(CONFIG_USER_ONLY) */ |
4849 | } |
4850 | |
4851 | /* slbmte */ |
4852 | static void gen_slbmte(DisasContext *ctx) |
4853 | { |
4854 | #if defined(CONFIG_USER_ONLY) |
4855 | GEN_PRIV; |
4856 | #else |
4857 | CHK_SV; |
4858 | |
4859 | gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], |
4860 | cpu_gpr[rS(ctx->opcode)]); |
4861 | #endif /* defined(CONFIG_USER_ONLY) */ |
4862 | } |
4863 | |
4864 | static void gen_slbmfee(DisasContext *ctx) |
4865 | { |
4866 | #if defined(CONFIG_USER_ONLY) |
4867 | GEN_PRIV; |
4868 | #else |
4869 | CHK_SV; |
4870 | |
4871 | gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
4872 | cpu_gpr[rB(ctx->opcode)]); |
4873 | #endif /* defined(CONFIG_USER_ONLY) */ |
4874 | } |
4875 | |
4876 | static void gen_slbmfev(DisasContext *ctx) |
4877 | { |
4878 | #if defined(CONFIG_USER_ONLY) |
4879 | GEN_PRIV; |
4880 | #else |
4881 | CHK_SV; |
4882 | |
4883 | gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
4884 | cpu_gpr[rB(ctx->opcode)]); |
4885 | #endif /* defined(CONFIG_USER_ONLY) */ |
4886 | } |
4887 | |
4888 | static void gen_slbfee_(DisasContext *ctx) |
4889 | { |
4890 | #if defined(CONFIG_USER_ONLY) |
4891 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4892 | #else |
4893 | TCGLabel *l1, *l2; |
4894 | |
4895 | if (unlikely(ctx->pr)) { |
4896 | gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
4897 | return; |
4898 | } |
4899 | gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, |
4900 | cpu_gpr[rB(ctx->opcode)]); |
4901 | l1 = gen_new_label(); |
4902 | l2 = gen_new_label(); |
4903 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
4904 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1); |
4905 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); |
4906 | tcg_gen_br(l2); |
4907 | gen_set_label(l1); |
4908 | tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0); |
4909 | gen_set_label(l2); |
4910 | #endif |
4911 | } |
4912 | #endif /* defined(TARGET_PPC64) */ |
4913 | |
4914 | /*** Lookaside buffer management ***/ |
4915 | /* Optional & supervisor only: */ |
4916 | |
4917 | /* tlbia */ |
4918 | static void gen_tlbia(DisasContext *ctx) |
4919 | { |
4920 | #if defined(CONFIG_USER_ONLY) |
4921 | GEN_PRIV; |
4922 | #else |
4923 | CHK_HV; |
4924 | |
4925 | gen_helper_tlbia(cpu_env); |
4926 | #endif /* defined(CONFIG_USER_ONLY) */ |
4927 | } |
4928 | |
4929 | /* tlbiel */ |
4930 | static void gen_tlbiel(DisasContext *ctx) |
4931 | { |
4932 | #if defined(CONFIG_USER_ONLY) |
4933 | GEN_PRIV; |
4934 | #else |
4935 | CHK_SV; |
4936 | |
4937 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
4938 | #endif /* defined(CONFIG_USER_ONLY) */ |
4939 | } |
4940 | |
4941 | /* tlbie */ |
4942 | static void gen_tlbie(DisasContext *ctx) |
4943 | { |
4944 | #if defined(CONFIG_USER_ONLY) |
4945 | GEN_PRIV; |
4946 | #else |
4947 | TCGv_i32 t1; |
4948 | |
4949 | if (ctx->gtse) { |
4950 | CHK_SV; /* If gtse is set then tlbie is supervisor privileged */ |
4951 | } else { |
4952 | CHK_HV; /* Else hypervisor privileged */ |
4953 | } |
4954 | |
4955 | if (NARROW_MODE(ctx)) { |
4956 | TCGv t0 = tcg_temp_new(); |
4957 | tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); |
4958 | gen_helper_tlbie(cpu_env, t0); |
4959 | tcg_temp_free(t0); |
4960 | } else { |
4961 | gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
4962 | } |
4963 | t1 = tcg_temp_new_i32(); |
4964 | tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
4965 | tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); |
4966 | tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); |
4967 | tcg_temp_free_i32(t1); |
4968 | #endif /* defined(CONFIG_USER_ONLY) */ |
4969 | } |
4970 | |
4971 | /* tlbsync */ |
4972 | static void gen_tlbsync(DisasContext *ctx) |
4973 | { |
4974 | #if defined(CONFIG_USER_ONLY) |
4975 | GEN_PRIV; |
4976 | #else |
4977 | |
4978 | if (ctx->gtse) { |
4979 | CHK_SV; /* If gtse is set then tlbsync is supervisor privileged */ |
4980 | } else { |
4981 | CHK_HV; /* Else hypervisor privileged */ |
4982 | } |
4983 | |
4984 | /* BookS does both ptesync and tlbsync make tlbsync a nop for server */ |
4985 | if (ctx->insns_flags & PPC_BOOKE) { |
4986 | gen_check_tlb_flush(ctx, true); |
4987 | } |
4988 | #endif /* defined(CONFIG_USER_ONLY) */ |
4989 | } |
4990 | |
4991 | #if defined(TARGET_PPC64) |
4992 | /* slbia */ |
4993 | static void gen_slbia(DisasContext *ctx) |
4994 | { |
4995 | #if defined(CONFIG_USER_ONLY) |
4996 | GEN_PRIV; |
4997 | #else |
4998 | CHK_SV; |
4999 | |
5000 | gen_helper_slbia(cpu_env); |
5001 | #endif /* defined(CONFIG_USER_ONLY) */ |
5002 | } |
5003 | |
5004 | /* slbie */ |
5005 | static void gen_slbie(DisasContext *ctx) |
5006 | { |
5007 | #if defined(CONFIG_USER_ONLY) |
5008 | GEN_PRIV; |
5009 | #else |
5010 | CHK_SV; |
5011 | |
5012 | gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5013 | #endif /* defined(CONFIG_USER_ONLY) */ |
5014 | } |
5015 | |
5016 | /* slbieg */ |
5017 | static void gen_slbieg(DisasContext *ctx) |
5018 | { |
5019 | #if defined(CONFIG_USER_ONLY) |
5020 | GEN_PRIV; |
5021 | #else |
5022 | CHK_SV; |
5023 | |
5024 | gen_helper_slbieg(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5025 | #endif /* defined(CONFIG_USER_ONLY) */ |
5026 | } |
5027 | |
5028 | /* slbsync */ |
5029 | static void gen_slbsync(DisasContext *ctx) |
5030 | { |
5031 | #if defined(CONFIG_USER_ONLY) |
5032 | GEN_PRIV; |
5033 | #else |
5034 | CHK_SV; |
5035 | gen_check_tlb_flush(ctx, true); |
5036 | #endif /* defined(CONFIG_USER_ONLY) */ |
5037 | } |
5038 | |
5039 | #endif /* defined(TARGET_PPC64) */ |
5040 | |
5041 | /*** External control ***/ |
5042 | /* Optional: */ |
5043 | |
5044 | /* eciwx */ |
5045 | static void gen_eciwx(DisasContext *ctx) |
5046 | { |
5047 | TCGv t0; |
5048 | /* Should check EAR[E] ! */ |
5049 | gen_set_access_type(ctx, ACCESS_EXT); |
5050 | t0 = tcg_temp_new(); |
5051 | gen_addr_reg_index(ctx, t0); |
5052 | tcg_gen_qemu_ld_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5053 | DEF_MEMOP(MO_UL | MO_ALIGN)); |
5054 | tcg_temp_free(t0); |
5055 | } |
5056 | |
5057 | /* ecowx */ |
5058 | static void gen_ecowx(DisasContext *ctx) |
5059 | { |
5060 | TCGv t0; |
5061 | /* Should check EAR[E] ! */ |
5062 | gen_set_access_type(ctx, ACCESS_EXT); |
5063 | t0 = tcg_temp_new(); |
5064 | gen_addr_reg_index(ctx, t0); |
5065 | tcg_gen_qemu_st_tl(cpu_gpr[rD(ctx->opcode)], t0, ctx->mem_idx, |
5066 | DEF_MEMOP(MO_UL | MO_ALIGN)); |
5067 | tcg_temp_free(t0); |
5068 | } |
5069 | |
5070 | /* PowerPC 601 specific instructions */ |
5071 | |
5072 | /* abs - abs. */ |
5073 | static void gen_abs(DisasContext *ctx) |
5074 | { |
5075 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5076 | TCGv a = cpu_gpr[rA(ctx->opcode)]; |
5077 | |
5078 | tcg_gen_abs_tl(d, a); |
5079 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5080 | gen_set_Rc0(ctx, d); |
5081 | } |
5082 | } |
5083 | |
5084 | /* abso - abso. */ |
5085 | static void gen_abso(DisasContext *ctx) |
5086 | { |
5087 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5088 | TCGv a = cpu_gpr[rA(ctx->opcode)]; |
5089 | |
5090 | tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_ov, a, 0x80000000); |
5091 | tcg_gen_abs_tl(d, a); |
5092 | tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov); |
5093 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5094 | gen_set_Rc0(ctx, d); |
5095 | } |
5096 | } |
5097 | |
5098 | /* clcs */ |
5099 | static void gen_clcs(DisasContext *ctx) |
5100 | { |
5101 | TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode)); |
5102 | gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
5103 | tcg_temp_free_i32(t0); |
5104 | /* Rc=1 sets CR0 to an undefined state */ |
5105 | } |
5106 | |
5107 | /* div - div. */ |
5108 | static void gen_div(DisasContext *ctx) |
5109 | { |
5110 | gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5111 | cpu_gpr[rB(ctx->opcode)]); |
5112 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5113 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5114 | } |
5115 | } |
5116 | |
5117 | /* divo - divo. */ |
5118 | static void gen_divo(DisasContext *ctx) |
5119 | { |
5120 | gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5121 | cpu_gpr[rB(ctx->opcode)]); |
5122 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5123 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5124 | } |
5125 | } |
5126 | |
5127 | /* divs - divs. */ |
5128 | static void gen_divs(DisasContext *ctx) |
5129 | { |
5130 | gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)], |
5131 | cpu_gpr[rB(ctx->opcode)]); |
5132 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5133 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5134 | } |
5135 | } |
5136 | |
5137 | /* divso - divso. */ |
5138 | static void gen_divso(DisasContext *ctx) |
5139 | { |
5140 | gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env, |
5141 | cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
5142 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5143 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5144 | } |
5145 | } |
5146 | |
5147 | /* doz - doz. */ |
5148 | static void gen_doz(DisasContext *ctx) |
5149 | { |
5150 | TCGLabel *l1 = gen_new_label(); |
5151 | TCGLabel *l2 = gen_new_label(); |
5152 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], |
5153 | cpu_gpr[rA(ctx->opcode)], l1); |
5154 | tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], |
5155 | cpu_gpr[rA(ctx->opcode)]); |
5156 | tcg_gen_br(l2); |
5157 | gen_set_label(l1); |
5158 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
5159 | gen_set_label(l2); |
5160 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5161 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5162 | } |
5163 | } |
5164 | |
5165 | /* dozo - dozo. */ |
5166 | static void gen_dozo(DisasContext *ctx) |
5167 | { |
5168 | TCGLabel *l1 = gen_new_label(); |
5169 | TCGLabel *l2 = gen_new_label(); |
5170 | TCGv t0 = tcg_temp_new(); |
5171 | TCGv t1 = tcg_temp_new(); |
5172 | TCGv t2 = tcg_temp_new(); |
5173 | /* Start with XER OV disabled, the most likely case */ |
5174 | tcg_gen_movi_tl(cpu_ov, 0); |
5175 | tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], |
5176 | cpu_gpr[rA(ctx->opcode)], l1); |
5177 | tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5178 | tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5179 | tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0); |
5180 | tcg_gen_andc_tl(t1, t1, t2); |
5181 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0); |
5182 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5183 | tcg_gen_movi_tl(cpu_ov, 1); |
5184 | tcg_gen_movi_tl(cpu_so, 1); |
5185 | tcg_gen_br(l2); |
5186 | gen_set_label(l1); |
5187 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
5188 | gen_set_label(l2); |
5189 | tcg_temp_free(t0); |
5190 | tcg_temp_free(t1); |
5191 | tcg_temp_free(t2); |
5192 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5193 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5194 | } |
5195 | } |
5196 | |
5197 | /* dozi */ |
5198 | static void gen_dozi(DisasContext *ctx) |
5199 | { |
5200 | target_long simm = SIMM(ctx->opcode); |
5201 | TCGLabel *l1 = gen_new_label(); |
5202 | TCGLabel *l2 = gen_new_label(); |
5203 | tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1); |
5204 | tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]); |
5205 | tcg_gen_br(l2); |
5206 | gen_set_label(l1); |
5207 | tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0); |
5208 | gen_set_label(l2); |
5209 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5210 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5211 | } |
5212 | } |
5213 | |
5214 | /* lscbx - lscbx. */ |
5215 | static void gen_lscbx(DisasContext *ctx) |
5216 | { |
5217 | TCGv t0 = tcg_temp_new(); |
5218 | TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode)); |
5219 | TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode)); |
5220 | TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode)); |
5221 | |
5222 | gen_addr_reg_index(ctx, t0); |
5223 | gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3); |
5224 | tcg_temp_free_i32(t1); |
5225 | tcg_temp_free_i32(t2); |
5226 | tcg_temp_free_i32(t3); |
5227 | tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F); |
5228 | tcg_gen_or_tl(cpu_xer, cpu_xer, t0); |
5229 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5230 | gen_set_Rc0(ctx, t0); |
5231 | } |
5232 | tcg_temp_free(t0); |
5233 | } |
5234 | |
5235 | /* maskg - maskg. */ |
5236 | static void gen_maskg(DisasContext *ctx) |
5237 | { |
5238 | TCGLabel *l1 = gen_new_label(); |
5239 | TCGv t0 = tcg_temp_new(); |
5240 | TCGv t1 = tcg_temp_new(); |
5241 | TCGv t2 = tcg_temp_new(); |
5242 | TCGv t3 = tcg_temp_new(); |
5243 | tcg_gen_movi_tl(t3, 0xFFFFFFFF); |
5244 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5245 | tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F); |
5246 | tcg_gen_addi_tl(t2, t0, 1); |
5247 | tcg_gen_shr_tl(t2, t3, t2); |
5248 | tcg_gen_shr_tl(t3, t3, t1); |
5249 | tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3); |
5250 | tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1); |
5251 | tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5252 | gen_set_label(l1); |
5253 | tcg_temp_free(t0); |
5254 | tcg_temp_free(t1); |
5255 | tcg_temp_free(t2); |
5256 | tcg_temp_free(t3); |
5257 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5258 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5259 | } |
5260 | } |
5261 | |
5262 | /* maskir - maskir. */ |
5263 | static void gen_maskir(DisasContext *ctx) |
5264 | { |
5265 | TCGv t0 = tcg_temp_new(); |
5266 | TCGv t1 = tcg_temp_new(); |
5267 | tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
5268 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
5269 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5270 | tcg_temp_free(t0); |
5271 | tcg_temp_free(t1); |
5272 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5273 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5274 | } |
5275 | } |
5276 | |
5277 | /* mul - mul. */ |
5278 | static void gen_mul(DisasContext *ctx) |
5279 | { |
5280 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5281 | TCGv_i64 t1 = tcg_temp_new_i64(); |
5282 | TCGv t2 = tcg_temp_new(); |
5283 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5284 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
5285 | tcg_gen_mul_i64(t0, t0, t1); |
5286 | tcg_gen_trunc_i64_tl(t2, t0); |
5287 | gen_store_spr(SPR_MQ, t2); |
5288 | tcg_gen_shri_i64(t1, t0, 32); |
5289 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
5290 | tcg_temp_free_i64(t0); |
5291 | tcg_temp_free_i64(t1); |
5292 | tcg_temp_free(t2); |
5293 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5294 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5295 | } |
5296 | } |
5297 | |
5298 | /* mulo - mulo. */ |
5299 | static void gen_mulo(DisasContext *ctx) |
5300 | { |
5301 | TCGLabel *l1 = gen_new_label(); |
5302 | TCGv_i64 t0 = tcg_temp_new_i64(); |
5303 | TCGv_i64 t1 = tcg_temp_new_i64(); |
5304 | TCGv t2 = tcg_temp_new(); |
5305 | /* Start with XER OV disabled, the most likely case */ |
5306 | tcg_gen_movi_tl(cpu_ov, 0); |
5307 | tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]); |
5308 | tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]); |
5309 | tcg_gen_mul_i64(t0, t0, t1); |
5310 | tcg_gen_trunc_i64_tl(t2, t0); |
5311 | gen_store_spr(SPR_MQ, t2); |
5312 | tcg_gen_shri_i64(t1, t0, 32); |
5313 | tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1); |
5314 | tcg_gen_ext32s_i64(t1, t0); |
5315 | tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1); |
5316 | tcg_gen_movi_tl(cpu_ov, 1); |
5317 | tcg_gen_movi_tl(cpu_so, 1); |
5318 | gen_set_label(l1); |
5319 | tcg_temp_free_i64(t0); |
5320 | tcg_temp_free_i64(t1); |
5321 | tcg_temp_free(t2); |
5322 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5323 | gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); |
5324 | } |
5325 | } |
5326 | |
5327 | /* nabs - nabs. */ |
5328 | static void gen_nabs(DisasContext *ctx) |
5329 | { |
5330 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5331 | TCGv a = cpu_gpr[rA(ctx->opcode)]; |
5332 | |
5333 | tcg_gen_abs_tl(d, a); |
5334 | tcg_gen_neg_tl(d, d); |
5335 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5336 | gen_set_Rc0(ctx, d); |
5337 | } |
5338 | } |
5339 | |
5340 | /* nabso - nabso. */ |
5341 | static void gen_nabso(DisasContext *ctx) |
5342 | { |
5343 | TCGv d = cpu_gpr[rD(ctx->opcode)]; |
5344 | TCGv a = cpu_gpr[rA(ctx->opcode)]; |
5345 | |
5346 | tcg_gen_abs_tl(d, a); |
5347 | tcg_gen_neg_tl(d, d); |
5348 | /* nabs never overflows */ |
5349 | tcg_gen_movi_tl(cpu_ov, 0); |
5350 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5351 | gen_set_Rc0(ctx, d); |
5352 | } |
5353 | } |
5354 | |
5355 | /* rlmi - rlmi. */ |
5356 | static void gen_rlmi(DisasContext *ctx) |
5357 | { |
5358 | uint32_t mb = MB(ctx->opcode); |
5359 | uint32_t me = ME(ctx->opcode); |
5360 | TCGv t0 = tcg_temp_new(); |
5361 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5362 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5363 | tcg_gen_andi_tl(t0, t0, MASK(mb, me)); |
5364 | tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], |
5365 | ~MASK(mb, me)); |
5366 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0); |
5367 | tcg_temp_free(t0); |
5368 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5369 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5370 | } |
5371 | } |
5372 | |
5373 | /* rrib - rrib. */ |
5374 | static void gen_rrib(DisasContext *ctx) |
5375 | { |
5376 | TCGv t0 = tcg_temp_new(); |
5377 | TCGv t1 = tcg_temp_new(); |
5378 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5379 | tcg_gen_movi_tl(t1, 0x80000000); |
5380 | tcg_gen_shr_tl(t1, t1, t0); |
5381 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5382 | tcg_gen_and_tl(t0, t0, t1); |
5383 | tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1); |
5384 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5385 | tcg_temp_free(t0); |
5386 | tcg_temp_free(t1); |
5387 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5388 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5389 | } |
5390 | } |
5391 | |
5392 | /* sle - sle. */ |
5393 | static void gen_sle(DisasContext *ctx) |
5394 | { |
5395 | TCGv t0 = tcg_temp_new(); |
5396 | TCGv t1 = tcg_temp_new(); |
5397 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5398 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5399 | tcg_gen_subfi_tl(t1, 32, t1); |
5400 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5401 | tcg_gen_or_tl(t1, t0, t1); |
5402 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5403 | gen_store_spr(SPR_MQ, t1); |
5404 | tcg_temp_free(t0); |
5405 | tcg_temp_free(t1); |
5406 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5407 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5408 | } |
5409 | } |
5410 | |
5411 | /* sleq - sleq. */ |
5412 | static void gen_sleq(DisasContext *ctx) |
5413 | { |
5414 | TCGv t0 = tcg_temp_new(); |
5415 | TCGv t1 = tcg_temp_new(); |
5416 | TCGv t2 = tcg_temp_new(); |
5417 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5418 | tcg_gen_movi_tl(t2, 0xFFFFFFFF); |
5419 | tcg_gen_shl_tl(t2, t2, t0); |
5420 | tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5421 | gen_load_spr(t1, SPR_MQ); |
5422 | gen_store_spr(SPR_MQ, t0); |
5423 | tcg_gen_and_tl(t0, t0, t2); |
5424 | tcg_gen_andc_tl(t1, t1, t2); |
5425 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5426 | tcg_temp_free(t0); |
5427 | tcg_temp_free(t1); |
5428 | tcg_temp_free(t2); |
5429 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5430 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5431 | } |
5432 | } |
5433 | |
5434 | /* sliq - sliq. */ |
5435 | static void gen_sliq(DisasContext *ctx) |
5436 | { |
5437 | int sh = SH(ctx->opcode); |
5438 | TCGv t0 = tcg_temp_new(); |
5439 | TCGv t1 = tcg_temp_new(); |
5440 | tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5441 | tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); |
5442 | tcg_gen_or_tl(t1, t0, t1); |
5443 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5444 | gen_store_spr(SPR_MQ, t1); |
5445 | tcg_temp_free(t0); |
5446 | tcg_temp_free(t1); |
5447 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5448 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5449 | } |
5450 | } |
5451 | |
5452 | /* slliq - slliq. */ |
5453 | static void gen_slliq(DisasContext *ctx) |
5454 | { |
5455 | int sh = SH(ctx->opcode); |
5456 | TCGv t0 = tcg_temp_new(); |
5457 | TCGv t1 = tcg_temp_new(); |
5458 | tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5459 | gen_load_spr(t1, SPR_MQ); |
5460 | gen_store_spr(SPR_MQ, t0); |
5461 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh)); |
5462 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh)); |
5463 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5464 | tcg_temp_free(t0); |
5465 | tcg_temp_free(t1); |
5466 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5467 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5468 | } |
5469 | } |
5470 | |
5471 | /* sllq - sllq. */ |
5472 | static void gen_sllq(DisasContext *ctx) |
5473 | { |
5474 | TCGLabel *l1 = gen_new_label(); |
5475 | TCGLabel *l2 = gen_new_label(); |
5476 | TCGv t0 = tcg_temp_local_new(); |
5477 | TCGv t1 = tcg_temp_local_new(); |
5478 | TCGv t2 = tcg_temp_local_new(); |
5479 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5480 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); |
5481 | tcg_gen_shl_tl(t1, t1, t2); |
5482 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); |
5483 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
5484 | gen_load_spr(t0, SPR_MQ); |
5485 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5486 | tcg_gen_br(l2); |
5487 | gen_set_label(l1); |
5488 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5489 | gen_load_spr(t2, SPR_MQ); |
5490 | tcg_gen_andc_tl(t1, t2, t1); |
5491 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5492 | gen_set_label(l2); |
5493 | tcg_temp_free(t0); |
5494 | tcg_temp_free(t1); |
5495 | tcg_temp_free(t2); |
5496 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5497 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5498 | } |
5499 | } |
5500 | |
5501 | /* slq - slq. */ |
5502 | static void gen_slq(DisasContext *ctx) |
5503 | { |
5504 | TCGLabel *l1 = gen_new_label(); |
5505 | TCGv t0 = tcg_temp_new(); |
5506 | TCGv t1 = tcg_temp_new(); |
5507 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5508 | tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5509 | tcg_gen_subfi_tl(t1, 32, t1); |
5510 | tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5511 | tcg_gen_or_tl(t1, t0, t1); |
5512 | gen_store_spr(SPR_MQ, t1); |
5513 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); |
5514 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5515 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5516 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
5517 | gen_set_label(l1); |
5518 | tcg_temp_free(t0); |
5519 | tcg_temp_free(t1); |
5520 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5521 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5522 | } |
5523 | } |
5524 | |
5525 | /* sraiq - sraiq. */ |
5526 | static void gen_sraiq(DisasContext *ctx) |
5527 | { |
5528 | int sh = SH(ctx->opcode); |
5529 | TCGLabel *l1 = gen_new_label(); |
5530 | TCGv t0 = tcg_temp_new(); |
5531 | TCGv t1 = tcg_temp_new(); |
5532 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5533 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); |
5534 | tcg_gen_or_tl(t0, t0, t1); |
5535 | gen_store_spr(SPR_MQ, t0); |
5536 | tcg_gen_movi_tl(cpu_ca, 0); |
5537 | tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); |
5538 | tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1); |
5539 | tcg_gen_movi_tl(cpu_ca, 1); |
5540 | gen_set_label(l1); |
5541 | tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh); |
5542 | tcg_temp_free(t0); |
5543 | tcg_temp_free(t1); |
5544 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5545 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5546 | } |
5547 | } |
5548 | |
5549 | /* sraq - sraq. */ |
5550 | static void gen_sraq(DisasContext *ctx) |
5551 | { |
5552 | TCGLabel *l1 = gen_new_label(); |
5553 | TCGLabel *l2 = gen_new_label(); |
5554 | TCGv t0 = tcg_temp_new(); |
5555 | TCGv t1 = tcg_temp_local_new(); |
5556 | TCGv t2 = tcg_temp_local_new(); |
5557 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5558 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5559 | tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2); |
5560 | tcg_gen_subfi_tl(t2, 32, t2); |
5561 | tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2); |
5562 | tcg_gen_or_tl(t0, t0, t2); |
5563 | gen_store_spr(SPR_MQ, t0); |
5564 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); |
5565 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1); |
5566 | tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]); |
5567 | tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31); |
5568 | gen_set_label(l1); |
5569 | tcg_temp_free(t0); |
5570 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1); |
5571 | tcg_gen_movi_tl(cpu_ca, 0); |
5572 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2); |
5573 | tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2); |
5574 | tcg_gen_movi_tl(cpu_ca, 1); |
5575 | gen_set_label(l2); |
5576 | tcg_temp_free(t1); |
5577 | tcg_temp_free(t2); |
5578 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5579 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5580 | } |
5581 | } |
5582 | |
5583 | /* sre - sre. */ |
5584 | static void gen_sre(DisasContext *ctx) |
5585 | { |
5586 | TCGv t0 = tcg_temp_new(); |
5587 | TCGv t1 = tcg_temp_new(); |
5588 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5589 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5590 | tcg_gen_subfi_tl(t1, 32, t1); |
5591 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5592 | tcg_gen_or_tl(t1, t0, t1); |
5593 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5594 | gen_store_spr(SPR_MQ, t1); |
5595 | tcg_temp_free(t0); |
5596 | tcg_temp_free(t1); |
5597 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5598 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5599 | } |
5600 | } |
5601 | |
5602 | /* srea - srea. */ |
5603 | static void gen_srea(DisasContext *ctx) |
5604 | { |
5605 | TCGv t0 = tcg_temp_new(); |
5606 | TCGv t1 = tcg_temp_new(); |
5607 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5608 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5609 | gen_store_spr(SPR_MQ, t0); |
5610 | tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1); |
5611 | tcg_temp_free(t0); |
5612 | tcg_temp_free(t1); |
5613 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5614 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5615 | } |
5616 | } |
5617 | |
5618 | /* sreq */ |
5619 | static void gen_sreq(DisasContext *ctx) |
5620 | { |
5621 | TCGv t0 = tcg_temp_new(); |
5622 | TCGv t1 = tcg_temp_new(); |
5623 | TCGv t2 = tcg_temp_new(); |
5624 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5625 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); |
5626 | tcg_gen_shr_tl(t1, t1, t0); |
5627 | tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0); |
5628 | gen_load_spr(t2, SPR_MQ); |
5629 | gen_store_spr(SPR_MQ, t0); |
5630 | tcg_gen_and_tl(t0, t0, t1); |
5631 | tcg_gen_andc_tl(t2, t2, t1); |
5632 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
5633 | tcg_temp_free(t0); |
5634 | tcg_temp_free(t1); |
5635 | tcg_temp_free(t2); |
5636 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5637 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5638 | } |
5639 | } |
5640 | |
5641 | /* sriq */ |
5642 | static void gen_sriq(DisasContext *ctx) |
5643 | { |
5644 | int sh = SH(ctx->opcode); |
5645 | TCGv t0 = tcg_temp_new(); |
5646 | TCGv t1 = tcg_temp_new(); |
5647 | tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5648 | tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh); |
5649 | tcg_gen_or_tl(t1, t0, t1); |
5650 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5651 | gen_store_spr(SPR_MQ, t1); |
5652 | tcg_temp_free(t0); |
5653 | tcg_temp_free(t1); |
5654 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5655 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5656 | } |
5657 | } |
5658 | |
5659 | /* srliq */ |
5660 | static void gen_srliq(DisasContext *ctx) |
5661 | { |
5662 | int sh = SH(ctx->opcode); |
5663 | TCGv t0 = tcg_temp_new(); |
5664 | TCGv t1 = tcg_temp_new(); |
5665 | tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh); |
5666 | gen_load_spr(t1, SPR_MQ); |
5667 | gen_store_spr(SPR_MQ, t0); |
5668 | tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh)); |
5669 | tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh)); |
5670 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5671 | tcg_temp_free(t0); |
5672 | tcg_temp_free(t1); |
5673 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5674 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5675 | } |
5676 | } |
5677 | |
5678 | /* srlq */ |
5679 | static void gen_srlq(DisasContext *ctx) |
5680 | { |
5681 | TCGLabel *l1 = gen_new_label(); |
5682 | TCGLabel *l2 = gen_new_label(); |
5683 | TCGv t0 = tcg_temp_local_new(); |
5684 | TCGv t1 = tcg_temp_local_new(); |
5685 | TCGv t2 = tcg_temp_local_new(); |
5686 | tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5687 | tcg_gen_movi_tl(t1, 0xFFFFFFFF); |
5688 | tcg_gen_shr_tl(t2, t1, t2); |
5689 | tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20); |
5690 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
5691 | gen_load_spr(t0, SPR_MQ); |
5692 | tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2); |
5693 | tcg_gen_br(l2); |
5694 | gen_set_label(l1); |
5695 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2); |
5696 | tcg_gen_and_tl(t0, t0, t2); |
5697 | gen_load_spr(t1, SPR_MQ); |
5698 | tcg_gen_andc_tl(t1, t1, t2); |
5699 | tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1); |
5700 | gen_set_label(l2); |
5701 | tcg_temp_free(t0); |
5702 | tcg_temp_free(t1); |
5703 | tcg_temp_free(t2); |
5704 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5705 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5706 | } |
5707 | } |
5708 | |
5709 | /* srq */ |
5710 | static void gen_srq(DisasContext *ctx) |
5711 | { |
5712 | TCGLabel *l1 = gen_new_label(); |
5713 | TCGv t0 = tcg_temp_new(); |
5714 | TCGv t1 = tcg_temp_new(); |
5715 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F); |
5716 | tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1); |
5717 | tcg_gen_subfi_tl(t1, 32, t1); |
5718 | tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1); |
5719 | tcg_gen_or_tl(t1, t0, t1); |
5720 | gen_store_spr(SPR_MQ, t1); |
5721 | tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20); |
5722 | tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0); |
5723 | tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1); |
5724 | tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0); |
5725 | gen_set_label(l1); |
5726 | tcg_temp_free(t0); |
5727 | tcg_temp_free(t1); |
5728 | if (unlikely(Rc(ctx->opcode) != 0)) { |
5729 | gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); |
5730 | } |
5731 | } |
5732 | |
5733 | /* PowerPC 602 specific instructions */ |
5734 | |
5735 | /* dsa */ |
5736 | static void gen_dsa(DisasContext *ctx) |
5737 | { |
5738 | /* XXX: TODO */ |
5739 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5740 | } |
5741 | |
5742 | /* esa */ |
5743 | static void gen_esa(DisasContext *ctx) |
5744 | { |
5745 | /* XXX: TODO */ |
5746 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5747 | } |
5748 | |
5749 | /* mfrom */ |
5750 | static void gen_mfrom(DisasContext *ctx) |
5751 | { |
5752 | #if defined(CONFIG_USER_ONLY) |
5753 | GEN_PRIV; |
5754 | #else |
5755 | CHK_SV; |
5756 | gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); |
5757 | #endif /* defined(CONFIG_USER_ONLY) */ |
5758 | } |
5759 | |
5760 | /* 602 - 603 - G2 TLB management */ |
5761 | |
5762 | /* tlbld */ |
5763 | static void gen_tlbld_6xx(DisasContext *ctx) |
5764 | { |
5765 | #if defined(CONFIG_USER_ONLY) |
5766 | GEN_PRIV; |
5767 | #else |
5768 | CHK_SV; |
5769 | gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5770 | #endif /* defined(CONFIG_USER_ONLY) */ |
5771 | } |
5772 | |
5773 | /* tlbli */ |
5774 | static void gen_tlbli_6xx(DisasContext *ctx) |
5775 | { |
5776 | #if defined(CONFIG_USER_ONLY) |
5777 | GEN_PRIV; |
5778 | #else |
5779 | CHK_SV; |
5780 | gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5781 | #endif /* defined(CONFIG_USER_ONLY) */ |
5782 | } |
5783 | |
5784 | /* 74xx TLB management */ |
5785 | |
5786 | /* tlbld */ |
5787 | static void gen_tlbld_74xx(DisasContext *ctx) |
5788 | { |
5789 | #if defined(CONFIG_USER_ONLY) |
5790 | GEN_PRIV; |
5791 | #else |
5792 | CHK_SV; |
5793 | gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5794 | #endif /* defined(CONFIG_USER_ONLY) */ |
5795 | } |
5796 | |
5797 | /* tlbli */ |
5798 | static void gen_tlbli_74xx(DisasContext *ctx) |
5799 | { |
5800 | #if defined(CONFIG_USER_ONLY) |
5801 | GEN_PRIV; |
5802 | #else |
5803 | CHK_SV; |
5804 | gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5805 | #endif /* defined(CONFIG_USER_ONLY) */ |
5806 | } |
5807 | |
5808 | /* POWER instructions not in PowerPC 601 */ |
5809 | |
5810 | /* clf */ |
5811 | static void gen_clf(DisasContext *ctx) |
5812 | { |
5813 | /* Cache line flush: implemented as no-op */ |
5814 | } |
5815 | |
5816 | /* cli */ |
5817 | static void gen_cli(DisasContext *ctx) |
5818 | { |
5819 | #if defined(CONFIG_USER_ONLY) |
5820 | GEN_PRIV; |
5821 | #else |
5822 | /* Cache line invalidate: privileged and treated as no-op */ |
5823 | CHK_SV; |
5824 | #endif /* defined(CONFIG_USER_ONLY) */ |
5825 | } |
5826 | |
5827 | /* dclst */ |
5828 | static void gen_dclst(DisasContext *ctx) |
5829 | { |
5830 | /* Data cache line store: treated as no-op */ |
5831 | } |
5832 | |
5833 | static void gen_mfsri(DisasContext *ctx) |
5834 | { |
5835 | #if defined(CONFIG_USER_ONLY) |
5836 | GEN_PRIV; |
5837 | #else |
5838 | int ra = rA(ctx->opcode); |
5839 | int rd = rD(ctx->opcode); |
5840 | TCGv t0; |
5841 | |
5842 | CHK_SV; |
5843 | t0 = tcg_temp_new(); |
5844 | gen_addr_reg_index(ctx, t0); |
5845 | tcg_gen_extract_tl(t0, t0, 28, 4); |
5846 | gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); |
5847 | tcg_temp_free(t0); |
5848 | if (ra != 0 && ra != rd) { |
5849 | tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); |
5850 | } |
5851 | #endif /* defined(CONFIG_USER_ONLY) */ |
5852 | } |
5853 | |
5854 | static void gen_rac(DisasContext *ctx) |
5855 | { |
5856 | #if defined(CONFIG_USER_ONLY) |
5857 | GEN_PRIV; |
5858 | #else |
5859 | TCGv t0; |
5860 | |
5861 | CHK_SV; |
5862 | t0 = tcg_temp_new(); |
5863 | gen_addr_reg_index(ctx, t0); |
5864 | gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
5865 | tcg_temp_free(t0); |
5866 | #endif /* defined(CONFIG_USER_ONLY) */ |
5867 | } |
5868 | |
5869 | static void gen_rfsvc(DisasContext *ctx) |
5870 | { |
5871 | #if defined(CONFIG_USER_ONLY) |
5872 | GEN_PRIV; |
5873 | #else |
5874 | CHK_SV; |
5875 | |
5876 | gen_helper_rfsvc(cpu_env); |
5877 | gen_sync_exception(ctx); |
5878 | #endif /* defined(CONFIG_USER_ONLY) */ |
5879 | } |
5880 | |
5881 | /* svc is not implemented for now */ |
5882 | |
5883 | /* BookE specific instructions */ |
5884 | |
5885 | /* XXX: not implemented on 440 ? */ |
5886 | static void gen_mfapidi(DisasContext *ctx) |
5887 | { |
5888 | /* XXX: TODO */ |
5889 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
5890 | } |
5891 | |
5892 | /* XXX: not implemented on 440 ? */ |
5893 | static void gen_tlbiva(DisasContext *ctx) |
5894 | { |
5895 | #if defined(CONFIG_USER_ONLY) |
5896 | GEN_PRIV; |
5897 | #else |
5898 | TCGv t0; |
5899 | |
5900 | CHK_SV; |
5901 | t0 = tcg_temp_new(); |
5902 | gen_addr_reg_index(ctx, t0); |
5903 | gen_helper_tlbiva(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
5904 | tcg_temp_free(t0); |
5905 | #endif /* defined(CONFIG_USER_ONLY) */ |
5906 | } |
5907 | |
5908 | /* All 405 MAC instructions are translated here */ |
5909 | static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3, |
5910 | int ra, int rb, int rt, int Rc) |
5911 | { |
5912 | TCGv t0, t1; |
5913 | |
5914 | t0 = tcg_temp_local_new(); |
5915 | t1 = tcg_temp_local_new(); |
5916 | |
5917 | switch (opc3 & 0x0D) { |
5918 | case 0x05: |
5919 | /* macchw - macchw. - macchwo - macchwo. */ |
5920 | /* macchws - macchws. - macchwso - macchwso. */ |
5921 | /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */ |
5922 | /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */ |
5923 | /* mulchw - mulchw. */ |
5924 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5925 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); |
5926 | tcg_gen_ext16s_tl(t1, t1); |
5927 | break; |
5928 | case 0x04: |
5929 | /* macchwu - macchwu. - macchwuo - macchwuo. */ |
5930 | /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */ |
5931 | /* mulchwu - mulchwu. */ |
5932 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5933 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); |
5934 | tcg_gen_ext16u_tl(t1, t1); |
5935 | break; |
5936 | case 0x01: |
5937 | /* machhw - machhw. - machhwo - machhwo. */ |
5938 | /* machhws - machhws. - machhwso - machhwso. */ |
5939 | /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */ |
5940 | /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */ |
5941 | /* mulhhw - mulhhw. */ |
5942 | tcg_gen_sari_tl(t0, cpu_gpr[ra], 16); |
5943 | tcg_gen_ext16s_tl(t0, t0); |
5944 | tcg_gen_sari_tl(t1, cpu_gpr[rb], 16); |
5945 | tcg_gen_ext16s_tl(t1, t1); |
5946 | break; |
5947 | case 0x00: |
5948 | /* machhwu - machhwu. - machhwuo - machhwuo. */ |
5949 | /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */ |
5950 | /* mulhhwu - mulhhwu. */ |
5951 | tcg_gen_shri_tl(t0, cpu_gpr[ra], 16); |
5952 | tcg_gen_ext16u_tl(t0, t0); |
5953 | tcg_gen_shri_tl(t1, cpu_gpr[rb], 16); |
5954 | tcg_gen_ext16u_tl(t1, t1); |
5955 | break; |
5956 | case 0x0D: |
5957 | /* maclhw - maclhw. - maclhwo - maclhwo. */ |
5958 | /* maclhws - maclhws. - maclhwso - maclhwso. */ |
5959 | /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */ |
5960 | /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */ |
5961 | /* mullhw - mullhw. */ |
5962 | tcg_gen_ext16s_tl(t0, cpu_gpr[ra]); |
5963 | tcg_gen_ext16s_tl(t1, cpu_gpr[rb]); |
5964 | break; |
5965 | case 0x0C: |
5966 | /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */ |
5967 | /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */ |
5968 | /* mullhwu - mullhwu. */ |
5969 | tcg_gen_ext16u_tl(t0, cpu_gpr[ra]); |
5970 | tcg_gen_ext16u_tl(t1, cpu_gpr[rb]); |
5971 | break; |
5972 | } |
5973 | if (opc2 & 0x04) { |
5974 | /* (n)multiply-and-accumulate (0x0C / 0x0E) */ |
5975 | tcg_gen_mul_tl(t1, t0, t1); |
5976 | if (opc2 & 0x02) { |
5977 | /* nmultiply-and-accumulate (0x0E) */ |
5978 | tcg_gen_sub_tl(t0, cpu_gpr[rt], t1); |
5979 | } else { |
5980 | /* multiply-and-accumulate (0x0C) */ |
5981 | tcg_gen_add_tl(t0, cpu_gpr[rt], t1); |
5982 | } |
5983 | |
5984 | if (opc3 & 0x12) { |
5985 | /* Check overflow and/or saturate */ |
5986 | TCGLabel *l1 = gen_new_label(); |
5987 | |
5988 | if (opc3 & 0x10) { |
5989 | /* Start with XER OV disabled, the most likely case */ |
5990 | tcg_gen_movi_tl(cpu_ov, 0); |
5991 | } |
5992 | if (opc3 & 0x01) { |
5993 | /* Signed */ |
5994 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t1); |
5995 | tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); |
5996 | tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); |
5997 | tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); |
5998 | if (opc3 & 0x02) { |
5999 | /* Saturate */ |
6000 | tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); |
6001 | tcg_gen_xori_tl(t0, t0, 0x7fffffff); |
6002 | } |
6003 | } else { |
6004 | /* Unsigned */ |
6005 | tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); |
6006 | if (opc3 & 0x02) { |
6007 | /* Saturate */ |
6008 | tcg_gen_movi_tl(t0, UINT32_MAX); |
6009 | } |
6010 | } |
6011 | if (opc3 & 0x10) { |
6012 | /* Check overflow */ |
6013 | tcg_gen_movi_tl(cpu_ov, 1); |
6014 | tcg_gen_movi_tl(cpu_so, 1); |
6015 | } |
6016 | gen_set_label(l1); |
6017 | tcg_gen_mov_tl(cpu_gpr[rt], t0); |
6018 | } |
6019 | } else { |
6020 | tcg_gen_mul_tl(cpu_gpr[rt], t0, t1); |
6021 | } |
6022 | tcg_temp_free(t0); |
6023 | tcg_temp_free(t1); |
6024 | if (unlikely(Rc) != 0) { |
6025 | /* Update Rc0 */ |
6026 | gen_set_Rc0(ctx, cpu_gpr[rt]); |
6027 | } |
6028 | } |
6029 | |
6030 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
6031 | static void glue(gen_, name)(DisasContext *ctx) \ |
6032 | { \ |
6033 | gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \ |
6034 | rD(ctx->opcode), Rc(ctx->opcode)); \ |
6035 | } |
6036 | |
6037 | /* macchw - macchw. */ |
6038 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05); |
6039 | /* macchwo - macchwo. */ |
6040 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15); |
6041 | /* macchws - macchws. */ |
6042 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07); |
6043 | /* macchwso - macchwso. */ |
6044 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17); |
6045 | /* macchwsu - macchwsu. */ |
6046 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06); |
6047 | /* macchwsuo - macchwsuo. */ |
6048 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16); |
6049 | /* macchwu - macchwu. */ |
6050 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04); |
6051 | /* macchwuo - macchwuo. */ |
6052 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14); |
6053 | /* machhw - machhw. */ |
6054 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01); |
6055 | /* machhwo - machhwo. */ |
6056 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11); |
6057 | /* machhws - machhws. */ |
6058 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03); |
6059 | /* machhwso - machhwso. */ |
6060 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13); |
6061 | /* machhwsu - machhwsu. */ |
6062 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02); |
6063 | /* machhwsuo - machhwsuo. */ |
6064 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12); |
6065 | /* machhwu - machhwu. */ |
6066 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00); |
6067 | /* machhwuo - machhwuo. */ |
6068 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10); |
6069 | /* maclhw - maclhw. */ |
6070 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D); |
6071 | /* maclhwo - maclhwo. */ |
6072 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D); |
6073 | /* maclhws - maclhws. */ |
6074 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F); |
6075 | /* maclhwso - maclhwso. */ |
6076 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F); |
6077 | /* maclhwu - maclhwu. */ |
6078 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C); |
6079 | /* maclhwuo - maclhwuo. */ |
6080 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C); |
6081 | /* maclhwsu - maclhwsu. */ |
6082 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E); |
6083 | /* maclhwsuo - maclhwsuo. */ |
6084 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E); |
6085 | /* nmacchw - nmacchw. */ |
6086 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05); |
6087 | /* nmacchwo - nmacchwo. */ |
6088 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15); |
6089 | /* nmacchws - nmacchws. */ |
6090 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07); |
6091 | /* nmacchwso - nmacchwso. */ |
6092 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17); |
6093 | /* nmachhw - nmachhw. */ |
6094 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01); |
6095 | /* nmachhwo - nmachhwo. */ |
6096 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11); |
6097 | /* nmachhws - nmachhws. */ |
6098 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03); |
6099 | /* nmachhwso - nmachhwso. */ |
6100 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13); |
6101 | /* nmaclhw - nmaclhw. */ |
6102 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D); |
6103 | /* nmaclhwo - nmaclhwo. */ |
6104 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D); |
6105 | /* nmaclhws - nmaclhws. */ |
6106 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F); |
6107 | /* nmaclhwso - nmaclhwso. */ |
6108 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F); |
6109 | |
6110 | /* mulchw - mulchw. */ |
6111 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05); |
6112 | /* mulchwu - mulchwu. */ |
6113 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04); |
6114 | /* mulhhw - mulhhw. */ |
6115 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01); |
6116 | /* mulhhwu - mulhhwu. */ |
6117 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00); |
6118 | /* mullhw - mullhw. */ |
6119 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D); |
6120 | /* mullhwu - mullhwu. */ |
6121 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C); |
6122 | |
6123 | /* mfdcr */ |
6124 | static void gen_mfdcr(DisasContext *ctx) |
6125 | { |
6126 | #if defined(CONFIG_USER_ONLY) |
6127 | GEN_PRIV; |
6128 | #else |
6129 | TCGv dcrn; |
6130 | |
6131 | CHK_SV; |
6132 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
6133 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn); |
6134 | tcg_temp_free(dcrn); |
6135 | #endif /* defined(CONFIG_USER_ONLY) */ |
6136 | } |
6137 | |
6138 | /* mtdcr */ |
6139 | static void gen_mtdcr(DisasContext *ctx) |
6140 | { |
6141 | #if defined(CONFIG_USER_ONLY) |
6142 | GEN_PRIV; |
6143 | #else |
6144 | TCGv dcrn; |
6145 | |
6146 | CHK_SV; |
6147 | dcrn = tcg_const_tl(SPR(ctx->opcode)); |
6148 | gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]); |
6149 | tcg_temp_free(dcrn); |
6150 | #endif /* defined(CONFIG_USER_ONLY) */ |
6151 | } |
6152 | |
6153 | /* mfdcrx */ |
6154 | /* XXX: not implemented on 440 ? */ |
6155 | static void gen_mfdcrx(DisasContext *ctx) |
6156 | { |
6157 | #if defined(CONFIG_USER_ONLY) |
6158 | GEN_PRIV; |
6159 | #else |
6160 | CHK_SV; |
6161 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6162 | cpu_gpr[rA(ctx->opcode)]); |
6163 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6164 | #endif /* defined(CONFIG_USER_ONLY) */ |
6165 | } |
6166 | |
6167 | /* mtdcrx */ |
6168 | /* XXX: not implemented on 440 ? */ |
6169 | static void gen_mtdcrx(DisasContext *ctx) |
6170 | { |
6171 | #if defined(CONFIG_USER_ONLY) |
6172 | GEN_PRIV; |
6173 | #else |
6174 | CHK_SV; |
6175 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6176 | cpu_gpr[rS(ctx->opcode)]); |
6177 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6178 | #endif /* defined(CONFIG_USER_ONLY) */ |
6179 | } |
6180 | |
6181 | /* mfdcrux (PPC 460) : user-mode access to DCR */ |
6182 | static void gen_mfdcrux(DisasContext *ctx) |
6183 | { |
6184 | gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6185 | cpu_gpr[rA(ctx->opcode)]); |
6186 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6187 | } |
6188 | |
6189 | /* mtdcrux (PPC 460) : user-mode access to DCR */ |
6190 | static void gen_mtdcrux(DisasContext *ctx) |
6191 | { |
6192 | gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6193 | cpu_gpr[rS(ctx->opcode)]); |
6194 | /* Note: Rc update flag set leads to undefined state of Rc0 */ |
6195 | } |
6196 | |
6197 | /* dccci */ |
6198 | static void gen_dccci(DisasContext *ctx) |
6199 | { |
6200 | CHK_SV; |
6201 | /* interpreted as no-op */ |
6202 | } |
6203 | |
6204 | /* dcread */ |
6205 | static void gen_dcread(DisasContext *ctx) |
6206 | { |
6207 | #if defined(CONFIG_USER_ONLY) |
6208 | GEN_PRIV; |
6209 | #else |
6210 | TCGv EA, val; |
6211 | |
6212 | CHK_SV; |
6213 | gen_set_access_type(ctx, ACCESS_CACHE); |
6214 | EA = tcg_temp_new(); |
6215 | gen_addr_reg_index(ctx, EA); |
6216 | val = tcg_temp_new(); |
6217 | gen_qemu_ld32u(ctx, val, EA); |
6218 | tcg_temp_free(val); |
6219 | tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA); |
6220 | tcg_temp_free(EA); |
6221 | #endif /* defined(CONFIG_USER_ONLY) */ |
6222 | } |
6223 | |
6224 | /* icbt */ |
6225 | static void gen_icbt_40x(DisasContext *ctx) |
6226 | { |
6227 | /* |
6228 | * interpreted as no-op |
6229 | * XXX: specification say this is treated as a load by the MMU but |
6230 | * does not generate any exception |
6231 | */ |
6232 | } |
6233 | |
6234 | /* iccci */ |
6235 | static void gen_iccci(DisasContext *ctx) |
6236 | { |
6237 | CHK_SV; |
6238 | /* interpreted as no-op */ |
6239 | } |
6240 | |
6241 | /* icread */ |
6242 | static void gen_icread(DisasContext *ctx) |
6243 | { |
6244 | CHK_SV; |
6245 | /* interpreted as no-op */ |
6246 | } |
6247 | |
6248 | /* rfci (supervisor only) */ |
6249 | static void gen_rfci_40x(DisasContext *ctx) |
6250 | { |
6251 | #if defined(CONFIG_USER_ONLY) |
6252 | GEN_PRIV; |
6253 | #else |
6254 | CHK_SV; |
6255 | /* Restore CPU state */ |
6256 | gen_helper_40x_rfci(cpu_env); |
6257 | gen_sync_exception(ctx); |
6258 | #endif /* defined(CONFIG_USER_ONLY) */ |
6259 | } |
6260 | |
6261 | static void gen_rfci(DisasContext *ctx) |
6262 | { |
6263 | #if defined(CONFIG_USER_ONLY) |
6264 | GEN_PRIV; |
6265 | #else |
6266 | CHK_SV; |
6267 | /* Restore CPU state */ |
6268 | gen_helper_rfci(cpu_env); |
6269 | gen_sync_exception(ctx); |
6270 | #endif /* defined(CONFIG_USER_ONLY) */ |
6271 | } |
6272 | |
6273 | /* BookE specific */ |
6274 | |
6275 | /* XXX: not implemented on 440 ? */ |
6276 | static void gen_rfdi(DisasContext *ctx) |
6277 | { |
6278 | #if defined(CONFIG_USER_ONLY) |
6279 | GEN_PRIV; |
6280 | #else |
6281 | CHK_SV; |
6282 | /* Restore CPU state */ |
6283 | gen_helper_rfdi(cpu_env); |
6284 | gen_sync_exception(ctx); |
6285 | #endif /* defined(CONFIG_USER_ONLY) */ |
6286 | } |
6287 | |
6288 | /* XXX: not implemented on 440 ? */ |
6289 | static void gen_rfmci(DisasContext *ctx) |
6290 | { |
6291 | #if defined(CONFIG_USER_ONLY) |
6292 | GEN_PRIV; |
6293 | #else |
6294 | CHK_SV; |
6295 | /* Restore CPU state */ |
6296 | gen_helper_rfmci(cpu_env); |
6297 | gen_sync_exception(ctx); |
6298 | #endif /* defined(CONFIG_USER_ONLY) */ |
6299 | } |
6300 | |
6301 | /* TLB management - PowerPC 405 implementation */ |
6302 | |
6303 | /* tlbre */ |
6304 | static void gen_tlbre_40x(DisasContext *ctx) |
6305 | { |
6306 | #if defined(CONFIG_USER_ONLY) |
6307 | GEN_PRIV; |
6308 | #else |
6309 | CHK_SV; |
6310 | switch (rB(ctx->opcode)) { |
6311 | case 0: |
6312 | gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6313 | cpu_gpr[rA(ctx->opcode)]); |
6314 | break; |
6315 | case 1: |
6316 | gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6317 | cpu_gpr[rA(ctx->opcode)]); |
6318 | break; |
6319 | default: |
6320 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6321 | break; |
6322 | } |
6323 | #endif /* defined(CONFIG_USER_ONLY) */ |
6324 | } |
6325 | |
6326 | /* tlbsx - tlbsx. */ |
6327 | static void gen_tlbsx_40x(DisasContext *ctx) |
6328 | { |
6329 | #if defined(CONFIG_USER_ONLY) |
6330 | GEN_PRIV; |
6331 | #else |
6332 | TCGv t0; |
6333 | |
6334 | CHK_SV; |
6335 | t0 = tcg_temp_new(); |
6336 | gen_addr_reg_index(ctx, t0); |
6337 | gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
6338 | tcg_temp_free(t0); |
6339 | if (Rc(ctx->opcode)) { |
6340 | TCGLabel *l1 = gen_new_label(); |
6341 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
6342 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6343 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
6344 | gen_set_label(l1); |
6345 | } |
6346 | #endif /* defined(CONFIG_USER_ONLY) */ |
6347 | } |
6348 | |
6349 | /* tlbwe */ |
6350 | static void gen_tlbwe_40x(DisasContext *ctx) |
6351 | { |
6352 | #if defined(CONFIG_USER_ONLY) |
6353 | GEN_PRIV; |
6354 | #else |
6355 | CHK_SV; |
6356 | |
6357 | switch (rB(ctx->opcode)) { |
6358 | case 0: |
6359 | gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6360 | cpu_gpr[rS(ctx->opcode)]); |
6361 | break; |
6362 | case 1: |
6363 | gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], |
6364 | cpu_gpr[rS(ctx->opcode)]); |
6365 | break; |
6366 | default: |
6367 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6368 | break; |
6369 | } |
6370 | #endif /* defined(CONFIG_USER_ONLY) */ |
6371 | } |
6372 | |
6373 | /* TLB management - PowerPC 440 implementation */ |
6374 | |
6375 | /* tlbre */ |
6376 | static void gen_tlbre_440(DisasContext *ctx) |
6377 | { |
6378 | #if defined(CONFIG_USER_ONLY) |
6379 | GEN_PRIV; |
6380 | #else |
6381 | CHK_SV; |
6382 | |
6383 | switch (rB(ctx->opcode)) { |
6384 | case 0: |
6385 | case 1: |
6386 | case 2: |
6387 | { |
6388 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
6389 | gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, |
6390 | t0, cpu_gpr[rA(ctx->opcode)]); |
6391 | tcg_temp_free_i32(t0); |
6392 | } |
6393 | break; |
6394 | default: |
6395 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6396 | break; |
6397 | } |
6398 | #endif /* defined(CONFIG_USER_ONLY) */ |
6399 | } |
6400 | |
6401 | /* tlbsx - tlbsx. */ |
6402 | static void gen_tlbsx_440(DisasContext *ctx) |
6403 | { |
6404 | #if defined(CONFIG_USER_ONLY) |
6405 | GEN_PRIV; |
6406 | #else |
6407 | TCGv t0; |
6408 | |
6409 | CHK_SV; |
6410 | t0 = tcg_temp_new(); |
6411 | gen_addr_reg_index(ctx, t0); |
6412 | gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); |
6413 | tcg_temp_free(t0); |
6414 | if (Rc(ctx->opcode)) { |
6415 | TCGLabel *l1 = gen_new_label(); |
6416 | tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); |
6417 | tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1); |
6418 | tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02); |
6419 | gen_set_label(l1); |
6420 | } |
6421 | #endif /* defined(CONFIG_USER_ONLY) */ |
6422 | } |
6423 | |
6424 | /* tlbwe */ |
6425 | static void gen_tlbwe_440(DisasContext *ctx) |
6426 | { |
6427 | #if defined(CONFIG_USER_ONLY) |
6428 | GEN_PRIV; |
6429 | #else |
6430 | CHK_SV; |
6431 | switch (rB(ctx->opcode)) { |
6432 | case 0: |
6433 | case 1: |
6434 | case 2: |
6435 | { |
6436 | TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); |
6437 | gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], |
6438 | cpu_gpr[rS(ctx->opcode)]); |
6439 | tcg_temp_free_i32(t0); |
6440 | } |
6441 | break; |
6442 | default: |
6443 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6444 | break; |
6445 | } |
6446 | #endif /* defined(CONFIG_USER_ONLY) */ |
6447 | } |
6448 | |
6449 | /* TLB management - PowerPC BookE 2.06 implementation */ |
6450 | |
6451 | /* tlbre */ |
6452 | static void gen_tlbre_booke206(DisasContext *ctx) |
6453 | { |
6454 | #if defined(CONFIG_USER_ONLY) |
6455 | GEN_PRIV; |
6456 | #else |
6457 | CHK_SV; |
6458 | gen_helper_booke206_tlbre(cpu_env); |
6459 | #endif /* defined(CONFIG_USER_ONLY) */ |
6460 | } |
6461 | |
6462 | /* tlbsx - tlbsx. */ |
6463 | static void gen_tlbsx_booke206(DisasContext *ctx) |
6464 | { |
6465 | #if defined(CONFIG_USER_ONLY) |
6466 | GEN_PRIV; |
6467 | #else |
6468 | TCGv t0; |
6469 | |
6470 | CHK_SV; |
6471 | if (rA(ctx->opcode)) { |
6472 | t0 = tcg_temp_new(); |
6473 | tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]); |
6474 | } else { |
6475 | t0 = tcg_const_tl(0); |
6476 | } |
6477 | |
6478 | tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); |
6479 | gen_helper_booke206_tlbsx(cpu_env, t0); |
6480 | tcg_temp_free(t0); |
6481 | #endif /* defined(CONFIG_USER_ONLY) */ |
6482 | } |
6483 | |
6484 | /* tlbwe */ |
6485 | static void gen_tlbwe_booke206(DisasContext *ctx) |
6486 | { |
6487 | #if defined(CONFIG_USER_ONLY) |
6488 | GEN_PRIV; |
6489 | #else |
6490 | CHK_SV; |
6491 | gen_helper_booke206_tlbwe(cpu_env); |
6492 | #endif /* defined(CONFIG_USER_ONLY) */ |
6493 | } |
6494 | |
6495 | static void gen_tlbivax_booke206(DisasContext *ctx) |
6496 | { |
6497 | #if defined(CONFIG_USER_ONLY) |
6498 | GEN_PRIV; |
6499 | #else |
6500 | TCGv t0; |
6501 | |
6502 | CHK_SV; |
6503 | t0 = tcg_temp_new(); |
6504 | gen_addr_reg_index(ctx, t0); |
6505 | gen_helper_booke206_tlbivax(cpu_env, t0); |
6506 | tcg_temp_free(t0); |
6507 | #endif /* defined(CONFIG_USER_ONLY) */ |
6508 | } |
6509 | |
6510 | static void gen_tlbilx_booke206(DisasContext *ctx) |
6511 | { |
6512 | #if defined(CONFIG_USER_ONLY) |
6513 | GEN_PRIV; |
6514 | #else |
6515 | TCGv t0; |
6516 | |
6517 | CHK_SV; |
6518 | t0 = tcg_temp_new(); |
6519 | gen_addr_reg_index(ctx, t0); |
6520 | |
6521 | switch ((ctx->opcode >> 21) & 0x3) { |
6522 | case 0: |
6523 | gen_helper_booke206_tlbilx0(cpu_env, t0); |
6524 | break; |
6525 | case 1: |
6526 | gen_helper_booke206_tlbilx1(cpu_env, t0); |
6527 | break; |
6528 | case 3: |
6529 | gen_helper_booke206_tlbilx3(cpu_env, t0); |
6530 | break; |
6531 | default: |
6532 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6533 | break; |
6534 | } |
6535 | |
6536 | tcg_temp_free(t0); |
6537 | #endif /* defined(CONFIG_USER_ONLY) */ |
6538 | } |
6539 | |
6540 | |
6541 | /* wrtee */ |
6542 | static void gen_wrtee(DisasContext *ctx) |
6543 | { |
6544 | #if defined(CONFIG_USER_ONLY) |
6545 | GEN_PRIV; |
6546 | #else |
6547 | TCGv t0; |
6548 | |
6549 | CHK_SV; |
6550 | t0 = tcg_temp_new(); |
6551 | tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE)); |
6552 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6553 | tcg_gen_or_tl(cpu_msr, cpu_msr, t0); |
6554 | tcg_temp_free(t0); |
6555 | /* |
6556 | * Stop translation to have a chance to raise an exception if we |
6557 | * just set msr_ee to 1 |
6558 | */ |
6559 | gen_stop_exception(ctx); |
6560 | #endif /* defined(CONFIG_USER_ONLY) */ |
6561 | } |
6562 | |
6563 | /* wrteei */ |
6564 | static void gen_wrteei(DisasContext *ctx) |
6565 | { |
6566 | #if defined(CONFIG_USER_ONLY) |
6567 | GEN_PRIV; |
6568 | #else |
6569 | CHK_SV; |
6570 | if (ctx->opcode & 0x00008000) { |
6571 | tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE)); |
6572 | /* Stop translation to have a chance to raise an exception */ |
6573 | gen_stop_exception(ctx); |
6574 | } else { |
6575 | tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE)); |
6576 | } |
6577 | #endif /* defined(CONFIG_USER_ONLY) */ |
6578 | } |
6579 | |
6580 | /* PowerPC 440 specific instructions */ |
6581 | |
6582 | /* dlmzb */ |
6583 | static void gen_dlmzb(DisasContext *ctx) |
6584 | { |
6585 | TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode)); |
6586 | gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env, |
6587 | cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); |
6588 | tcg_temp_free_i32(t0); |
6589 | } |
6590 | |
6591 | /* mbar replaces eieio on 440 */ |
6592 | static void gen_mbar(DisasContext *ctx) |
6593 | { |
6594 | /* interpreted as no-op */ |
6595 | } |
6596 | |
6597 | /* msync replaces sync on 440 */ |
6598 | static void gen_msync_4xx(DisasContext *ctx) |
6599 | { |
6600 | /* Only e500 seems to treat reserved bits as invalid */ |
6601 | if ((ctx->insns_flags2 & PPC2_BOOKE206) && |
6602 | (ctx->opcode & 0x03FFF801)) { |
6603 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
6604 | } |
6605 | /* otherwise interpreted as no-op */ |
6606 | } |
6607 | |
6608 | /* icbt */ |
6609 | static void gen_icbt_440(DisasContext *ctx) |
6610 | { |
6611 | /* |
6612 | * interpreted as no-op |
6613 | * XXX: specification say this is treated as a load by the MMU but |
6614 | * does not generate any exception |
6615 | */ |
6616 | } |
6617 | |
6618 | /* Embedded.Processor Control */ |
6619 | |
6620 | static void gen_msgclr(DisasContext *ctx) |
6621 | { |
6622 | #if defined(CONFIG_USER_ONLY) |
6623 | GEN_PRIV; |
6624 | #else |
6625 | CHK_HV; |
6626 | if (is_book3s_arch2x(ctx)) { |
6627 | gen_helper_book3s_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
6628 | } else { |
6629 | gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]); |
6630 | } |
6631 | #endif /* defined(CONFIG_USER_ONLY) */ |
6632 | } |
6633 | |
6634 | static void gen_msgsnd(DisasContext *ctx) |
6635 | { |
6636 | #if defined(CONFIG_USER_ONLY) |
6637 | GEN_PRIV; |
6638 | #else |
6639 | CHK_HV; |
6640 | if (is_book3s_arch2x(ctx)) { |
6641 | gen_helper_book3s_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
6642 | } else { |
6643 | gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]); |
6644 | } |
6645 | #endif /* defined(CONFIG_USER_ONLY) */ |
6646 | } |
6647 | |
6648 | static void gen_msgsync(DisasContext *ctx) |
6649 | { |
6650 | #if defined(CONFIG_USER_ONLY) |
6651 | GEN_PRIV; |
6652 | #else |
6653 | CHK_HV; |
6654 | #endif /* defined(CONFIG_USER_ONLY) */ |
6655 | /* interpreted as no-op */ |
6656 | } |
6657 | |
6658 | #if defined(TARGET_PPC64) |
6659 | static void gen_maddld(DisasContext *ctx) |
6660 | { |
6661 | TCGv_i64 t1 = tcg_temp_new_i64(); |
6662 | |
6663 | tcg_gen_mul_i64(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); |
6664 | tcg_gen_add_i64(cpu_gpr[rD(ctx->opcode)], t1, cpu_gpr[rC(ctx->opcode)]); |
6665 | tcg_temp_free_i64(t1); |
6666 | } |
6667 | |
6668 | /* maddhd maddhdu */ |
6669 | static void gen_maddhd_maddhdu(DisasContext *ctx) |
6670 | { |
6671 | TCGv_i64 lo = tcg_temp_new_i64(); |
6672 | TCGv_i64 hi = tcg_temp_new_i64(); |
6673 | TCGv_i64 t1 = tcg_temp_new_i64(); |
6674 | |
6675 | if (Rc(ctx->opcode)) { |
6676 | tcg_gen_mulu2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], |
6677 | cpu_gpr[rB(ctx->opcode)]); |
6678 | tcg_gen_movi_i64(t1, 0); |
6679 | } else { |
6680 | tcg_gen_muls2_i64(lo, hi, cpu_gpr[rA(ctx->opcode)], |
6681 | cpu_gpr[rB(ctx->opcode)]); |
6682 | tcg_gen_sari_i64(t1, cpu_gpr[rC(ctx->opcode)], 63); |
6683 | } |
6684 | tcg_gen_add2_i64(t1, cpu_gpr[rD(ctx->opcode)], lo, hi, |
6685 | cpu_gpr[rC(ctx->opcode)], t1); |
6686 | tcg_temp_free_i64(lo); |
6687 | tcg_temp_free_i64(hi); |
6688 | tcg_temp_free_i64(t1); |
6689 | } |
6690 | #endif /* defined(TARGET_PPC64) */ |
6691 | |
6692 | static void gen_tbegin(DisasContext *ctx) |
6693 | { |
6694 | if (unlikely(!ctx->tm_enabled)) { |
6695 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); |
6696 | return; |
6697 | } |
6698 | gen_helper_tbegin(cpu_env); |
6699 | } |
6700 | |
6701 | #define GEN_TM_NOOP(name) \ |
6702 | static inline void gen_##name(DisasContext *ctx) \ |
6703 | { \ |
6704 | if (unlikely(!ctx->tm_enabled)) { \ |
6705 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ |
6706 | return; \ |
6707 | } \ |
6708 | /* \ |
6709 | * Because tbegin always fails in QEMU, these user \ |
6710 | * space instructions all have a simple implementation: \ |
6711 | * \ |
6712 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ |
6713 | * = 0b0 || 0b00 || 0b0 \ |
6714 | */ \ |
6715 | tcg_gen_movi_i32(cpu_crf[0], 0); \ |
6716 | } |
6717 | |
6718 | GEN_TM_NOOP(tend); |
6719 | GEN_TM_NOOP(tabort); |
6720 | GEN_TM_NOOP(tabortwc); |
6721 | GEN_TM_NOOP(tabortwci); |
6722 | GEN_TM_NOOP(tabortdc); |
6723 | GEN_TM_NOOP(tabortdci); |
6724 | GEN_TM_NOOP(tsr); |
6725 | |
6726 | static inline void gen_cp_abort(DisasContext *ctx) |
6727 | { |
6728 | /* Do Nothing */ |
6729 | } |
6730 | |
6731 | #define GEN_CP_PASTE_NOOP(name) \ |
6732 | static inline void gen_##name(DisasContext *ctx) \ |
6733 | { \ |
6734 | /* \ |
6735 | * Generate invalid exception until we have an \ |
6736 | * implementation of the copy paste facility \ |
6737 | */ \ |
6738 | gen_invalid(ctx); \ |
6739 | } |
6740 | |
6741 | GEN_CP_PASTE_NOOP(copy) |
6742 | GEN_CP_PASTE_NOOP(paste) |
6743 | |
6744 | static void gen_tcheck(DisasContext *ctx) |
6745 | { |
6746 | if (unlikely(!ctx->tm_enabled)) { |
6747 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); |
6748 | return; |
6749 | } |
6750 | /* |
6751 | * Because tbegin always fails, the tcheck implementation is |
6752 | * simple: |
6753 | * |
6754 | * CR[CRF] = TDOOMED || MSR[TS] || 0b0 |
6755 | * = 0b1 || 0b00 || 0b0 |
6756 | */ |
6757 | tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0x8); |
6758 | } |
6759 | |
6760 | #if defined(CONFIG_USER_ONLY) |
6761 | #define GEN_TM_PRIV_NOOP(name) \ |
6762 | static inline void gen_##name(DisasContext *ctx) \ |
6763 | { \ |
6764 | gen_priv_exception(ctx, POWERPC_EXCP_PRIV_OPC); \ |
6765 | } |
6766 | |
6767 | #else |
6768 | |
6769 | #define GEN_TM_PRIV_NOOP(name) \ |
6770 | static inline void gen_##name(DisasContext *ctx) \ |
6771 | { \ |
6772 | CHK_SV; \ |
6773 | if (unlikely(!ctx->tm_enabled)) { \ |
6774 | gen_exception_err(ctx, POWERPC_EXCP_FU, FSCR_IC_TM); \ |
6775 | return; \ |
6776 | } \ |
6777 | /* \ |
6778 | * Because tbegin always fails, the implementation is \ |
6779 | * simple: \ |
6780 | * \ |
6781 | * CR[0] = 0b0 || MSR[TS] || 0b0 \ |
6782 | * = 0b0 || 0b00 | 0b0 \ |
6783 | */ \ |
6784 | tcg_gen_movi_i32(cpu_crf[0], 0); \ |
6785 | } |
6786 | |
6787 | #endif |
6788 | |
6789 | GEN_TM_PRIV_NOOP(treclaim); |
6790 | GEN_TM_PRIV_NOOP(trechkpt); |
6791 | |
6792 | static inline void get_fpr(TCGv_i64 dst, int regno) |
6793 | { |
6794 | tcg_gen_ld_i64(dst, cpu_env, fpr_offset(regno)); |
6795 | } |
6796 | |
6797 | static inline void set_fpr(int regno, TCGv_i64 src) |
6798 | { |
6799 | tcg_gen_st_i64(src, cpu_env, fpr_offset(regno)); |
6800 | } |
6801 | |
6802 | static inline void get_avr64(TCGv_i64 dst, int regno, bool high) |
6803 | { |
6804 | tcg_gen_ld_i64(dst, cpu_env, avr64_offset(regno, high)); |
6805 | } |
6806 | |
6807 | static inline void set_avr64(int regno, TCGv_i64 src, bool high) |
6808 | { |
6809 | tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high)); |
6810 | } |
6811 | |
6812 | #include "translate/fp-impl.inc.c" |
6813 | |
6814 | #include "translate/vmx-impl.inc.c" |
6815 | |
6816 | #include "translate/vsx-impl.inc.c" |
6817 | |
6818 | #include "translate/dfp-impl.inc.c" |
6819 | |
6820 | #include "translate/spe-impl.inc.c" |
6821 | |
6822 | /* Handles lfdp, lxsd, lxssp */ |
6823 | static void gen_dform39(DisasContext *ctx) |
6824 | { |
6825 | switch (ctx->opcode & 0x3) { |
6826 | case 0: /* lfdp */ |
6827 | if (ctx->insns_flags2 & PPC2_ISA205) { |
6828 | return gen_lfdp(ctx); |
6829 | } |
6830 | break; |
6831 | case 2: /* lxsd */ |
6832 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6833 | return gen_lxsd(ctx); |
6834 | } |
6835 | break; |
6836 | case 3: /* lxssp */ |
6837 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6838 | return gen_lxssp(ctx); |
6839 | } |
6840 | break; |
6841 | } |
6842 | return gen_invalid(ctx); |
6843 | } |
6844 | |
6845 | /* handles stfdp, lxv, stxsd, stxssp lxvx */ |
6846 | static void gen_dform3D(DisasContext *ctx) |
6847 | { |
6848 | if ((ctx->opcode & 3) == 1) { /* DQ-FORM */ |
6849 | switch (ctx->opcode & 0x7) { |
6850 | case 1: /* lxv */ |
6851 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6852 | return gen_lxv(ctx); |
6853 | } |
6854 | break; |
6855 | case 5: /* stxv */ |
6856 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6857 | return gen_stxv(ctx); |
6858 | } |
6859 | break; |
6860 | } |
6861 | } else { /* DS-FORM */ |
6862 | switch (ctx->opcode & 0x3) { |
6863 | case 0: /* stfdp */ |
6864 | if (ctx->insns_flags2 & PPC2_ISA205) { |
6865 | return gen_stfdp(ctx); |
6866 | } |
6867 | break; |
6868 | case 2: /* stxsd */ |
6869 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6870 | return gen_stxsd(ctx); |
6871 | } |
6872 | break; |
6873 | case 3: /* stxssp */ |
6874 | if (ctx->insns_flags2 & PPC2_ISA300) { |
6875 | return gen_stxssp(ctx); |
6876 | } |
6877 | break; |
6878 | } |
6879 | } |
6880 | return gen_invalid(ctx); |
6881 | } |
6882 | |
6883 | static opcode_t opcodes[] = { |
6884 | GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE), |
6885 | GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER), |
6886 | GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
6887 | GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400001, PPC_INTEGER), |
6888 | GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER), |
6889 | #if defined(TARGET_PPC64) |
6890 | GEN_HANDLER_E(cmpeqb, 0x1F, 0x00, 0x07, 0x00600000, PPC_NONE, PPC2_ISA300), |
6891 | #endif |
6892 | GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205), |
6893 | GEN_HANDLER_E(cmprb, 0x1F, 0x00, 0x06, 0x00400001, PPC_NONE, PPC2_ISA300), |
6894 | GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL), |
6895 | GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6896 | GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6897 | GEN_HANDLER2(addic_, "addic." , 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6898 | GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6899 | GEN_HANDLER_E(addpcis, 0x13, 0x2, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
6900 | GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER), |
6901 | GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER), |
6902 | GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER), |
6903 | GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER), |
6904 | GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6905 | #if defined(TARGET_PPC64) |
6906 | GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B), |
6907 | #endif |
6908 | GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER), |
6909 | GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER), |
6910 | GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6911 | GEN_HANDLER2(andi_, "andi." , 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6912 | GEN_HANDLER2(andis_, "andis." , 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6913 | GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER), |
6914 | GEN_HANDLER_E(cnttzw, 0x1F, 0x1A, 0x10, 0x00000000, PPC_NONE, PPC2_ISA300), |
6915 | GEN_HANDLER_E(copy, 0x1F, 0x06, 0x18, 0x03C00001, PPC_NONE, PPC2_ISA300), |
6916 | GEN_HANDLER_E(cp_abort, 0x1F, 0x06, 0x1A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
6917 | GEN_HANDLER_E(paste, 0x1F, 0x06, 0x1C, 0x03C00000, PPC_NONE, PPC2_ISA300), |
6918 | GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER), |
6919 | GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER), |
6920 | GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6921 | GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6922 | GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6923 | GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6924 | GEN_HANDLER(popcntb, 0x1F, 0x1A, 0x03, 0x0000F801, PPC_POPCNTB), |
6925 | GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD), |
6926 | GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205), |
6927 | #if defined(TARGET_PPC64) |
6928 | GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD), |
6929 | GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B), |
6930 | GEN_HANDLER_E(cnttzd, 0x1F, 0x1A, 0x11, 0x00000000, PPC_NONE, PPC2_ISA300), |
6931 | GEN_HANDLER_E(darn, 0x1F, 0x13, 0x17, 0x001CF801, PPC_NONE, PPC2_ISA300), |
6932 | GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205), |
6933 | GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206), |
6934 | #endif |
6935 | GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6936 | GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6937 | GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6938 | GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER), |
6939 | GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER), |
6940 | GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER), |
6941 | GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER), |
6942 | #if defined(TARGET_PPC64) |
6943 | GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B), |
6944 | GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B), |
6945 | GEN_HANDLER2(sradi0, "sradi" , 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B), |
6946 | GEN_HANDLER2(sradi1, "sradi" , 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B), |
6947 | GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B), |
6948 | GEN_HANDLER2_E(extswsli0, "extswsli" , 0x1F, 0x1A, 0x1B, 0x00000000, |
6949 | PPC_NONE, PPC2_ISA300), |
6950 | GEN_HANDLER2_E(extswsli1, "extswsli" , 0x1F, 0x1B, 0x1B, 0x00000000, |
6951 | PPC_NONE, PPC2_ISA300), |
6952 | #endif |
6953 | #if defined(TARGET_PPC64) |
6954 | GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B), |
6955 | GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX), |
6956 | GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B), |
6957 | #endif |
6958 | /* handles lfdp, lxsd, lxssp */ |
6959 | GEN_HANDLER_E(dform39, 0x39, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
6960 | /* handles stfdp, lxv, stxsd, stxssp, stxv */ |
6961 | GEN_HANDLER_E(dform3D, 0x3D, 0xFF, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA205), |
6962 | GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6963 | GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER), |
6964 | GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING), |
6965 | GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING), |
6966 | GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING), |
6967 | GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING), |
6968 | GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO), |
6969 | GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM), |
6970 | GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6971 | GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6972 | GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES), |
6973 | GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300), |
6974 | GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300), |
6975 | GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6976 | GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206), |
6977 | GEN_HANDLER2(stwcx_, "stwcx." , 0x1F, 0x16, 0x04, 0x00000000, PPC_RES), |
6978 | #if defined(TARGET_PPC64) |
6979 | GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300), |
6980 | GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300), |
6981 | GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B), |
6982 | GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207), |
6983 | GEN_HANDLER2(stdcx_, "stdcx." , 0x1F, 0x16, 0x06, 0x00000000, PPC_64B), |
6984 | GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207), |
6985 | #endif |
6986 | GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC), |
6987 | GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT), |
6988 | GEN_HANDLER_E(wait, 0x1F, 0x1E, 0x00, 0x039FF801, PPC_NONE, PPC2_ISA300), |
6989 | GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
6990 | GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
6991 | GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW), |
6992 | GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW), |
6993 | GEN_HANDLER_E(bctar, 0x13, 0x10, 0x11, 0x0000E000, PPC_NONE, PPC2_BCTAR_ISA207), |
6994 | GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER), |
6995 | GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW), |
6996 | #if defined(TARGET_PPC64) |
6997 | GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B), |
6998 | GEN_HANDLER_E(stop, 0x13, 0x12, 0x0b, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
6999 | GEN_HANDLER_E(doze, 0x13, 0x12, 0x0c, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
7000 | GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
7001 | GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
7002 | GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_ISA206), |
7003 | GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), |
7004 | #endif |
7005 | GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW), |
7006 | GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW), |
7007 | GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW), |
7008 | #if defined(TARGET_PPC64) |
7009 | GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B), |
7010 | GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B), |
7011 | #endif |
7012 | GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC), |
7013 | GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC), |
7014 | GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC), |
7015 | GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC), |
7016 | GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB), |
7017 | GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC), |
7018 | #if defined(TARGET_PPC64) |
7019 | GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B), |
7020 | GEN_HANDLER_E(setb, 0x1F, 0x00, 0x04, 0x0003F801, PPC_NONE, PPC2_ISA300), |
7021 | GEN_HANDLER_E(mcrxrx, 0x1F, 0x00, 0x12, 0x007FF801, PPC_NONE, PPC2_ISA300), |
7022 | #endif |
7023 | GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001EF801, PPC_MISC), |
7024 | GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000000, PPC_MISC), |
7025 | GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE), |
7026 | GEN_HANDLER_E(dcbfep, 0x1F, 0x1F, 0x03, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
7027 | GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE), |
7028 | GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE), |
7029 | GEN_HANDLER_E(dcbstep, 0x1F, 0x1F, 0x01, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
7030 | GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE), |
7031 | GEN_HANDLER_E(dcbtep, 0x1F, 0x1F, 0x09, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
7032 | GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE), |
7033 | GEN_HANDLER_E(dcbtstep, 0x1F, 0x1F, 0x07, 0x00000001, PPC_NONE, PPC2_BOOKE206), |
7034 | GEN_HANDLER_E(dcbtls, 0x1F, 0x06, 0x05, 0x02000001, PPC_BOOKE, PPC2_BOOKE206), |
7035 | GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ), |
7036 | GEN_HANDLER_E(dcbzep, 0x1F, 0x1F, 0x1F, 0x03C00001, PPC_NONE, PPC2_BOOKE206), |
7037 | GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC), |
7038 | GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x01800001, PPC_ALTIVEC), |
7039 | GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC), |
7040 | GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI), |
7041 | GEN_HANDLER_E(icbiep, 0x1F, 0x1F, 0x1E, 0x03E00001, PPC_NONE, PPC2_BOOKE206), |
7042 | GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA), |
7043 | GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT), |
7044 | GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT), |
7045 | GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT), |
7046 | GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT), |
7047 | #if defined(TARGET_PPC64) |
7048 | GEN_HANDLER2(mfsr_64b, "mfsr" , 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B), |
7049 | GEN_HANDLER2(mfsrin_64b, "mfsrin" , 0x1F, 0x13, 0x14, 0x001F0001, |
7050 | PPC_SEGMENT_64B), |
7051 | GEN_HANDLER2(mtsr_64b, "mtsr" , 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B), |
7052 | GEN_HANDLER2(mtsrin_64b, "mtsrin" , 0x1F, 0x12, 0x07, 0x001F0001, |
7053 | PPC_SEGMENT_64B), |
7054 | GEN_HANDLER2(slbmte, "slbmte" , 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B), |
7055 | GEN_HANDLER2(slbmfee, "slbmfee" , 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B), |
7056 | GEN_HANDLER2(slbmfev, "slbmfev" , 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B), |
7057 | GEN_HANDLER2(slbfee_, "slbfee." , 0x1F, 0x13, 0x1E, 0x001F0000, PPC_SEGMENT_64B), |
7058 | #endif |
7059 | GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA), |
7060 | /* |
7061 | * XXX Those instructions will need to be handled differently for |
7062 | * different ISA versions |
7063 | */ |
7064 | GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x001F0001, PPC_MEM_TLBIE), |
7065 | GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x001F0001, PPC_MEM_TLBIE), |
7066 | GEN_HANDLER_E(tlbiel, 0x1F, 0x12, 0x08, 0x00100001, PPC_NONE, PPC2_ISA300), |
7067 | GEN_HANDLER_E(tlbie, 0x1F, 0x12, 0x09, 0x00100001, PPC_NONE, PPC2_ISA300), |
7068 | GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC), |
7069 | #if defined(TARGET_PPC64) |
7070 | GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x031FFC01, PPC_SLBI), |
7071 | GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI), |
7072 | GEN_HANDLER_E(slbieg, 0x1F, 0x12, 0x0E, 0x001F0001, PPC_NONE, PPC2_ISA300), |
7073 | GEN_HANDLER_E(slbsync, 0x1F, 0x12, 0x0A, 0x03FFF801, PPC_NONE, PPC2_ISA300), |
7074 | #endif |
7075 | GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN), |
7076 | GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN), |
7077 | GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR), |
7078 | GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR), |
7079 | GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR), |
7080 | GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR), |
7081 | GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR), |
7082 | GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR), |
7083 | GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR), |
7084 | GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR), |
7085 | GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR), |
7086 | GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
7087 | GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR), |
7088 | GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR), |
7089 | GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR), |
7090 | GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR), |
7091 | GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR), |
7092 | GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR), |
7093 | GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR), |
7094 | GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR), |
7095 | GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR), |
7096 | GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR), |
7097 | GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR), |
7098 | GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR), |
7099 | GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR), |
7100 | GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR), |
7101 | GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR), |
7102 | GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR), |
7103 | GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR), |
7104 | GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR), |
7105 | GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR), |
7106 | GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR), |
7107 | GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR), |
7108 | GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR), |
7109 | GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR), |
7110 | GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR), |
7111 | GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC), |
7112 | GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC), |
7113 | GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC), |
7114 | GEN_HANDLER2(tlbld_6xx, "tlbld" , 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB), |
7115 | GEN_HANDLER2(tlbli_6xx, "tlbli" , 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB), |
7116 | GEN_HANDLER2(tlbld_74xx, "tlbld" , 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB), |
7117 | GEN_HANDLER2(tlbli_74xx, "tlbli" , 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB), |
7118 | GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER), |
7119 | GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER), |
7120 | GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER), |
7121 | GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER), |
7122 | GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER), |
7123 | GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER), |
7124 | GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
7125 | GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
7126 | GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2), |
7127 | GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2), |
7128 | GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
7129 | GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2), |
7130 | GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2), |
7131 | GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2), |
7132 | GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI), |
7133 | GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA), |
7134 | GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR), |
7135 | GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR), |
7136 | GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX), |
7137 | GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX), |
7138 | GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX), |
7139 | GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX), |
7140 | GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON), |
7141 | GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON), |
7142 | GEN_HANDLER2(icbt_40x, "icbt" , 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT), |
7143 | GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON), |
7144 | GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON), |
7145 | GEN_HANDLER2(rfci_40x, "rfci" , 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP), |
7146 | GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206), |
7147 | GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI), |
7148 | GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI), |
7149 | GEN_HANDLER2(tlbre_40x, "tlbre" , 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB), |
7150 | GEN_HANDLER2(tlbsx_40x, "tlbsx" , 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB), |
7151 | GEN_HANDLER2(tlbwe_40x, "tlbwe" , 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB), |
7152 | GEN_HANDLER2(tlbre_440, "tlbre" , 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE), |
7153 | GEN_HANDLER2(tlbsx_440, "tlbsx" , 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE), |
7154 | GEN_HANDLER2(tlbwe_440, "tlbwe" , 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE), |
7155 | GEN_HANDLER2_E(tlbre_booke206, "tlbre" , 0x1F, 0x12, 0x1D, 0x00000001, |
7156 | PPC_NONE, PPC2_BOOKE206), |
7157 | GEN_HANDLER2_E(tlbsx_booke206, "tlbsx" , 0x1F, 0x12, 0x1C, 0x00000000, |
7158 | PPC_NONE, PPC2_BOOKE206), |
7159 | GEN_HANDLER2_E(tlbwe_booke206, "tlbwe" , 0x1F, 0x12, 0x1E, 0x00000001, |
7160 | PPC_NONE, PPC2_BOOKE206), |
7161 | GEN_HANDLER2_E(tlbivax_booke206, "tlbivax" , 0x1F, 0x12, 0x18, 0x00000001, |
7162 | PPC_NONE, PPC2_BOOKE206), |
7163 | GEN_HANDLER2_E(tlbilx_booke206, "tlbilx" , 0x1F, 0x12, 0x00, 0x03800001, |
7164 | PPC_NONE, PPC2_BOOKE206), |
7165 | GEN_HANDLER2_E(msgsnd, "msgsnd" , 0x1F, 0x0E, 0x06, 0x03ff0001, |
7166 | PPC_NONE, PPC2_PRCNTL), |
7167 | GEN_HANDLER2_E(msgclr, "msgclr" , 0x1F, 0x0E, 0x07, 0x03ff0001, |
7168 | PPC_NONE, PPC2_PRCNTL), |
7169 | GEN_HANDLER2_E(msgsync, "msgsync" , 0x1F, 0x16, 0x1B, 0x00000000, |
7170 | PPC_NONE, PPC2_PRCNTL), |
7171 | GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE), |
7172 | GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE), |
7173 | GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC), |
7174 | GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801, |
7175 | PPC_BOOKE, PPC2_BOOKE206), |
7176 | GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x039FF801, PPC_BOOKE), |
7177 | GEN_HANDLER2_E(icbt_440, "icbt" , 0x1F, 0x16, 0x00, 0x03E00001, |
7178 | PPC_BOOKE, PPC2_BOOKE206), |
7179 | GEN_HANDLER2(icbt_440, "icbt" , 0x1F, 0x06, 0x08, 0x03E00001, |
7180 | PPC_440_SPEC), |
7181 | GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC), |
7182 | GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC), |
7183 | GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC), |
7184 | GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC), |
7185 | GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC), |
7186 | #if defined(TARGET_PPC64) |
7187 | GEN_HANDLER_E(maddhd_maddhdu, 0x04, 0x18, 0xFF, 0x00000000, PPC_NONE, |
7188 | PPC2_ISA300), |
7189 | GEN_HANDLER_E(maddld, 0x04, 0x19, 0xFF, 0x00000000, PPC_NONE, PPC2_ISA300), |
7190 | #endif |
7191 | |
7192 | #undef GEN_INT_ARITH_ADD |
7193 | #undef GEN_INT_ARITH_ADD_CONST |
7194 | #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \ |
7195 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER), |
7196 | #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \ |
7197 | add_ca, compute_ca, compute_ov) \ |
7198 | GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER), |
7199 | GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0) |
7200 | GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1) |
7201 | GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0) |
7202 | GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1) |
7203 | GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0) |
7204 | GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1) |
7205 | GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0) |
7206 | GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1) |
7207 | GEN_HANDLER_E(addex, 0x1F, 0x0A, 0x05, 0x00000000, PPC_NONE, PPC2_ISA300), |
7208 | GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0) |
7209 | GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1) |
7210 | |
7211 | #undef GEN_INT_ARITH_DIVW |
7212 | #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \ |
7213 | GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER) |
7214 | GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0), |
7215 | GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1), |
7216 | GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0), |
7217 | GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1), |
7218 | GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7219 | GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7220 | GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7221 | GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7222 | GEN_HANDLER_E(modsw, 0x1F, 0x0B, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
7223 | GEN_HANDLER_E(moduw, 0x1F, 0x0B, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), |
7224 | |
7225 | #if defined(TARGET_PPC64) |
7226 | #undef GEN_INT_ARITH_DIVD |
7227 | #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \ |
7228 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
7229 | GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0), |
7230 | GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1), |
7231 | GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0), |
7232 | GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1), |
7233 | |
7234 | GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7235 | GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7236 | GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7237 | GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206), |
7238 | GEN_HANDLER_E(modsd, 0x1F, 0x09, 0x18, 0x00000001, PPC_NONE, PPC2_ISA300), |
7239 | GEN_HANDLER_E(modud, 0x1F, 0x09, 0x08, 0x00000001, PPC_NONE, PPC2_ISA300), |
7240 | |
7241 | #undef GEN_INT_ARITH_MUL_HELPER |
7242 | #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \ |
7243 | GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B) |
7244 | GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00), |
7245 | GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02), |
7246 | GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17), |
7247 | #endif |
7248 | |
7249 | #undef GEN_INT_ARITH_SUBF |
7250 | #undef GEN_INT_ARITH_SUBF_CONST |
7251 | #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \ |
7252 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER), |
7253 | #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \ |
7254 | add_ca, compute_ca, compute_ov) \ |
7255 | GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER), |
7256 | GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0) |
7257 | GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1) |
7258 | GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0) |
7259 | GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1) |
7260 | GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0) |
7261 | GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1) |
7262 | GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0) |
7263 | GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1) |
7264 | GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0) |
7265 | GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1) |
7266 | |
7267 | #undef GEN_LOGICAL1 |
7268 | #undef GEN_LOGICAL2 |
7269 | #define GEN_LOGICAL2(name, tcg_op, opc, type) \ |
7270 | GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type) |
7271 | #define GEN_LOGICAL1(name, tcg_op, opc, type) \ |
7272 | GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type) |
7273 | GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER), |
7274 | GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER), |
7275 | GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER), |
7276 | GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER), |
7277 | GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER), |
7278 | GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER), |
7279 | GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER), |
7280 | GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER), |
7281 | #if defined(TARGET_PPC64) |
7282 | GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B), |
7283 | #endif |
7284 | |
7285 | #if defined(TARGET_PPC64) |
7286 | #undef GEN_PPC64_R2 |
7287 | #undef GEN_PPC64_R4 |
7288 | #define GEN_PPC64_R2(name, opc1, opc2) \ |
7289 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
7290 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
7291 | PPC_64B) |
7292 | #define GEN_PPC64_R4(name, opc1, opc2) \ |
7293 | GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\ |
7294 | GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \ |
7295 | PPC_64B), \ |
7296 | GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \ |
7297 | PPC_64B), \ |
7298 | GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \ |
7299 | PPC_64B) |
7300 | GEN_PPC64_R4(rldicl, 0x1E, 0x00), |
7301 | GEN_PPC64_R4(rldicr, 0x1E, 0x02), |
7302 | GEN_PPC64_R4(rldic, 0x1E, 0x04), |
7303 | GEN_PPC64_R2(rldcl, 0x1E, 0x08), |
7304 | GEN_PPC64_R2(rldcr, 0x1E, 0x09), |
7305 | GEN_PPC64_R4(rldimi, 0x1E, 0x06), |
7306 | #endif |
7307 | |
7308 | #undef GEN_LD |
7309 | #undef GEN_LDU |
7310 | #undef GEN_LDUX |
7311 | #undef GEN_LDX_E |
7312 | #undef GEN_LDS |
7313 | #define GEN_LD(name, ldop, opc, type) \ |
7314 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
7315 | #define GEN_LDU(name, ldop, opc, type) \ |
7316 | GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type), |
7317 | #define GEN_LDUX(name, ldop, opc2, opc3, type) \ |
7318 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
7319 | #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2, chk) \ |
7320 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2), |
7321 | #define GEN_LDS(name, ldop, op, type) \ |
7322 | GEN_LD(name, ldop, op | 0x20, type) \ |
7323 | GEN_LDU(name, ldop, op | 0x21, type) \ |
7324 | GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \ |
7325 | GEN_LDX(name, ldop, 0x17, op | 0x00, type) |
7326 | |
7327 | GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER) |
7328 | GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER) |
7329 | GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER) |
7330 | GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER) |
7331 | #if defined(TARGET_PPC64) |
7332 | GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B) |
7333 | GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B) |
7334 | GEN_LDUX(ld, ld64_i64, 0x15, 0x01, PPC_64B) |
7335 | GEN_LDX(ld, ld64_i64, 0x15, 0x00, PPC_64B) |
7336 | GEN_LDX_E(ldbr, ld64ur_i64, 0x14, 0x10, PPC_NONE, PPC2_DBRX, CHK_NONE) |
7337 | |
7338 | /* HV/P7 and later only */ |
7339 | GEN_LDX_HVRM(ldcix, ld64_i64, 0x15, 0x1b, PPC_CILDST) |
7340 | GEN_LDX_HVRM(lwzcix, ld32u, 0x15, 0x18, PPC_CILDST) |
7341 | GEN_LDX_HVRM(lhzcix, ld16u, 0x15, 0x19, PPC_CILDST) |
7342 | GEN_LDX_HVRM(lbzcix, ld8u, 0x15, 0x1a, PPC_CILDST) |
7343 | #endif |
7344 | GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER) |
7345 | GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER) |
7346 | |
7347 | /* External PID based load */ |
7348 | #undef GEN_LDEPX |
7349 | #define GEN_LDEPX(name, ldop, opc2, opc3) \ |
7350 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ |
7351 | 0x00000001, PPC_NONE, PPC2_BOOKE206), |
7352 | |
7353 | GEN_LDEPX(lb, DEF_MEMOP(MO_UB), 0x1F, 0x02) |
7354 | GEN_LDEPX(lh, DEF_MEMOP(MO_UW), 0x1F, 0x08) |
7355 | GEN_LDEPX(lw, DEF_MEMOP(MO_UL), 0x1F, 0x00) |
7356 | #if defined(TARGET_PPC64) |
7357 | GEN_LDEPX(ld, DEF_MEMOP(MO_Q), 0x1D, 0x00) |
7358 | #endif |
7359 | |
7360 | #undef GEN_ST |
7361 | #undef GEN_STU |
7362 | #undef GEN_STUX |
7363 | #undef GEN_STX_E |
7364 | #undef GEN_STS |
7365 | #define GEN_ST(name, stop, opc, type) \ |
7366 | GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type), |
7367 | #define GEN_STU(name, stop, opc, type) \ |
7368 | GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type), |
7369 | #define GEN_STUX(name, stop, opc2, opc3, type) \ |
7370 | GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type), |
7371 | #define GEN_STX_E(name, stop, opc2, opc3, type, type2, chk) \ |
7372 | GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000000, type, type2), |
7373 | #define GEN_STS(name, stop, op, type) \ |
7374 | GEN_ST(name, stop, op | 0x20, type) \ |
7375 | GEN_STU(name, stop, op | 0x21, type) \ |
7376 | GEN_STUX(name, stop, 0x17, op | 0x01, type) \ |
7377 | GEN_STX(name, stop, 0x17, op | 0x00, type) |
7378 | |
7379 | GEN_STS(stb, st8, 0x06, PPC_INTEGER) |
7380 | GEN_STS(sth, st16, 0x0C, PPC_INTEGER) |
7381 | GEN_STS(stw, st32, 0x04, PPC_INTEGER) |
7382 | #if defined(TARGET_PPC64) |
7383 | GEN_STUX(std, st64_i64, 0x15, 0x05, PPC_64B) |
7384 | GEN_STX(std, st64_i64, 0x15, 0x04, PPC_64B) |
7385 | GEN_STX_E(stdbr, st64r_i64, 0x14, 0x14, PPC_NONE, PPC2_DBRX, CHK_NONE) |
7386 | GEN_STX_HVRM(stdcix, st64_i64, 0x15, 0x1f, PPC_CILDST) |
7387 | GEN_STX_HVRM(stwcix, st32, 0x15, 0x1c, PPC_CILDST) |
7388 | GEN_STX_HVRM(sthcix, st16, 0x15, 0x1d, PPC_CILDST) |
7389 | GEN_STX_HVRM(stbcix, st8, 0x15, 0x1e, PPC_CILDST) |
7390 | #endif |
7391 | GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER) |
7392 | GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER) |
7393 | |
7394 | #undef GEN_STEPX |
7395 | #define GEN_STEPX(name, ldop, opc2, opc3) \ |
7396 | GEN_HANDLER_E(name##epx, 0x1F, opc2, opc3, \ |
7397 | 0x00000001, PPC_NONE, PPC2_BOOKE206), |
7398 | |
7399 | GEN_STEPX(stb, DEF_MEMOP(MO_UB), 0x1F, 0x06) |
7400 | GEN_STEPX(sth, DEF_MEMOP(MO_UW), 0x1F, 0x0C) |
7401 | GEN_STEPX(stw, DEF_MEMOP(MO_UL), 0x1F, 0x04) |
7402 | #if defined(TARGET_PPC64) |
7403 | GEN_STEPX(std, DEF_MEMOP(MO_Q), 0x1D, 0x04) |
7404 | #endif |
7405 | |
7406 | #undef GEN_CRLOGIC |
7407 | #define GEN_CRLOGIC(name, tcg_op, opc) \ |
7408 | GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER) |
7409 | GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08), |
7410 | GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04), |
7411 | GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09), |
7412 | GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07), |
7413 | GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01), |
7414 | GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E), |
7415 | GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D), |
7416 | GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06), |
7417 | |
7418 | #undef GEN_MAC_HANDLER |
7419 | #define GEN_MAC_HANDLER(name, opc2, opc3) \ |
7420 | GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC) |
7421 | GEN_MAC_HANDLER(macchw, 0x0C, 0x05), |
7422 | GEN_MAC_HANDLER(macchwo, 0x0C, 0x15), |
7423 | GEN_MAC_HANDLER(macchws, 0x0C, 0x07), |
7424 | GEN_MAC_HANDLER(macchwso, 0x0C, 0x17), |
7425 | GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06), |
7426 | GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16), |
7427 | GEN_MAC_HANDLER(macchwu, 0x0C, 0x04), |
7428 | GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14), |
7429 | GEN_MAC_HANDLER(machhw, 0x0C, 0x01), |
7430 | GEN_MAC_HANDLER(machhwo, 0x0C, 0x11), |
7431 | GEN_MAC_HANDLER(machhws, 0x0C, 0x03), |
7432 | GEN_MAC_HANDLER(machhwso, 0x0C, 0x13), |
7433 | GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02), |
7434 | GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12), |
7435 | GEN_MAC_HANDLER(machhwu, 0x0C, 0x00), |
7436 | GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10), |
7437 | GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D), |
7438 | GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D), |
7439 | GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F), |
7440 | GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F), |
7441 | GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C), |
7442 | GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C), |
7443 | GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E), |
7444 | GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E), |
7445 | GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05), |
7446 | GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15), |
7447 | GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07), |
7448 | GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17), |
7449 | GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01), |
7450 | GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11), |
7451 | GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03), |
7452 | GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13), |
7453 | GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D), |
7454 | GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D), |
7455 | GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F), |
7456 | GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F), |
7457 | GEN_MAC_HANDLER(mulchw, 0x08, 0x05), |
7458 | GEN_MAC_HANDLER(mulchwu, 0x08, 0x04), |
7459 | GEN_MAC_HANDLER(mulhhw, 0x08, 0x01), |
7460 | GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00), |
7461 | GEN_MAC_HANDLER(mullhw, 0x08, 0x0D), |
7462 | GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C), |
7463 | |
7464 | GEN_HANDLER2_E(tbegin, "tbegin" , 0x1F, 0x0E, 0x14, 0x01DFF800, \ |
7465 | PPC_NONE, PPC2_TM), |
7466 | GEN_HANDLER2_E(tend, "tend" , 0x1F, 0x0E, 0x15, 0x01FFF800, \ |
7467 | PPC_NONE, PPC2_TM), |
7468 | GEN_HANDLER2_E(tabort, "tabort" , 0x1F, 0x0E, 0x1C, 0x03E0F800, \ |
7469 | PPC_NONE, PPC2_TM), |
7470 | GEN_HANDLER2_E(tabortwc, "tabortwc" , 0x1F, 0x0E, 0x18, 0x00000000, \ |
7471 | PPC_NONE, PPC2_TM), |
7472 | GEN_HANDLER2_E(tabortwci, "tabortwci" , 0x1F, 0x0E, 0x1A, 0x00000000, \ |
7473 | PPC_NONE, PPC2_TM), |
7474 | GEN_HANDLER2_E(tabortdc, "tabortdc" , 0x1F, 0x0E, 0x19, 0x00000000, \ |
7475 | PPC_NONE, PPC2_TM), |
7476 | GEN_HANDLER2_E(tabortdci, "tabortdci" , 0x1F, 0x0E, 0x1B, 0x00000000, \ |
7477 | PPC_NONE, PPC2_TM), |
7478 | GEN_HANDLER2_E(tsr, "tsr" , 0x1F, 0x0E, 0x17, 0x03DFF800, \ |
7479 | PPC_NONE, PPC2_TM), |
7480 | GEN_HANDLER2_E(tcheck, "tcheck" , 0x1F, 0x0E, 0x16, 0x007FF800, \ |
7481 | PPC_NONE, PPC2_TM), |
7482 | GEN_HANDLER2_E(treclaim, "treclaim" , 0x1F, 0x0E, 0x1D, 0x03E0F800, \ |
7483 | PPC_NONE, PPC2_TM), |
7484 | GEN_HANDLER2_E(trechkpt, "trechkpt" , 0x1F, 0x0E, 0x1F, 0x03FFF800, \ |
7485 | PPC_NONE, PPC2_TM), |
7486 | |
7487 | #include "translate/fp-ops.inc.c" |
7488 | |
7489 | #include "translate/vmx-ops.inc.c" |
7490 | |
7491 | #include "translate/vsx-ops.inc.c" |
7492 | |
7493 | #include "translate/dfp-ops.inc.c" |
7494 | |
7495 | #include "translate/spe-ops.inc.c" |
7496 | }; |
7497 | |
7498 | #include "helper_regs.h" |
7499 | #include "translate_init.inc.c" |
7500 | |
7501 | /*****************************************************************************/ |
7502 | /* Misc PowerPC helpers */ |
7503 | void ppc_cpu_dump_state(CPUState *cs, FILE *f, int flags) |
7504 | { |
7505 | #define RGPL 4 |
7506 | #define RFPL 4 |
7507 | |
7508 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7509 | CPUPPCState *env = &cpu->env; |
7510 | int i; |
7511 | |
7512 | qemu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR " |
7513 | TARGET_FMT_lx " XER " TARGET_FMT_lx " CPU#%d\n" , |
7514 | env->nip, env->lr, env->ctr, cpu_read_xer(env), |
7515 | cs->cpu_index); |
7516 | qemu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF " |
7517 | TARGET_FMT_lx " iidx %d didx %d\n" , |
7518 | env->msr, env->spr[SPR_HID0], |
7519 | env->hflags, env->immu_idx, env->dmmu_idx); |
7520 | #if !defined(NO_TIMER_DUMP) |
7521 | qemu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64 |
7522 | #if !defined(CONFIG_USER_ONLY) |
7523 | " DECR " TARGET_FMT_lu |
7524 | #endif |
7525 | "\n" , |
7526 | cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env) |
7527 | #if !defined(CONFIG_USER_ONLY) |
7528 | , cpu_ppc_load_decr(env) |
7529 | #endif |
7530 | ); |
7531 | #endif |
7532 | for (i = 0; i < 32; i++) { |
7533 | if ((i & (RGPL - 1)) == 0) { |
7534 | qemu_fprintf(f, "GPR%02d" , i); |
7535 | } |
7536 | qemu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i)); |
7537 | if ((i & (RGPL - 1)) == (RGPL - 1)) { |
7538 | qemu_fprintf(f, "\n" ); |
7539 | } |
7540 | } |
7541 | qemu_fprintf(f, "CR " ); |
7542 | for (i = 0; i < 8; i++) |
7543 | qemu_fprintf(f, "%01x" , env->crf[i]); |
7544 | qemu_fprintf(f, " [" ); |
7545 | for (i = 0; i < 8; i++) { |
7546 | char a = '-'; |
7547 | if (env->crf[i] & 0x08) { |
7548 | a = 'L'; |
7549 | } else if (env->crf[i] & 0x04) { |
7550 | a = 'G'; |
7551 | } else if (env->crf[i] & 0x02) { |
7552 | a = 'E'; |
7553 | } |
7554 | qemu_fprintf(f, " %c%c" , a, env->crf[i] & 0x01 ? 'O' : ' '); |
7555 | } |
7556 | qemu_fprintf(f, " ] RES " TARGET_FMT_lx "\n" , |
7557 | env->reserve_addr); |
7558 | |
7559 | if (flags & CPU_DUMP_FPU) { |
7560 | for (i = 0; i < 32; i++) { |
7561 | if ((i & (RFPL - 1)) == 0) { |
7562 | qemu_fprintf(f, "FPR%02d" , i); |
7563 | } |
7564 | qemu_fprintf(f, " %016" PRIx64, *cpu_fpr_ptr(env, i)); |
7565 | if ((i & (RFPL - 1)) == (RFPL - 1)) { |
7566 | qemu_fprintf(f, "\n" ); |
7567 | } |
7568 | } |
7569 | qemu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n" , env->fpscr); |
7570 | } |
7571 | |
7572 | #if !defined(CONFIG_USER_ONLY) |
7573 | qemu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx |
7574 | " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n" , |
7575 | env->spr[SPR_SRR0], env->spr[SPR_SRR1], |
7576 | env->spr[SPR_PVR], env->spr[SPR_VRSAVE]); |
7577 | |
7578 | qemu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx |
7579 | " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n" , |
7580 | env->spr[SPR_SPRG0], env->spr[SPR_SPRG1], |
7581 | env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]); |
7582 | |
7583 | qemu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx |
7584 | " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n" , |
7585 | env->spr[SPR_SPRG4], env->spr[SPR_SPRG5], |
7586 | env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]); |
7587 | |
7588 | #if defined(TARGET_PPC64) |
7589 | if (env->excp_model == POWERPC_EXCP_POWER7 || |
7590 | env->excp_model == POWERPC_EXCP_POWER8 || |
7591 | env->excp_model == POWERPC_EXCP_POWER9) { |
7592 | qemu_fprintf(f, "HSRR0 " TARGET_FMT_lx " HSRR1 " TARGET_FMT_lx "\n" , |
7593 | env->spr[SPR_HSRR0], env->spr[SPR_HSRR1]); |
7594 | } |
7595 | #endif |
7596 | if (env->excp_model == POWERPC_EXCP_BOOKE) { |
7597 | qemu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx |
7598 | " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n" , |
7599 | env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1], |
7600 | env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]); |
7601 | |
7602 | qemu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx |
7603 | " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n" , |
7604 | env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR], |
7605 | env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]); |
7606 | |
7607 | qemu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx |
7608 | " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n" , |
7609 | env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR], |
7610 | env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]); |
7611 | |
7612 | qemu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx |
7613 | " EPR " TARGET_FMT_lx "\n" , |
7614 | env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8], |
7615 | env->spr[SPR_BOOKE_EPR]); |
7616 | |
7617 | /* FSL-specific */ |
7618 | qemu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx |
7619 | " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n" , |
7620 | env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1], |
7621 | env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]); |
7622 | |
7623 | /* |
7624 | * IVORs are left out as they are large and do not change often -- |
7625 | * they can be read with "p $ivor0", "p $ivor1", etc. |
7626 | */ |
7627 | } |
7628 | |
7629 | #if defined(TARGET_PPC64) |
7630 | if (env->flags & POWERPC_FLAG_CFAR) { |
7631 | qemu_fprintf(f, " CFAR " TARGET_FMT_lx"\n" , env->cfar); |
7632 | } |
7633 | #endif |
7634 | |
7635 | if (env->spr_cb[SPR_LPCR].name) { |
7636 | qemu_fprintf(f, " LPCR " TARGET_FMT_lx "\n" , env->spr[SPR_LPCR]); |
7637 | } |
7638 | |
7639 | switch (env->mmu_model) { |
7640 | case POWERPC_MMU_32B: |
7641 | case POWERPC_MMU_601: |
7642 | case POWERPC_MMU_SOFT_6xx: |
7643 | case POWERPC_MMU_SOFT_74xx: |
7644 | #if defined(TARGET_PPC64) |
7645 | case POWERPC_MMU_64B: |
7646 | case POWERPC_MMU_2_03: |
7647 | case POWERPC_MMU_2_06: |
7648 | case POWERPC_MMU_2_07: |
7649 | case POWERPC_MMU_3_00: |
7650 | #endif |
7651 | if (env->spr_cb[SPR_SDR1].name) { /* SDR1 Exists */ |
7652 | qemu_fprintf(f, " SDR1 " TARGET_FMT_lx " " , env->spr[SPR_SDR1]); |
7653 | } |
7654 | if (env->spr_cb[SPR_PTCR].name) { /* PTCR Exists */ |
7655 | qemu_fprintf(f, " PTCR " TARGET_FMT_lx " " , env->spr[SPR_PTCR]); |
7656 | } |
7657 | qemu_fprintf(f, " DAR " TARGET_FMT_lx " DSISR " TARGET_FMT_lx "\n" , |
7658 | env->spr[SPR_DAR], env->spr[SPR_DSISR]); |
7659 | break; |
7660 | case POWERPC_MMU_BOOKE206: |
7661 | qemu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx |
7662 | " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n" , |
7663 | env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1], |
7664 | env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]); |
7665 | |
7666 | qemu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx |
7667 | " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n" , |
7668 | env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6], |
7669 | env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]); |
7670 | |
7671 | qemu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx |
7672 | " TLB1CFG " TARGET_FMT_lx "\n" , |
7673 | env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG], |
7674 | env->spr[SPR_BOOKE_TLB1CFG]); |
7675 | break; |
7676 | default: |
7677 | break; |
7678 | } |
7679 | #endif |
7680 | |
7681 | #undef RGPL |
7682 | #undef RFPL |
7683 | } |
7684 | |
7685 | void ppc_cpu_dump_statistics(CPUState *cs, int flags) |
7686 | { |
7687 | #if defined(DO_PPC_STATISTICS) |
7688 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7689 | opc_handler_t **t1, **t2, **t3, *handler; |
7690 | int op1, op2, op3; |
7691 | |
7692 | t1 = cpu->env.opcodes; |
7693 | for (op1 = 0; op1 < 64; op1++) { |
7694 | handler = t1[op1]; |
7695 | if (is_indirect_opcode(handler)) { |
7696 | t2 = ind_table(handler); |
7697 | for (op2 = 0; op2 < 32; op2++) { |
7698 | handler = t2[op2]; |
7699 | if (is_indirect_opcode(handler)) { |
7700 | t3 = ind_table(handler); |
7701 | for (op3 = 0; op3 < 32; op3++) { |
7702 | handler = t3[op3]; |
7703 | if (handler->count == 0) { |
7704 | continue; |
7705 | } |
7706 | qemu_printf("%02x %02x %02x (%02x %04d) %16s: " |
7707 | "%016" PRIx64 " %" PRId64 "\n" , |
7708 | op1, op2, op3, op1, (op3 << 5) | op2, |
7709 | handler->oname, |
7710 | handler->count, handler->count); |
7711 | } |
7712 | } else { |
7713 | if (handler->count == 0) { |
7714 | continue; |
7715 | } |
7716 | qemu_printf("%02x %02x (%02x %04d) %16s: " |
7717 | "%016" PRIx64 " %" PRId64 "\n" , |
7718 | op1, op2, op1, op2, handler->oname, |
7719 | handler->count, handler->count); |
7720 | } |
7721 | } |
7722 | } else { |
7723 | if (handler->count == 0) { |
7724 | continue; |
7725 | } |
7726 | qemu_printf("%02x (%02x ) %16s: %016" PRIx64 |
7727 | " %" PRId64 "\n" , |
7728 | op1, op1, handler->oname, |
7729 | handler->count, handler->count); |
7730 | } |
7731 | } |
7732 | #endif |
7733 | } |
7734 | |
7735 | static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) |
7736 | { |
7737 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
7738 | CPUPPCState *env = cs->env_ptr; |
7739 | int bound; |
7740 | |
7741 | ctx->exception = POWERPC_EXCP_NONE; |
7742 | ctx->spr_cb = env->spr_cb; |
7743 | ctx->pr = msr_pr; |
7744 | ctx->mem_idx = env->dmmu_idx; |
7745 | ctx->dr = msr_dr; |
7746 | #if !defined(CONFIG_USER_ONLY) |
7747 | ctx->hv = msr_hv || !env->has_hv_mode; |
7748 | #endif |
7749 | ctx->insns_flags = env->insns_flags; |
7750 | ctx->insns_flags2 = env->insns_flags2; |
7751 | ctx->access_type = -1; |
7752 | ctx->need_access_type = !(env->mmu_model & POWERPC_MMU_64B); |
7753 | ctx->le_mode = !!(env->hflags & (1 << MSR_LE)); |
7754 | ctx->default_tcg_memop_mask = ctx->le_mode ? MO_LE : MO_BE; |
7755 | ctx->flags = env->flags; |
7756 | #if defined(TARGET_PPC64) |
7757 | ctx->sf_mode = msr_is_64bit(env, env->msr); |
7758 | ctx->has_cfar = !!(env->flags & POWERPC_FLAG_CFAR); |
7759 | #endif |
7760 | ctx->lazy_tlb_flush = env->mmu_model == POWERPC_MMU_32B |
7761 | || env->mmu_model == POWERPC_MMU_601 |
7762 | || (env->mmu_model & POWERPC_MMU_64B); |
7763 | |
7764 | ctx->fpu_enabled = !!msr_fp; |
7765 | if ((env->flags & POWERPC_FLAG_SPE) && msr_spe) { |
7766 | ctx->spe_enabled = !!msr_spe; |
7767 | } else { |
7768 | ctx->spe_enabled = false; |
7769 | } |
7770 | if ((env->flags & POWERPC_FLAG_VRE) && msr_vr) { |
7771 | ctx->altivec_enabled = !!msr_vr; |
7772 | } else { |
7773 | ctx->altivec_enabled = false; |
7774 | } |
7775 | if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) { |
7776 | ctx->vsx_enabled = !!msr_vsx; |
7777 | } else { |
7778 | ctx->vsx_enabled = false; |
7779 | } |
7780 | #if defined(TARGET_PPC64) |
7781 | if ((env->flags & POWERPC_FLAG_TM) && msr_tm) { |
7782 | ctx->tm_enabled = !!msr_tm; |
7783 | } else { |
7784 | ctx->tm_enabled = false; |
7785 | } |
7786 | #endif |
7787 | ctx->gtse = !!(env->spr[SPR_LPCR] & LPCR_GTSE); |
7788 | if ((env->flags & POWERPC_FLAG_SE) && msr_se) { |
7789 | ctx->singlestep_enabled = CPU_SINGLE_STEP; |
7790 | } else { |
7791 | ctx->singlestep_enabled = 0; |
7792 | } |
7793 | if ((env->flags & POWERPC_FLAG_BE) && msr_be) { |
7794 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
7795 | } |
7796 | if ((env->flags & POWERPC_FLAG_DE) && msr_de) { |
7797 | ctx->singlestep_enabled = 0; |
7798 | target_ulong dbcr0 = env->spr[SPR_BOOKE_DBCR0]; |
7799 | if (dbcr0 & DBCR0_ICMP) { |
7800 | ctx->singlestep_enabled |= CPU_SINGLE_STEP; |
7801 | } |
7802 | if (dbcr0 & DBCR0_BRT) { |
7803 | ctx->singlestep_enabled |= CPU_BRANCH_STEP; |
7804 | } |
7805 | |
7806 | } |
7807 | if (unlikely(ctx->base.singlestep_enabled)) { |
7808 | ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP; |
7809 | } |
7810 | #if defined(DO_SINGLE_STEP) && 0 |
7811 | /* Single step trace mode */ |
7812 | msr_se = 1; |
7813 | #endif |
7814 | |
7815 | bound = -(ctx->base.pc_first | TARGET_PAGE_MASK) / 4; |
7816 | ctx->base.max_insns = MIN(ctx->base.max_insns, bound); |
7817 | } |
7818 | |
7819 | static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs) |
7820 | { |
7821 | } |
7822 | |
7823 | static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) |
7824 | { |
7825 | tcg_gen_insn_start(dcbase->pc_next); |
7826 | } |
7827 | |
7828 | static bool ppc_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, |
7829 | const CPUBreakpoint *bp) |
7830 | { |
7831 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
7832 | |
7833 | gen_debug_exception(ctx); |
7834 | dcbase->is_jmp = DISAS_NORETURN; |
7835 | /* |
7836 | * The address covered by the breakpoint must be included in |
7837 | * [tb->pc, tb->pc + tb->size) in order to for it to be properly |
7838 | * cleared -- thus we increment the PC here so that the logic |
7839 | * setting tb->size below does the right thing. |
7840 | */ |
7841 | ctx->base.pc_next += 4; |
7842 | return true; |
7843 | } |
7844 | |
7845 | static void ppc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) |
7846 | { |
7847 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
7848 | PowerPCCPU *cpu = POWERPC_CPU(cs); |
7849 | CPUPPCState *env = cs->env_ptr; |
7850 | opc_handler_t **table, *handler; |
7851 | |
7852 | LOG_DISAS("----------------\n" ); |
7853 | LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n" , |
7854 | ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); |
7855 | |
7856 | if (unlikely(need_byteswap(ctx))) { |
7857 | ctx->opcode = bswap32(cpu_ldl_code(env, ctx->base.pc_next)); |
7858 | } else { |
7859 | ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); |
7860 | } |
7861 | LOG_DISAS("translate opcode %08x (%02x %02x %02x %02x) (%s)\n" , |
7862 | ctx->opcode, opc1(ctx->opcode), opc2(ctx->opcode), |
7863 | opc3(ctx->opcode), opc4(ctx->opcode), |
7864 | ctx->le_mode ? "little" : "big" ); |
7865 | ctx->base.pc_next += 4; |
7866 | table = cpu->opcodes; |
7867 | handler = table[opc1(ctx->opcode)]; |
7868 | if (is_indirect_opcode(handler)) { |
7869 | table = ind_table(handler); |
7870 | handler = table[opc2(ctx->opcode)]; |
7871 | if (is_indirect_opcode(handler)) { |
7872 | table = ind_table(handler); |
7873 | handler = table[opc3(ctx->opcode)]; |
7874 | if (is_indirect_opcode(handler)) { |
7875 | table = ind_table(handler); |
7876 | handler = table[opc4(ctx->opcode)]; |
7877 | } |
7878 | } |
7879 | } |
7880 | /* Is opcode *REALLY* valid ? */ |
7881 | if (unlikely(handler->handler == &gen_invalid)) { |
7882 | qemu_log_mask(LOG_GUEST_ERROR, "invalid/unsupported opcode: " |
7883 | "%02x - %02x - %02x - %02x (%08x) " |
7884 | TARGET_FMT_lx " %d\n" , |
7885 | opc1(ctx->opcode), opc2(ctx->opcode), |
7886 | opc3(ctx->opcode), opc4(ctx->opcode), |
7887 | ctx->opcode, ctx->base.pc_next - 4, (int)msr_ir); |
7888 | } else { |
7889 | uint32_t inval; |
7890 | |
7891 | if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) |
7892 | && Rc(ctx->opcode))) { |
7893 | inval = handler->inval2; |
7894 | } else { |
7895 | inval = handler->inval1; |
7896 | } |
7897 | |
7898 | if (unlikely((ctx->opcode & inval) != 0)) { |
7899 | qemu_log_mask(LOG_GUEST_ERROR, "invalid bits: %08x for opcode: " |
7900 | "%02x - %02x - %02x - %02x (%08x) " |
7901 | TARGET_FMT_lx "\n" , ctx->opcode & inval, |
7902 | opc1(ctx->opcode), opc2(ctx->opcode), |
7903 | opc3(ctx->opcode), opc4(ctx->opcode), |
7904 | ctx->opcode, ctx->base.pc_next - 4); |
7905 | gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); |
7906 | ctx->base.is_jmp = DISAS_NORETURN; |
7907 | return; |
7908 | } |
7909 | } |
7910 | (*(handler->handler))(ctx); |
7911 | #if defined(DO_PPC_STATISTICS) |
7912 | handler->count++; |
7913 | #endif |
7914 | /* Check trace mode exceptions */ |
7915 | if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP && |
7916 | (ctx->base.pc_next <= 0x100 || ctx->base.pc_next > 0xF00) && |
7917 | ctx->exception != POWERPC_SYSCALL && |
7918 | ctx->exception != POWERPC_EXCP_TRAP && |
7919 | ctx->exception != POWERPC_EXCP_BRANCH)) { |
7920 | uint32_t excp = gen_prep_dbgex(ctx); |
7921 | gen_exception_nip(ctx, excp, ctx->base.pc_next); |
7922 | } |
7923 | |
7924 | if (tcg_check_temp_count()) { |
7925 | qemu_log("Opcode %02x %02x %02x %02x (%08x) leaked " |
7926 | "temporaries\n" , opc1(ctx->opcode), opc2(ctx->opcode), |
7927 | opc3(ctx->opcode), opc4(ctx->opcode), ctx->opcode); |
7928 | } |
7929 | |
7930 | ctx->base.is_jmp = ctx->exception == POWERPC_EXCP_NONE ? |
7931 | DISAS_NEXT : DISAS_NORETURN; |
7932 | } |
7933 | |
7934 | static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) |
7935 | { |
7936 | DisasContext *ctx = container_of(dcbase, DisasContext, base); |
7937 | |
7938 | if (ctx->exception == POWERPC_EXCP_NONE) { |
7939 | gen_goto_tb(ctx, 0, ctx->base.pc_next); |
7940 | } else if (ctx->exception != POWERPC_EXCP_BRANCH) { |
7941 | if (unlikely(ctx->base.singlestep_enabled)) { |
7942 | gen_debug_exception(ctx); |
7943 | } |
7944 | /* Generate the return instruction */ |
7945 | tcg_gen_exit_tb(NULL, 0); |
7946 | } |
7947 | } |
7948 | |
7949 | static void ppc_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) |
7950 | { |
7951 | qemu_log("IN: %s\n" , lookup_symbol(dcbase->pc_first)); |
7952 | log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); |
7953 | } |
7954 | |
7955 | static const TranslatorOps ppc_tr_ops = { |
7956 | .init_disas_context = ppc_tr_init_disas_context, |
7957 | .tb_start = ppc_tr_tb_start, |
7958 | .insn_start = ppc_tr_insn_start, |
7959 | .breakpoint_check = ppc_tr_breakpoint_check, |
7960 | .translate_insn = ppc_tr_translate_insn, |
7961 | .tb_stop = ppc_tr_tb_stop, |
7962 | .disas_log = ppc_tr_disas_log, |
7963 | }; |
7964 | |
7965 | void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) |
7966 | { |
7967 | DisasContext ctx; |
7968 | |
7969 | translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns); |
7970 | } |
7971 | |
7972 | void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, |
7973 | target_ulong *data) |
7974 | { |
7975 | env->nip = data[0]; |
7976 | } |
7977 | |