1 | /* |
2 | * Tiny Code Generator for QEMU |
3 | * |
4 | * Copyright (c) 2008 Fabrice Bellard |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #ifndef TCG_TCG_OP_H |
26 | #define TCG_TCG_OP_H |
27 | |
28 | #include "tcg.h" |
29 | #include "exec/helper-proto.h" |
30 | #include "exec/helper-gen.h" |
31 | |
32 | /* Basic output routines. Not for general consumption. */ |
33 | |
34 | void tcg_gen_op1(TCGOpcode, TCGArg); |
35 | void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); |
36 | void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); |
37 | void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); |
38 | void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); |
39 | void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); |
40 | |
41 | void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); |
42 | void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); |
43 | void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); |
44 | |
45 | static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) |
46 | { |
47 | tcg_gen_op1(opc, tcgv_i32_arg(a1)); |
48 | } |
49 | |
50 | static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) |
51 | { |
52 | tcg_gen_op1(opc, tcgv_i64_arg(a1)); |
53 | } |
54 | |
55 | static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) |
56 | { |
57 | tcg_gen_op1(opc, a1); |
58 | } |
59 | |
60 | static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) |
61 | { |
62 | tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); |
63 | } |
64 | |
65 | static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) |
66 | { |
67 | tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); |
68 | } |
69 | |
70 | static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) |
71 | { |
72 | tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); |
73 | } |
74 | |
75 | static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) |
76 | { |
77 | tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); |
78 | } |
79 | |
80 | static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) |
81 | { |
82 | tcg_gen_op2(opc, a1, a2); |
83 | } |
84 | |
85 | static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, |
86 | TCGv_i32 a2, TCGv_i32 a3) |
87 | { |
88 | tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); |
89 | } |
90 | |
91 | static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, |
92 | TCGv_i64 a2, TCGv_i64 a3) |
93 | { |
94 | tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); |
95 | } |
96 | |
97 | static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, |
98 | TCGv_i32 a2, TCGArg a3) |
99 | { |
100 | tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); |
101 | } |
102 | |
103 | static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, |
104 | TCGv_i64 a2, TCGArg a3) |
105 | { |
106 | tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); |
107 | } |
108 | |
109 | static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, |
110 | TCGv_ptr base, TCGArg offset) |
111 | { |
112 | tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); |
113 | } |
114 | |
115 | static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, |
116 | TCGv_ptr base, TCGArg offset) |
117 | { |
118 | tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); |
119 | } |
120 | |
121 | static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
122 | TCGv_i32 a3, TCGv_i32 a4) |
123 | { |
124 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
125 | tcgv_i32_arg(a3), tcgv_i32_arg(a4)); |
126 | } |
127 | |
128 | static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
129 | TCGv_i64 a3, TCGv_i64 a4) |
130 | { |
131 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
132 | tcgv_i64_arg(a3), tcgv_i64_arg(a4)); |
133 | } |
134 | |
135 | static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
136 | TCGv_i32 a3, TCGArg a4) |
137 | { |
138 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
139 | tcgv_i32_arg(a3), a4); |
140 | } |
141 | |
142 | static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
143 | TCGv_i64 a3, TCGArg a4) |
144 | { |
145 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
146 | tcgv_i64_arg(a3), a4); |
147 | } |
148 | |
149 | static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
150 | TCGArg a3, TCGArg a4) |
151 | { |
152 | tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); |
153 | } |
154 | |
155 | static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
156 | TCGArg a3, TCGArg a4) |
157 | { |
158 | tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); |
159 | } |
160 | |
161 | static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
162 | TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) |
163 | { |
164 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
165 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); |
166 | } |
167 | |
168 | static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
169 | TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) |
170 | { |
171 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
172 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); |
173 | } |
174 | |
175 | static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
176 | TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) |
177 | { |
178 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
179 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); |
180 | } |
181 | |
182 | static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
183 | TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) |
184 | { |
185 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
186 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); |
187 | } |
188 | |
189 | static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
190 | TCGv_i32 a3, TCGArg a4, TCGArg a5) |
191 | { |
192 | tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
193 | tcgv_i32_arg(a3), a4, a5); |
194 | } |
195 | |
196 | static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
197 | TCGv_i64 a3, TCGArg a4, TCGArg a5) |
198 | { |
199 | tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
200 | tcgv_i64_arg(a3), a4, a5); |
201 | } |
202 | |
203 | static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
204 | TCGv_i32 a3, TCGv_i32 a4, |
205 | TCGv_i32 a5, TCGv_i32 a6) |
206 | { |
207 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
208 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), |
209 | tcgv_i32_arg(a6)); |
210 | } |
211 | |
212 | static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
213 | TCGv_i64 a3, TCGv_i64 a4, |
214 | TCGv_i64 a5, TCGv_i64 a6) |
215 | { |
216 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
217 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), |
218 | tcgv_i64_arg(a6)); |
219 | } |
220 | |
221 | static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
222 | TCGv_i32 a3, TCGv_i32 a4, |
223 | TCGv_i32 a5, TCGArg a6) |
224 | { |
225 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
226 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); |
227 | } |
228 | |
229 | static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
230 | TCGv_i64 a3, TCGv_i64 a4, |
231 | TCGv_i64 a5, TCGArg a6) |
232 | { |
233 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
234 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); |
235 | } |
236 | |
237 | static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, |
238 | TCGv_i32 a3, TCGv_i32 a4, |
239 | TCGArg a5, TCGArg a6) |
240 | { |
241 | tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), |
242 | tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); |
243 | } |
244 | |
245 | static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, |
246 | TCGv_i64 a3, TCGv_i64 a4, |
247 | TCGArg a5, TCGArg a6) |
248 | { |
249 | tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), |
250 | tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); |
251 | } |
252 | |
253 | |
254 | /* Generic ops. */ |
255 | |
256 | static inline void gen_set_label(TCGLabel *l) |
257 | { |
258 | l->present = 1; |
259 | tcg_gen_op1(INDEX_op_set_label, label_arg(l)); |
260 | } |
261 | |
262 | static inline void tcg_gen_br(TCGLabel *l) |
263 | { |
264 | l->refs++; |
265 | tcg_gen_op1(INDEX_op_br, label_arg(l)); |
266 | } |
267 | |
268 | void tcg_gen_mb(TCGBar); |
269 | |
270 | /* Helper calls. */ |
271 | |
272 | /* 32 bit ops */ |
273 | |
274 | void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
275 | void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); |
276 | void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
277 | void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
278 | void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
279 | void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
280 | void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
281 | void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
282 | void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
283 | void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); |
284 | void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
285 | void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
286 | void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
287 | void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
288 | void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
289 | void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
290 | void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
291 | void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
292 | void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
293 | void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
294 | void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
295 | void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
296 | void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); |
297 | void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); |
298 | void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); |
299 | void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
300 | void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
301 | void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); |
302 | void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2); |
303 | void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, |
304 | unsigned int ofs, unsigned int len); |
305 | void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, |
306 | unsigned int ofs, unsigned int len); |
307 | void (TCGv_i32 ret, TCGv_i32 arg, |
308 | unsigned int ofs, unsigned int len); |
309 | void (TCGv_i32 ret, TCGv_i32 arg, |
310 | unsigned int ofs, unsigned int len); |
311 | void (TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, |
312 | unsigned int ofs); |
313 | void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); |
314 | void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); |
315 | void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, |
316 | TCGv_i32 arg1, TCGv_i32 arg2); |
317 | void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, |
318 | TCGv_i32 arg1, int32_t arg2); |
319 | void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, |
320 | TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); |
321 | void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, |
322 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); |
323 | void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, |
324 | TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); |
325 | void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
326 | void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
327 | void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); |
328 | void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); |
329 | void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); |
330 | void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); |
331 | void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); |
332 | void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg); |
333 | void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); |
334 | void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); |
335 | void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); |
336 | void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); |
337 | void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); |
338 | void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); |
339 | |
340 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) |
341 | { |
342 | tcg_gen_op1_i32(INDEX_op_discard, arg); |
343 | } |
344 | |
345 | static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) |
346 | { |
347 | if (ret != arg) { |
348 | tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); |
349 | } |
350 | } |
351 | |
352 | static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg) |
353 | { |
354 | tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg); |
355 | } |
356 | |
357 | static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
358 | tcg_target_long offset) |
359 | { |
360 | tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); |
361 | } |
362 | |
363 | static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
364 | tcg_target_long offset) |
365 | { |
366 | tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); |
367 | } |
368 | |
369 | static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, |
370 | tcg_target_long offset) |
371 | { |
372 | tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); |
373 | } |
374 | |
375 | static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, |
376 | tcg_target_long offset) |
377 | { |
378 | tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); |
379 | } |
380 | |
381 | static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, |
382 | tcg_target_long offset) |
383 | { |
384 | tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); |
385 | } |
386 | |
387 | static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
388 | tcg_target_long offset) |
389 | { |
390 | tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); |
391 | } |
392 | |
393 | static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
394 | tcg_target_long offset) |
395 | { |
396 | tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); |
397 | } |
398 | |
399 | static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, |
400 | tcg_target_long offset) |
401 | { |
402 | tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); |
403 | } |
404 | |
405 | static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
406 | { |
407 | tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); |
408 | } |
409 | |
410 | static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
411 | { |
412 | tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); |
413 | } |
414 | |
415 | static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
416 | { |
417 | tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); |
418 | } |
419 | |
420 | static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
421 | { |
422 | tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); |
423 | } |
424 | |
425 | static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
426 | { |
427 | tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); |
428 | } |
429 | |
430 | static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
431 | { |
432 | tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); |
433 | } |
434 | |
435 | static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
436 | { |
437 | tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); |
438 | } |
439 | |
440 | static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
441 | { |
442 | tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); |
443 | } |
444 | |
445 | static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) |
446 | { |
447 | tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); |
448 | } |
449 | |
450 | static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) |
451 | { |
452 | if (TCG_TARGET_HAS_neg_i32) { |
453 | tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); |
454 | } else { |
455 | tcg_gen_subfi_i32(ret, 0, arg); |
456 | } |
457 | } |
458 | |
459 | static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) |
460 | { |
461 | if (TCG_TARGET_HAS_not_i32) { |
462 | tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); |
463 | } else { |
464 | tcg_gen_xori_i32(ret, arg, -1); |
465 | } |
466 | } |
467 | |
468 | /* 64 bit ops */ |
469 | |
470 | void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
471 | void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); |
472 | void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
473 | void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
474 | void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
475 | void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
476 | void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
477 | void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
478 | void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
479 | void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); |
480 | void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
481 | void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
482 | void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
483 | void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
484 | void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
485 | void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
486 | void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
487 | void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
488 | void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
489 | void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
490 | void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
491 | void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
492 | void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); |
493 | void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); |
494 | void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); |
495 | void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
496 | void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
497 | void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
498 | void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2); |
499 | void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, |
500 | unsigned int ofs, unsigned int len); |
501 | void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, |
502 | unsigned int ofs, unsigned int len); |
503 | void (TCGv_i64 ret, TCGv_i64 arg, |
504 | unsigned int ofs, unsigned int len); |
505 | void (TCGv_i64 ret, TCGv_i64 arg, |
506 | unsigned int ofs, unsigned int len); |
507 | void (TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, |
508 | unsigned int ofs); |
509 | void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); |
510 | void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); |
511 | void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, |
512 | TCGv_i64 arg1, TCGv_i64 arg2); |
513 | void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, |
514 | TCGv_i64 arg1, int64_t arg2); |
515 | void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, |
516 | TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); |
517 | void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, |
518 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); |
519 | void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, |
520 | TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); |
521 | void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
522 | void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
523 | void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); |
524 | void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); |
525 | void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); |
526 | void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); |
527 | void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); |
528 | void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); |
529 | void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); |
530 | void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); |
531 | void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg); |
532 | void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg); |
533 | void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); |
534 | void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); |
535 | void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); |
536 | void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); |
537 | void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); |
538 | void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); |
539 | |
540 | #if TCG_TARGET_REG_BITS == 64 |
541 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) |
542 | { |
543 | tcg_gen_op1_i64(INDEX_op_discard, arg); |
544 | } |
545 | |
546 | static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) |
547 | { |
548 | if (ret != arg) { |
549 | tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); |
550 | } |
551 | } |
552 | |
553 | static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg) |
554 | { |
555 | tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg); |
556 | } |
557 | |
558 | static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
559 | tcg_target_long offset) |
560 | { |
561 | tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); |
562 | } |
563 | |
564 | static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
565 | tcg_target_long offset) |
566 | { |
567 | tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); |
568 | } |
569 | |
570 | static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
571 | tcg_target_long offset) |
572 | { |
573 | tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); |
574 | } |
575 | |
576 | static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
577 | tcg_target_long offset) |
578 | { |
579 | tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); |
580 | } |
581 | |
582 | static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, |
583 | tcg_target_long offset) |
584 | { |
585 | tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); |
586 | } |
587 | |
588 | static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, |
589 | tcg_target_long offset) |
590 | { |
591 | tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); |
592 | } |
593 | |
594 | static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, |
595 | tcg_target_long offset) |
596 | { |
597 | tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); |
598 | } |
599 | |
600 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
601 | tcg_target_long offset) |
602 | { |
603 | tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); |
604 | } |
605 | |
606 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
607 | tcg_target_long offset) |
608 | { |
609 | tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); |
610 | } |
611 | |
612 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
613 | tcg_target_long offset) |
614 | { |
615 | tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); |
616 | } |
617 | |
618 | static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
619 | tcg_target_long offset) |
620 | { |
621 | tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); |
622 | } |
623 | |
624 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
625 | { |
626 | tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); |
627 | } |
628 | |
629 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
630 | { |
631 | tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); |
632 | } |
633 | |
634 | static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
635 | { |
636 | tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); |
637 | } |
638 | |
639 | static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
640 | { |
641 | tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); |
642 | } |
643 | |
644 | static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
645 | { |
646 | tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); |
647 | } |
648 | |
649 | static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
650 | { |
651 | tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); |
652 | } |
653 | |
654 | static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
655 | { |
656 | tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); |
657 | } |
658 | |
659 | static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
660 | { |
661 | tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); |
662 | } |
663 | |
664 | static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
665 | { |
666 | tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); |
667 | } |
668 | #else /* TCG_TARGET_REG_BITS == 32 */ |
669 | static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
670 | tcg_target_long offset) |
671 | { |
672 | tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset); |
673 | } |
674 | |
675 | static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
676 | tcg_target_long offset) |
677 | { |
678 | tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset); |
679 | } |
680 | |
681 | static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, |
682 | tcg_target_long offset) |
683 | { |
684 | tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset); |
685 | } |
686 | |
687 | static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
688 | { |
689 | tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
690 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); |
691 | } |
692 | |
693 | static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) |
694 | { |
695 | tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1), |
696 | TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2)); |
697 | } |
698 | |
699 | void tcg_gen_discard_i64(TCGv_i64 arg); |
700 | void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); |
701 | void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); |
702 | void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
703 | void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
704 | void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
705 | void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
706 | void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
707 | void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
708 | void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); |
709 | void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); |
710 | void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
711 | void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
712 | void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
713 | void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
714 | void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
715 | void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
716 | void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); |
717 | #endif /* TCG_TARGET_REG_BITS */ |
718 | |
719 | static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) |
720 | { |
721 | if (TCG_TARGET_HAS_neg_i64) { |
722 | tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); |
723 | } else { |
724 | tcg_gen_subfi_i64(ret, 0, arg); |
725 | } |
726 | } |
727 | |
728 | /* Size changing operations. */ |
729 | |
730 | void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
731 | void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); |
732 | void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); |
733 | void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
734 | void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); |
735 | void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); |
736 | void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); |
737 | |
738 | static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) |
739 | { |
740 | tcg_gen_deposit_i64(ret, lo, hi, 32, 32); |
741 | } |
742 | |
743 | /* QEMU specific operations. */ |
744 | |
745 | #ifndef TARGET_LONG_BITS |
746 | #error must include QEMU headers |
747 | #endif |
748 | |
749 | #if TARGET_INSN_START_WORDS == 1 |
750 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
751 | static inline void tcg_gen_insn_start(target_ulong pc) |
752 | { |
753 | tcg_gen_op1(INDEX_op_insn_start, pc); |
754 | } |
755 | # else |
756 | static inline void tcg_gen_insn_start(target_ulong pc) |
757 | { |
758 | tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32)); |
759 | } |
760 | # endif |
761 | #elif TARGET_INSN_START_WORDS == 2 |
762 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
763 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
764 | { |
765 | tcg_gen_op2(INDEX_op_insn_start, pc, a1); |
766 | } |
767 | # else |
768 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
769 | { |
770 | tcg_gen_op4(INDEX_op_insn_start, |
771 | (uint32_t)pc, (uint32_t)(pc >> 32), |
772 | (uint32_t)a1, (uint32_t)(a1 >> 32)); |
773 | } |
774 | # endif |
775 | #elif TARGET_INSN_START_WORDS == 3 |
776 | # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS |
777 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
778 | target_ulong a2) |
779 | { |
780 | tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2); |
781 | } |
782 | # else |
783 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
784 | target_ulong a2) |
785 | { |
786 | tcg_gen_op6(INDEX_op_insn_start, |
787 | (uint32_t)pc, (uint32_t)(pc >> 32), |
788 | (uint32_t)a1, (uint32_t)(a1 >> 32), |
789 | (uint32_t)a2, (uint32_t)(a2 >> 32)); |
790 | } |
791 | # endif |
792 | #else |
793 | # error "Unhandled number of operands to insn_start" |
794 | #endif |
795 | |
796 | /** |
797 | * tcg_gen_exit_tb() - output exit_tb TCG operation |
798 | * @tb: The TranslationBlock from which we are exiting |
799 | * @idx: Direct jump slot index, or exit request |
800 | * |
801 | * See tcg/README for more info about this TCG operation. |
802 | * See also tcg.h and the block comment above TB_EXIT_MASK. |
803 | * |
804 | * For a normal exit from the TB, back to the main loop, @tb should |
805 | * be NULL and @idx should be 0. Otherwise, @tb should be valid and |
806 | * @idx should be one of the TB_EXIT_ values. |
807 | */ |
808 | void tcg_gen_exit_tb(TranslationBlock *tb, unsigned idx); |
809 | |
810 | /** |
811 | * tcg_gen_goto_tb() - output goto_tb TCG operation |
812 | * @idx: Direct jump slot index (0 or 1) |
813 | * |
814 | * See tcg/README for more info about this TCG operation. |
815 | * |
816 | * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within |
817 | * the pages this TB resides in because we don't take care of direct jumps when |
818 | * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a |
819 | * static address translation, so the destination address is always valid, TBs |
820 | * are always invalidated properly, and direct jumps are reset when mapping |
821 | * changes. |
822 | */ |
823 | void tcg_gen_goto_tb(unsigned idx); |
824 | |
825 | /** |
826 | * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid |
827 | * @addr: Guest address of the target TB |
828 | * |
829 | * If the TB is not valid, jump to the epilogue. |
830 | * |
831 | * This operation is optional. If the TCG backend does not implement goto_ptr, |
832 | * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. |
833 | */ |
834 | void tcg_gen_lookup_and_goto_ptr(void); |
835 | |
836 | #if TARGET_LONG_BITS == 32 |
837 | #define tcg_temp_new() tcg_temp_new_i32() |
838 | #define tcg_global_reg_new tcg_global_reg_new_i32 |
839 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
840 | #define tcg_temp_local_new() tcg_temp_local_new_i32() |
841 | #define tcg_temp_free tcg_temp_free_i32 |
842 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
843 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 |
844 | #else |
845 | #define tcg_temp_new() tcg_temp_new_i64() |
846 | #define tcg_global_reg_new tcg_global_reg_new_i64 |
847 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
848 | #define tcg_temp_local_new() tcg_temp_local_new_i64() |
849 | #define tcg_temp_free tcg_temp_free_i64 |
850 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
851 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 |
852 | #endif |
853 | |
854 | void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); |
855 | void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); |
856 | void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); |
857 | void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); |
858 | |
859 | static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) |
860 | { |
861 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB); |
862 | } |
863 | |
864 | static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index) |
865 | { |
866 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB); |
867 | } |
868 | |
869 | static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index) |
870 | { |
871 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW); |
872 | } |
873 | |
874 | static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index) |
875 | { |
876 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW); |
877 | } |
878 | |
879 | static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index) |
880 | { |
881 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL); |
882 | } |
883 | |
884 | static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index) |
885 | { |
886 | tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL); |
887 | } |
888 | |
889 | static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index) |
890 | { |
891 | tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ); |
892 | } |
893 | |
894 | static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index) |
895 | { |
896 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB); |
897 | } |
898 | |
899 | static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index) |
900 | { |
901 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW); |
902 | } |
903 | |
904 | static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index) |
905 | { |
906 | tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL); |
907 | } |
908 | |
909 | static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index) |
910 | { |
911 | tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ); |
912 | } |
913 | |
914 | void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, |
915 | TCGArg, MemOp); |
916 | void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, |
917 | TCGArg, MemOp); |
918 | |
919 | void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
920 | void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
921 | |
922 | void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
923 | void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
924 | void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
925 | void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
926 | void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
927 | void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
928 | void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
929 | void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
930 | void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
931 | void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
932 | void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
933 | void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
934 | void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
935 | void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
936 | void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
937 | void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
938 | |
939 | void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
940 | void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
941 | void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
942 | void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
943 | void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
944 | void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
945 | void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
946 | void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
947 | void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
948 | void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
949 | void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
950 | void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
951 | void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
952 | void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
953 | void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); |
954 | void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); |
955 | |
956 | void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); |
957 | void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); |
958 | void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); |
959 | void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); |
960 | void tcg_gen_dup8i_vec(TCGv_vec, uint32_t); |
961 | void tcg_gen_dup16i_vec(TCGv_vec, uint32_t); |
962 | void tcg_gen_dup32i_vec(TCGv_vec, uint32_t); |
963 | void tcg_gen_dup64i_vec(TCGv_vec, uint64_t); |
964 | void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); |
965 | void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
966 | void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
967 | void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
968 | void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
969 | void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
970 | void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
971 | void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
972 | void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
973 | void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
974 | void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
975 | void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
976 | void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); |
977 | void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); |
978 | void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); |
979 | void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
980 | void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
981 | void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
982 | void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
983 | void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
984 | void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
985 | void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
986 | void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); |
987 | |
988 | void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); |
989 | void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); |
990 | void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); |
991 | |
992 | void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); |
993 | void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); |
994 | void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); |
995 | |
996 | void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); |
997 | void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); |
998 | void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); |
999 | |
1000 | void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, |
1001 | TCGv_vec a, TCGv_vec b); |
1002 | |
1003 | void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, |
1004 | TCGv_vec b, TCGv_vec c); |
1005 | void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, |
1006 | TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); |
1007 | |
1008 | void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); |
1009 | void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); |
1010 | void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); |
1011 | |
1012 | #if TARGET_LONG_BITS == 64 |
1013 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
1014 | #define tcg_gen_mov_tl tcg_gen_mov_i64 |
1015 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 |
1016 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 |
1017 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 |
1018 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 |
1019 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 |
1020 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 |
1021 | #define tcg_gen_ld_tl tcg_gen_ld_i64 |
1022 | #define tcg_gen_st8_tl tcg_gen_st8_i64 |
1023 | #define tcg_gen_st16_tl tcg_gen_st16_i64 |
1024 | #define tcg_gen_st32_tl tcg_gen_st32_i64 |
1025 | #define tcg_gen_st_tl tcg_gen_st_i64 |
1026 | #define tcg_gen_add_tl tcg_gen_add_i64 |
1027 | #define tcg_gen_addi_tl tcg_gen_addi_i64 |
1028 | #define tcg_gen_sub_tl tcg_gen_sub_i64 |
1029 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
1030 | #define tcg_gen_abs_tl tcg_gen_abs_i64 |
1031 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
1032 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
1033 | #define tcg_gen_and_tl tcg_gen_and_i64 |
1034 | #define tcg_gen_andi_tl tcg_gen_andi_i64 |
1035 | #define tcg_gen_or_tl tcg_gen_or_i64 |
1036 | #define tcg_gen_ori_tl tcg_gen_ori_i64 |
1037 | #define tcg_gen_xor_tl tcg_gen_xor_i64 |
1038 | #define tcg_gen_xori_tl tcg_gen_xori_i64 |
1039 | #define tcg_gen_not_tl tcg_gen_not_i64 |
1040 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
1041 | #define tcg_gen_shli_tl tcg_gen_shli_i64 |
1042 | #define tcg_gen_shr_tl tcg_gen_shr_i64 |
1043 | #define tcg_gen_shri_tl tcg_gen_shri_i64 |
1044 | #define tcg_gen_sar_tl tcg_gen_sar_i64 |
1045 | #define tcg_gen_sari_tl tcg_gen_sari_i64 |
1046 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
1047 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
1048 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
1049 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
1050 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
1051 | #define tcg_gen_muli_tl tcg_gen_muli_i64 |
1052 | #define tcg_gen_div_tl tcg_gen_div_i64 |
1053 | #define tcg_gen_rem_tl tcg_gen_rem_i64 |
1054 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
1055 | #define tcg_gen_remu_tl tcg_gen_remu_i64 |
1056 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
1057 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
1058 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
1059 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 |
1060 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 |
1061 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 |
1062 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 |
1063 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
1064 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 |
1065 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 |
1066 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 |
1067 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 |
1068 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 |
1069 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
1070 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 |
1071 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 |
1072 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
1073 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
1074 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
1075 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 |
1076 | #define tcg_gen_nand_tl tcg_gen_nand_i64 |
1077 | #define tcg_gen_nor_tl tcg_gen_nor_i64 |
1078 | #define tcg_gen_orc_tl tcg_gen_orc_i64 |
1079 | #define tcg_gen_clz_tl tcg_gen_clz_i64 |
1080 | #define tcg_gen_ctz_tl tcg_gen_ctz_i64 |
1081 | #define tcg_gen_clzi_tl tcg_gen_clzi_i64 |
1082 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 |
1083 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 |
1084 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 |
1085 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
1086 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 |
1087 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 |
1088 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 |
1089 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
1090 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 |
1091 | #define tcg_gen_extract_i64 |
1092 | #define tcg_gen_sextract_i64 |
1093 | #define tcg_gen_extract2_i64 |
1094 | #define tcg_const_tl tcg_const_i64 |
1095 | #define tcg_const_local_tl tcg_const_local_i64 |
1096 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
1097 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
1098 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 |
1099 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
1100 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 |
1101 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 |
1102 | #define tcg_gen_smin_tl tcg_gen_smin_i64 |
1103 | #define tcg_gen_umin_tl tcg_gen_umin_i64 |
1104 | #define tcg_gen_smax_tl tcg_gen_smax_i64 |
1105 | #define tcg_gen_umax_tl tcg_gen_umax_i64 |
1106 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 |
1107 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 |
1108 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 |
1109 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 |
1110 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 |
1111 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 |
1112 | #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64 |
1113 | #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64 |
1114 | #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64 |
1115 | #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64 |
1116 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 |
1117 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 |
1118 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 |
1119 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 |
1120 | #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64 |
1121 | #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 |
1122 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 |
1123 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 |
1124 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec |
1125 | #else |
1126 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
1127 | #define tcg_gen_mov_tl tcg_gen_mov_i32 |
1128 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 |
1129 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 |
1130 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 |
1131 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 |
1132 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 |
1133 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 |
1134 | #define tcg_gen_ld_tl tcg_gen_ld_i32 |
1135 | #define tcg_gen_st8_tl tcg_gen_st8_i32 |
1136 | #define tcg_gen_st16_tl tcg_gen_st16_i32 |
1137 | #define tcg_gen_st32_tl tcg_gen_st_i32 |
1138 | #define tcg_gen_st_tl tcg_gen_st_i32 |
1139 | #define tcg_gen_add_tl tcg_gen_add_i32 |
1140 | #define tcg_gen_addi_tl tcg_gen_addi_i32 |
1141 | #define tcg_gen_sub_tl tcg_gen_sub_i32 |
1142 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
1143 | #define tcg_gen_abs_tl tcg_gen_abs_i32 |
1144 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
1145 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
1146 | #define tcg_gen_and_tl tcg_gen_and_i32 |
1147 | #define tcg_gen_andi_tl tcg_gen_andi_i32 |
1148 | #define tcg_gen_or_tl tcg_gen_or_i32 |
1149 | #define tcg_gen_ori_tl tcg_gen_ori_i32 |
1150 | #define tcg_gen_xor_tl tcg_gen_xor_i32 |
1151 | #define tcg_gen_xori_tl tcg_gen_xori_i32 |
1152 | #define tcg_gen_not_tl tcg_gen_not_i32 |
1153 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
1154 | #define tcg_gen_shli_tl tcg_gen_shli_i32 |
1155 | #define tcg_gen_shr_tl tcg_gen_shr_i32 |
1156 | #define tcg_gen_shri_tl tcg_gen_shri_i32 |
1157 | #define tcg_gen_sar_tl tcg_gen_sar_i32 |
1158 | #define tcg_gen_sari_tl tcg_gen_sari_i32 |
1159 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
1160 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
1161 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
1162 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
1163 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
1164 | #define tcg_gen_muli_tl tcg_gen_muli_i32 |
1165 | #define tcg_gen_div_tl tcg_gen_div_i32 |
1166 | #define tcg_gen_rem_tl tcg_gen_rem_i32 |
1167 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
1168 | #define tcg_gen_remu_tl tcg_gen_remu_i32 |
1169 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
1170 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
1171 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
1172 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
1173 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 |
1174 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 |
1175 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 |
1176 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
1177 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 |
1178 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 |
1179 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 |
1180 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 |
1181 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 |
1182 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
1183 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32 |
1184 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
1185 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
1186 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
1187 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 |
1188 | #define tcg_gen_nand_tl tcg_gen_nand_i32 |
1189 | #define tcg_gen_nor_tl tcg_gen_nor_i32 |
1190 | #define tcg_gen_orc_tl tcg_gen_orc_i32 |
1191 | #define tcg_gen_clz_tl tcg_gen_clz_i32 |
1192 | #define tcg_gen_ctz_tl tcg_gen_ctz_i32 |
1193 | #define tcg_gen_clzi_tl tcg_gen_clzi_i32 |
1194 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 |
1195 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 |
1196 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 |
1197 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
1198 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 |
1199 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 |
1200 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 |
1201 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
1202 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 |
1203 | #define tcg_gen_extract_tl tcg_gen_extract_i32 |
1204 | #define tcg_gen_sextract_tl tcg_gen_sextract_i32 |
1205 | #define tcg_gen_extract2_tl tcg_gen_extract2_i32 |
1206 | #define tcg_const_tl tcg_const_i32 |
1207 | #define tcg_const_local_tl tcg_const_local_i32 |
1208 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
1209 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
1210 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 |
1211 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
1212 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 |
1213 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 |
1214 | #define tcg_gen_smin_tl tcg_gen_smin_i32 |
1215 | #define tcg_gen_umin_tl tcg_gen_umin_i32 |
1216 | #define tcg_gen_smax_tl tcg_gen_smax_i32 |
1217 | #define tcg_gen_umax_tl tcg_gen_umax_i32 |
1218 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 |
1219 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 |
1220 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 |
1221 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 |
1222 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 |
1223 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 |
1224 | #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32 |
1225 | #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32 |
1226 | #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32 |
1227 | #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32 |
1228 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 |
1229 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 |
1230 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 |
1231 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 |
1232 | #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32 |
1233 | #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 |
1234 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 |
1235 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 |
1236 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec |
1237 | #endif |
1238 | |
1239 | #if UINTPTR_MAX == UINT32_MAX |
1240 | # define PTR i32 |
1241 | # define NAT TCGv_i32 |
1242 | #else |
1243 | # define PTR i64 |
1244 | # define NAT TCGv_i64 |
1245 | #endif |
1246 | |
1247 | static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) |
1248 | { |
1249 | glue(tcg_gen_ld_,PTR)((NAT)r, a, o); |
1250 | } |
1251 | |
1252 | static inline void tcg_gen_discard_ptr(TCGv_ptr a) |
1253 | { |
1254 | glue(tcg_gen_discard_,PTR)((NAT)a); |
1255 | } |
1256 | |
1257 | static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) |
1258 | { |
1259 | glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); |
1260 | } |
1261 | |
1262 | static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) |
1263 | { |
1264 | glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); |
1265 | } |
1266 | |
1267 | static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, |
1268 | intptr_t b, TCGLabel *label) |
1269 | { |
1270 | glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); |
1271 | } |
1272 | |
1273 | static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) |
1274 | { |
1275 | #if UINTPTR_MAX == UINT32_MAX |
1276 | tcg_gen_mov_i32((NAT)r, a); |
1277 | #else |
1278 | tcg_gen_ext_i32_i64((NAT)r, a); |
1279 | #endif |
1280 | } |
1281 | |
1282 | static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) |
1283 | { |
1284 | #if UINTPTR_MAX == UINT32_MAX |
1285 | tcg_gen_extrl_i64_i32((NAT)r, a); |
1286 | #else |
1287 | tcg_gen_mov_i64((NAT)r, a); |
1288 | #endif |
1289 | } |
1290 | |
1291 | static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) |
1292 | { |
1293 | #if UINTPTR_MAX == UINT32_MAX |
1294 | tcg_gen_extu_i32_i64(r, (NAT)a); |
1295 | #else |
1296 | tcg_gen_mov_i64(r, (NAT)a); |
1297 | #endif |
1298 | } |
1299 | |
1300 | static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) |
1301 | { |
1302 | #if UINTPTR_MAX == UINT32_MAX |
1303 | tcg_gen_mov_i32(r, (NAT)a); |
1304 | #else |
1305 | tcg_gen_extrl_i64_i32(r, (NAT)a); |
1306 | #endif |
1307 | } |
1308 | |
1309 | #undef PTR |
1310 | #undef NAT |
1311 | |
1312 | #endif /* TCG_TCG_OP_H */ |
1313 | |