1// This file is generated by tools/gen_operators.pl. CHANGES WILL BE OVERWRITTEN
2/* Copyright (C) 2013-2014 Povilas Kanapickas <povilas@radix.lt>
3
4 Distributed under the Boost Software License, Version 1.0.
5 (See accompanying file LICENSE_1_0.txt or copy at
6 http://www.boost.org/LICENSE_1_0.txt)
7*/
8
9#ifndef LIBSIMDPP_SIMDPP_CORE_I_SHIFT_R_OPERATOR_H
10#define LIBSIMDPP_SIMDPP_CORE_I_SHIFT_R_OPERATOR_H
11
12#ifndef LIBSIMDPP_SIMD_H
13 #error "This file must be included through simd.h"
14#endif
15
16#include <simdpp/types.h>
17#include <simdpp/capabilities.h>
18#include <simdpp/detail/insn/i_shift_r.h>
19#include <simdpp/detail/insn/i_shift_r_v.h>
20#include <simdpp/detail/not_implemented.h>
21
22namespace simdpp {
23namespace SIMDPP_ARCH_NAMESPACE {
24
25// -----------------------------------------------------------------------------
26// shift by scalar
27
28/** Shifts signed 8-bit values right by @a count bits while shifting in the
29 sign bit.
30
31 @code
32 r0 = a0 >> count
33 ...
34 rN = aN >> count
35 @endcode
36*/
37template<unsigned N, class E> SIMDPP_INL
38int8<N,expr_empty> operator>>(const int8<N,E>& a, unsigned count)
39{
40 return detail::insn::i_shift_r(a.eval(), count);
41}
42
43/** Shifts unsigned 8-bit values right by @a count bits while shifting in zeros.
44
45 @code
46 r0 = a0 >> count
47 ...
48 rN = aN >> count
49 @endcode
50*/
51template<unsigned N, class E> SIMDPP_INL
52uint8<N,expr_empty> operator>>(const uint8<N,E>& a, unsigned count)
53{
54 return detail::insn::i_shift_r(a.eval(), count);
55}
56
57/** Shifts signed 16-bit values right by @a count bits while shifting in the
58 sign bit.
59
60 @code
61 r0 = a0 >> count
62 ...
63 rN = aN >> count
64 @endcode
65*/
66template<unsigned N, class E> SIMDPP_INL
67int16<N,expr_empty> operator>>(const int16<N,E>& a, unsigned count)
68{
69 return detail::insn::i_shift_r(a.eval(), count);
70}
71
72/** Shifts unsigned 16-bit values right by @a count bits while shifting in
73 zeros.
74
75 @code
76 r0 = a0 >> count
77 ...
78 rN = aN >> count
79 @endcode
80*/
81template<unsigned N, class E> SIMDPP_INL
82uint16<N,expr_empty> operator>>(const uint16<N,E>& a, unsigned count)
83{
84 return detail::insn::i_shift_r(a.eval(), count);
85}
86
87/** Shifts signed 32-bit values right by @a count bits while shifting in the
88 sign bit.
89
90 @code
91 r0 = a0 >> count
92 ...
93 rN = aN >> count
94 @endcode
95*/
96template<unsigned N, class E> SIMDPP_INL
97int32<N,expr_empty> operator>>(const int32<N,E>& a, unsigned count)
98{
99 return detail::insn::i_shift_r(a.eval(), count);
100}
101
102/** Shifts unsigned 32-bit values right by @a count bits while shifting in
103 zeros.
104
105 @code
106 r0 = a0 >> count
107 ...
108 rN = aN >> count
109 @endcode
110*/
111template<unsigned N, class E> SIMDPP_INL
112uint32<N,expr_empty> operator>>(const uint32<N,E>& a, unsigned count)
113{
114 return detail::insn::i_shift_r(a.eval(), count);
115}
116
117/** Shifts signed 64-bit values right by @a count bits while shifting in the
118 sign bit.
119
120 @code
121 r0 = a0 >> count
122 ...
123 rN = aN >> count
124 @endcode
125*/
126template<unsigned N, class E> SIMDPP_INL
127int64<N,expr_empty> operator>>(const int64<N,E>& a, unsigned count)
128{
129 return detail::insn::i_shift_r(a.eval(), count);
130}
131
132/** Shifts unsigned 64-bit values right by @a count bits while shifting in
133 zeros.
134
135 @code
136 r0 = a0 >> count
137 ...
138 rN = aN >> count
139 @endcode
140*/
141template<unsigned N, class E> SIMDPP_INL
142uint64<N,expr_empty> operator>>(const uint64<N,E>& a, unsigned count)
143{
144 return detail::insn::i_shift_r(a.eval(), count);
145}
146
147// -----------------------------------------------------------------------------
148// shift by vector
149
150/** Shifts signed 8-bit values right by the number of bits in corresponding
151 element in the given count vector. Sign bits are shifted in.
152
153 @code
154 r0 = a0 >> count0
155 ...
156 rN = aN >> countN
157 @endcode
158*/
159template<unsigned N, class E> SIMDPP_INL
160int8<N,expr_empty> operator>>(const int8<N,E>& a, const uint8<N,E>& count)
161{
162#if SIMDPP_HAS_INT8_SHIFT_R_BY_VECTOR
163 return detail::insn::i_shift_r_v(a.eval(), count.eval());
164#else
165 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
166#endif
167}
168
169/** Shifts unsigned 8-bit values right by the number of bits in corresponding
170 element in the given count vector. Zero bits are shifted in.
171
172 @code
173 r0 = a0 >> count0
174 ...
175 rN = aN >> countN
176 @endcode
177*/
178template<unsigned N, class E> SIMDPP_INL
179uint8<N,expr_empty> operator>>(const uint8<N,E>& a, const uint8<N,E>& count)
180{
181#if SIMDPP_HAS_UINT8_SHIFT_R_BY_VECTOR
182 return detail::insn::i_shift_r_v(a.eval(), count.eval());
183#else
184 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
185#endif
186}
187
188/** Shifts signed 16-bit values right by the number of bits in corresponding
189 element in the given count vector. Sign bits are shifted in.
190
191 @code
192 r0 = a0 >> count0
193 ...
194 rN = aN >> countN
195 @endcode
196*/
197template<unsigned N, class E> SIMDPP_INL
198int16<N,expr_empty> operator>>(const int16<N,E>& a, const uint16<N,E>& count)
199{
200#if SIMDPP_HAS_INT16_SHIFT_R_BY_VECTOR
201 return detail::insn::i_shift_r_v(a.eval(), count.eval());
202#else
203 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
204#endif
205}
206
207/** Shifts unsigned 16-bit values right by the number of bits in corresponding
208 element in the given count vector. Zero bits are shifted in.
209
210 @code
211 r0 = a0 >> count0
212 ...
213 rN = aN >> countN
214 @endcode
215*/
216template<unsigned N, class E> SIMDPP_INL
217uint16<N,expr_empty> operator>>(const uint16<N,E>& a, const uint16<N,E>& count)
218{
219#if SIMDPP_HAS_UINT16_SHIFT_R_BY_VECTOR
220 return detail::insn::i_shift_r_v(a.eval(), count.eval());
221#else
222 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
223#endif
224}
225
226/** Shifts signed 32-bit values right by the number of bits in corresponding
227 element in the given count vector. Sign bits are shifted in.
228
229 @code
230 r0 = a0 >> count0
231 ...
232 rN = aN >> countN
233 @endcode
234*/
235template<unsigned N, class E> SIMDPP_INL
236int32<N,expr_empty> operator>>(const int32<N,E>& a, const uint32<N,E>& count)
237{
238#if SIMDPP_HAS_INT32_SHIFT_R_BY_VECTOR
239 return detail::insn::i_shift_r_v(a.eval(), count.eval());
240#else
241 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
242#endif
243}
244
245/** Shifts unsigned 32-bit values right by the number of bits in corresponding
246 element in the given count vector. Zero bits are shifted in.
247
248 @code
249 r0 = a0 >> count0
250 ...
251 rN = aN >> countN
252 @endcode
253*/
254template<unsigned N, class E> SIMDPP_INL
255uint32<N,expr_empty> operator>>(const uint32<N,E>& a, const uint32<N,E>& count)
256{
257#if SIMDPP_HAS_UINT32_SHIFT_R_BY_VECTOR
258 return detail::insn::i_shift_r_v(a.eval(), count.eval());
259#else
260 return SIMDPP_NOT_IMPLEMENTED_TEMPLATE2(E, a, count);
261#endif
262}
263
264// -----------------------------------------------------------------------------
265// shift by compile-time constant
266
267} // namespace SIMDPP_ARCH_NAMESPACE
268} // namespace simdpp
269
270#endif
271
272