1/*
2 * ACPI implementation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
9 *
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
17 *
18 * Contributions after 2012-01-13 are licensed under the terms of the
19 * GNU GPL, version 2 or (at your option) any later version.
20 */
21
22#include "qemu/osdep.h"
23#include "hw/i386/pc.h"
24#include "hw/irq.h"
25#include "hw/isa/apm.h"
26#include "hw/i2c/pm_smbus.h"
27#include "hw/pci/pci.h"
28#include "hw/qdev-properties.h"
29#include "hw/acpi/acpi.h"
30#include "sysemu/reset.h"
31#include "sysemu/runstate.h"
32#include "sysemu/sysemu.h"
33#include "qapi/error.h"
34#include "qemu/range.h"
35#include "exec/address-spaces.h"
36#include "hw/acpi/piix4.h"
37#include "hw/acpi/pcihp.h"
38#include "hw/acpi/cpu_hotplug.h"
39#include "hw/acpi/cpu.h"
40#include "hw/hotplug.h"
41#include "hw/mem/pc-dimm.h"
42#include "hw/acpi/memory_hotplug.h"
43#include "hw/acpi/acpi_dev_interface.h"
44#include "hw/xen/xen.h"
45#include "migration/qemu-file-types.h"
46#include "migration/vmstate.h"
47#include "hw/core/cpu.h"
48#include "trace.h"
49
50#define GPE_BASE 0xafe0
51#define GPE_LEN 4
52
53struct pci_status {
54 uint32_t up; /* deprecated, maintained for migration compatibility */
55 uint32_t down;
56};
57
58typedef struct PIIX4PMState {
59 /*< private >*/
60 PCIDevice parent_obj;
61 /*< public >*/
62
63 MemoryRegion io;
64 uint32_t io_base;
65
66 MemoryRegion io_gpe;
67 ACPIREGS ar;
68
69 APMState apm;
70
71 PMSMBus smb;
72 uint32_t smb_io_base;
73
74 qemu_irq irq;
75 qemu_irq smi_irq;
76 int smm_enabled;
77 Notifier machine_ready;
78 Notifier powerdown_notifier;
79
80 AcpiPciHpState acpi_pci_hotplug;
81 bool use_acpi_pci_hotplug;
82
83 uint8_t disable_s3;
84 uint8_t disable_s4;
85 uint8_t s4_val;
86
87 bool cpu_hotplug_legacy;
88 AcpiCpuHotplug gpe_cpu;
89 CPUHotplugState cpuhp_state;
90
91 MemHotplugState acpi_memory_hotplug;
92} PIIX4PMState;
93
94#define PIIX4_PM(obj) \
95 OBJECT_CHECK(PIIX4PMState, (obj), TYPE_PIIX4_PM)
96
97static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
98 PCIBus *bus, PIIX4PMState *s);
99
100#define ACPI_ENABLE 0xf1
101#define ACPI_DISABLE 0xf0
102
103static void pm_tmr_timer(ACPIREGS *ar)
104{
105 PIIX4PMState *s = container_of(ar, PIIX4PMState, ar);
106 acpi_update_sci(&s->ar, s->irq);
107}
108
109static void apm_ctrl_changed(uint32_t val, void *arg)
110{
111 PIIX4PMState *s = arg;
112 PCIDevice *d = PCI_DEVICE(s);
113
114 /* ACPI specs 3.0, 4.7.2.5 */
115 acpi_pm1_cnt_update(&s->ar, val == ACPI_ENABLE, val == ACPI_DISABLE);
116 if (val == ACPI_ENABLE || val == ACPI_DISABLE) {
117 return;
118 }
119
120 if (d->config[0x5b] & (1 << 1)) {
121 if (s->smi_irq) {
122 qemu_irq_raise(s->smi_irq);
123 }
124 }
125}
126
127static void pm_io_space_update(PIIX4PMState *s)
128{
129 PCIDevice *d = PCI_DEVICE(s);
130
131 s->io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x40));
132 s->io_base &= 0xffc0;
133
134 memory_region_transaction_begin();
135 memory_region_set_enabled(&s->io, d->config[0x80] & 1);
136 memory_region_set_address(&s->io, s->io_base);
137 memory_region_transaction_commit();
138}
139
140static void smbus_io_space_update(PIIX4PMState *s)
141{
142 PCIDevice *d = PCI_DEVICE(s);
143
144 s->smb_io_base = le32_to_cpu(*(uint32_t *)(d->config + 0x90));
145 s->smb_io_base &= 0xffc0;
146
147 memory_region_transaction_begin();
148 memory_region_set_enabled(&s->smb.io, d->config[0xd2] & 1);
149 memory_region_set_address(&s->smb.io, s->smb_io_base);
150 memory_region_transaction_commit();
151}
152
153static void pm_write_config(PCIDevice *d,
154 uint32_t address, uint32_t val, int len)
155{
156 pci_default_write_config(d, address, val, len);
157 if (range_covers_byte(address, len, 0x80) ||
158 ranges_overlap(address, len, 0x40, 4)) {
159 pm_io_space_update((PIIX4PMState *)d);
160 }
161 if (range_covers_byte(address, len, 0xd2) ||
162 ranges_overlap(address, len, 0x90, 4)) {
163 smbus_io_space_update((PIIX4PMState *)d);
164 }
165}
166
167static int vmstate_acpi_post_load(void *opaque, int version_id)
168{
169 PIIX4PMState *s = opaque;
170
171 pm_io_space_update(s);
172 smbus_io_space_update(s);
173 return 0;
174}
175
176#define VMSTATE_GPE_ARRAY(_field, _state) \
177 { \
178 .name = (stringify(_field)), \
179 .version_id = 0, \
180 .info = &vmstate_info_uint16, \
181 .size = sizeof(uint16_t), \
182 .flags = VMS_SINGLE | VMS_POINTER, \
183 .offset = vmstate_offset_pointer(_state, _field, uint8_t), \
184 }
185
186static const VMStateDescription vmstate_gpe = {
187 .name = "gpe",
188 .version_id = 1,
189 .minimum_version_id = 1,
190 .fields = (VMStateField[]) {
191 VMSTATE_GPE_ARRAY(sts, ACPIGPE),
192 VMSTATE_GPE_ARRAY(en, ACPIGPE),
193 VMSTATE_END_OF_LIST()
194 }
195};
196
197static const VMStateDescription vmstate_pci_status = {
198 .name = "pci_status",
199 .version_id = 1,
200 .minimum_version_id = 1,
201 .fields = (VMStateField[]) {
202 VMSTATE_UINT32(up, struct AcpiPciHpPciStatus),
203 VMSTATE_UINT32(down, struct AcpiPciHpPciStatus),
204 VMSTATE_END_OF_LIST()
205 }
206};
207
208static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
209{
210 PIIX4PMState *s = opaque;
211 int ret, i;
212 uint16_t temp;
213
214 ret = pci_device_load(PCI_DEVICE(s), f);
215 if (ret < 0) {
216 return ret;
217 }
218 qemu_get_be16s(f, &s->ar.pm1.evt.sts);
219 qemu_get_be16s(f, &s->ar.pm1.evt.en);
220 qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
221
222 ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
223 if (ret) {
224 return ret;
225 }
226
227 timer_get(f, s->ar.tmr.timer);
228 qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
229
230 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
231 for (i = 0; i < 3; i++) {
232 qemu_get_be16s(f, &temp);
233 }
234
235 qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
236 for (i = 0; i < 3; i++) {
237 qemu_get_be16s(f, &temp);
238 }
239
240 ret = vmstate_load_state(f, &vmstate_pci_status,
241 &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
242 return ret;
243}
244
245static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
246{
247 PIIX4PMState *s = opaque;
248 return s->use_acpi_pci_hotplug;
249}
250
251static bool vmstate_test_no_use_acpi_pci_hotplug(void *opaque, int version_id)
252{
253 PIIX4PMState *s = opaque;
254 return !s->use_acpi_pci_hotplug;
255}
256
257static bool vmstate_test_use_memhp(void *opaque)
258{
259 PIIX4PMState *s = opaque;
260 return s->acpi_memory_hotplug.is_enabled;
261}
262
263static const VMStateDescription vmstate_memhp_state = {
264 .name = "piix4_pm/memhp",
265 .version_id = 1,
266 .minimum_version_id = 1,
267 .minimum_version_id_old = 1,
268 .needed = vmstate_test_use_memhp,
269 .fields = (VMStateField[]) {
270 VMSTATE_MEMORY_HOTPLUG(acpi_memory_hotplug, PIIX4PMState),
271 VMSTATE_END_OF_LIST()
272 }
273};
274
275static bool vmstate_test_use_cpuhp(void *opaque)
276{
277 PIIX4PMState *s = opaque;
278 return !s->cpu_hotplug_legacy;
279}
280
281static int vmstate_cpuhp_pre_load(void *opaque)
282{
283 Object *obj = OBJECT(opaque);
284 object_property_set_bool(obj, false, "cpu-hotplug-legacy", &error_abort);
285 return 0;
286}
287
288static const VMStateDescription vmstate_cpuhp_state = {
289 .name = "piix4_pm/cpuhp",
290 .version_id = 1,
291 .minimum_version_id = 1,
292 .minimum_version_id_old = 1,
293 .needed = vmstate_test_use_cpuhp,
294 .pre_load = vmstate_cpuhp_pre_load,
295 .fields = (VMStateField[]) {
296 VMSTATE_CPU_HOTPLUG(cpuhp_state, PIIX4PMState),
297 VMSTATE_END_OF_LIST()
298 }
299};
300
301static bool piix4_vmstate_need_smbus(void *opaque, int version_id)
302{
303 return pm_smbus_vmstate_needed();
304}
305
306/* qemu-kvm 1.2 uses version 3 but advertised as 2
307 * To support incoming qemu-kvm 1.2 migration, change version_id
308 * and minimum_version_id to 2 below (which breaks migration from
309 * qemu 1.2).
310 *
311 */
312static const VMStateDescription vmstate_acpi = {
313 .name = "piix4_pm",
314 .version_id = 3,
315 .minimum_version_id = 3,
316 .minimum_version_id_old = 1,
317 .load_state_old = acpi_load_old,
318 .post_load = vmstate_acpi_post_load,
319 .fields = (VMStateField[]) {
320 VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
321 VMSTATE_UINT16(ar.pm1.evt.sts, PIIX4PMState),
322 VMSTATE_UINT16(ar.pm1.evt.en, PIIX4PMState),
323 VMSTATE_UINT16(ar.pm1.cnt.cnt, PIIX4PMState),
324 VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
325 VMSTATE_STRUCT_TEST(smb, PIIX4PMState, piix4_vmstate_need_smbus, 3,
326 pmsmb_vmstate, PMSMBus),
327 VMSTATE_TIMER_PTR(ar.tmr.timer, PIIX4PMState),
328 VMSTATE_INT64(ar.tmr.overflow_time, PIIX4PMState),
329 VMSTATE_STRUCT(ar.gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
330 VMSTATE_STRUCT_TEST(
331 acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT],
332 PIIX4PMState,
333 vmstate_test_no_use_acpi_pci_hotplug,
334 2, vmstate_pci_status,
335 struct AcpiPciHpPciStatus),
336 VMSTATE_PCI_HOTPLUG(acpi_pci_hotplug, PIIX4PMState,
337 vmstate_test_use_acpi_pci_hotplug),
338 VMSTATE_END_OF_LIST()
339 },
340 .subsections = (const VMStateDescription*[]) {
341 &vmstate_memhp_state,
342 &vmstate_cpuhp_state,
343 NULL
344 }
345};
346
347static void piix4_reset(void *opaque)
348{
349 PIIX4PMState *s = opaque;
350 PCIDevice *d = PCI_DEVICE(s);
351 uint8_t *pci_conf = d->config;
352
353 pci_conf[0x58] = 0;
354 pci_conf[0x59] = 0;
355 pci_conf[0x5a] = 0;
356 pci_conf[0x5b] = 0;
357
358 pci_conf[0x40] = 0x01; /* PM io base read only bit */
359 pci_conf[0x80] = 0;
360
361 if (!s->smm_enabled) {
362 /* Mark SMM as already inited (until KVM supports SMM). */
363 pci_conf[0x5B] = 0x02;
364 }
365 pm_io_space_update(s);
366 acpi_pcihp_reset(&s->acpi_pci_hotplug);
367}
368
369static void piix4_pm_powerdown_req(Notifier *n, void *opaque)
370{
371 PIIX4PMState *s = container_of(n, PIIX4PMState, powerdown_notifier);
372
373 assert(s != NULL);
374 acpi_pm1_evt_power_down(&s->ar);
375}
376
377static void piix4_device_pre_plug_cb(HotplugHandler *hotplug_dev,
378 DeviceState *dev, Error **errp)
379{
380 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
381
382 if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
383 acpi_pcihp_device_pre_plug_cb(hotplug_dev, dev, errp);
384 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
385 if (!s->acpi_memory_hotplug.is_enabled) {
386 error_setg(errp,
387 "memory hotplug is not enabled: %s.memory-hotplug-support "
388 "is not set", object_get_typename(OBJECT(s)));
389 }
390 } else if (
391 !object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
392 error_setg(errp, "acpi: device pre plug request for not supported"
393 " device type: %s", object_get_typename(OBJECT(dev)));
394 }
395}
396
397static void piix4_device_plug_cb(HotplugHandler *hotplug_dev,
398 DeviceState *dev, Error **errp)
399{
400 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
401
402 if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
403 if (object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM)) {
404 nvdimm_acpi_plug_cb(hotplug_dev, dev);
405 } else {
406 acpi_memory_plug_cb(hotplug_dev, &s->acpi_memory_hotplug,
407 dev, errp);
408 }
409 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
410 acpi_pcihp_device_plug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev, errp);
411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) {
412 if (s->cpu_hotplug_legacy) {
413 legacy_acpi_cpu_plug_cb(hotplug_dev, &s->gpe_cpu, dev, errp);
414 } else {
415 acpi_cpu_plug_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
416 }
417 } else {
418 g_assert_not_reached();
419 }
420}
421
422static void piix4_device_unplug_request_cb(HotplugHandler *hotplug_dev,
423 DeviceState *dev, Error **errp)
424{
425 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
426
427 if (s->acpi_memory_hotplug.is_enabled &&
428 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
429 acpi_memory_unplug_request_cb(hotplug_dev, &s->acpi_memory_hotplug,
430 dev, errp);
431 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
432 acpi_pcihp_device_unplug_request_cb(hotplug_dev, &s->acpi_pci_hotplug,
433 dev, errp);
434 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
435 !s->cpu_hotplug_legacy) {
436 acpi_cpu_unplug_request_cb(hotplug_dev, &s->cpuhp_state, dev, errp);
437 } else {
438 error_setg(errp, "acpi: device unplug request for not supported device"
439 " type: %s", object_get_typename(OBJECT(dev)));
440 }
441}
442
443static void piix4_device_unplug_cb(HotplugHandler *hotplug_dev,
444 DeviceState *dev, Error **errp)
445{
446 PIIX4PMState *s = PIIX4_PM(hotplug_dev);
447
448 if (s->acpi_memory_hotplug.is_enabled &&
449 object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
450 acpi_memory_unplug_cb(&s->acpi_memory_hotplug, dev, errp);
451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_DEVICE)) {
452 acpi_pcihp_device_unplug_cb(hotplug_dev, &s->acpi_pci_hotplug, dev,
453 errp);
454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) &&
455 !s->cpu_hotplug_legacy) {
456 acpi_cpu_unplug_cb(&s->cpuhp_state, dev, errp);
457 } else {
458 error_setg(errp, "acpi: device unplug for not supported device"
459 " type: %s", object_get_typename(OBJECT(dev)));
460 }
461}
462
463static void piix4_pm_machine_ready(Notifier *n, void *opaque)
464{
465 PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
466 PCIDevice *d = PCI_DEVICE(s);
467 MemoryRegion *io_as = pci_address_space_io(d);
468 uint8_t *pci_conf;
469
470 pci_conf = d->config;
471 pci_conf[0x5f] = 0x10 |
472 (memory_region_present(io_as, 0x378) ? 0x80 : 0);
473 pci_conf[0x63] = 0x60;
474 pci_conf[0x67] = (memory_region_present(io_as, 0x3f8) ? 0x08 : 0) |
475 (memory_region_present(io_as, 0x2f8) ? 0x90 : 0);
476}
477
478static void piix4_pm_add_propeties(PIIX4PMState *s)
479{
480 static const uint8_t acpi_enable_cmd = ACPI_ENABLE;
481 static const uint8_t acpi_disable_cmd = ACPI_DISABLE;
482 static const uint32_t gpe0_blk = GPE_BASE;
483 static const uint32_t gpe0_blk_len = GPE_LEN;
484 static const uint16_t sci_int = 9;
485
486 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_ENABLE_CMD,
487 &acpi_enable_cmd, NULL);
488 object_property_add_uint8_ptr(OBJECT(s), ACPI_PM_PROP_ACPI_DISABLE_CMD,
489 &acpi_disable_cmd, NULL);
490 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK,
491 &gpe0_blk, NULL);
492 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_GPE0_BLK_LEN,
493 &gpe0_blk_len, NULL);
494 object_property_add_uint16_ptr(OBJECT(s), ACPI_PM_PROP_SCI_INT,
495 &sci_int, NULL);
496 object_property_add_uint32_ptr(OBJECT(s), ACPI_PM_PROP_PM_IO_BASE,
497 &s->io_base, NULL);
498}
499
500static void piix4_pm_realize(PCIDevice *dev, Error **errp)
501{
502 PIIX4PMState *s = PIIX4_PM(dev);
503 uint8_t *pci_conf;
504
505 pci_conf = dev->config;
506 pci_conf[0x06] = 0x80;
507 pci_conf[0x07] = 0x02;
508 pci_conf[0x09] = 0x00;
509 pci_conf[0x3d] = 0x01; // interrupt pin 1
510
511 /* APM */
512 apm_init(dev, &s->apm, apm_ctrl_changed, s);
513
514 if (!s->smm_enabled) {
515 /* Mark SMM as already inited to prevent SMM from running. KVM does not
516 * support SMM mode. */
517 pci_conf[0x5B] = 0x02;
518 }
519
520 /* XXX: which specification is used ? The i82731AB has different
521 mappings */
522 pci_conf[0x90] = s->smb_io_base | 1;
523 pci_conf[0x91] = s->smb_io_base >> 8;
524 pci_conf[0xd2] = 0x09;
525 pm_smbus_init(DEVICE(dev), &s->smb, true);
526 memory_region_set_enabled(&s->smb.io, pci_conf[0xd2] & 1);
527 memory_region_add_subregion(pci_address_space_io(dev),
528 s->smb_io_base, &s->smb.io);
529
530 memory_region_init(&s->io, OBJECT(s), "piix4-pm", 64);
531 memory_region_set_enabled(&s->io, false);
532 memory_region_add_subregion(pci_address_space_io(dev),
533 0, &s->io);
534
535 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
536 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
537 acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val);
538 acpi_gpe_init(&s->ar, GPE_LEN);
539
540 s->powerdown_notifier.notify = piix4_pm_powerdown_req;
541 qemu_register_powerdown_notifier(&s->powerdown_notifier);
542
543 s->machine_ready.notify = piix4_pm_machine_ready;
544 qemu_add_machine_init_done_notifier(&s->machine_ready);
545 qemu_register_reset(piix4_reset, s);
546
547 piix4_acpi_system_hot_add_init(pci_address_space_io(dev),
548 pci_get_bus(dev), s);
549 qbus_set_hotplug_handler(BUS(pci_get_bus(dev)), OBJECT(s), &error_abort);
550
551 piix4_pm_add_propeties(s);
552}
553
554I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
555 qemu_irq sci_irq, qemu_irq smi_irq,
556 int smm_enabled, DeviceState **piix4_pm)
557{
558 DeviceState *dev;
559 PIIX4PMState *s;
560
561 dev = DEVICE(pci_create(bus, devfn, TYPE_PIIX4_PM));
562 qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
563 if (piix4_pm) {
564 *piix4_pm = dev;
565 }
566
567 s = PIIX4_PM(dev);
568 s->irq = sci_irq;
569 s->smi_irq = smi_irq;
570 s->smm_enabled = smm_enabled;
571 if (xen_enabled()) {
572 s->use_acpi_pci_hotplug = false;
573 }
574
575 qdev_init_nofail(dev);
576
577 return s->smb.smbus;
578}
579
580static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
581{
582 PIIX4PMState *s = opaque;
583 uint32_t val = acpi_gpe_ioport_readb(&s->ar, addr);
584
585 trace_piix4_gpe_readb(addr, width, val);
586 return val;
587}
588
589static void gpe_writeb(void *opaque, hwaddr addr, uint64_t val,
590 unsigned width)
591{
592 PIIX4PMState *s = opaque;
593
594 trace_piix4_gpe_writeb(addr, width, val);
595 acpi_gpe_ioport_writeb(&s->ar, addr, val);
596 acpi_update_sci(&s->ar, s->irq);
597}
598
599static const MemoryRegionOps piix4_gpe_ops = {
600 .read = gpe_readb,
601 .write = gpe_writeb,
602 .valid.min_access_size = 1,
603 .valid.max_access_size = 4,
604 .impl.min_access_size = 1,
605 .impl.max_access_size = 1,
606 .endianness = DEVICE_LITTLE_ENDIAN,
607};
608
609
610static bool piix4_get_cpu_hotplug_legacy(Object *obj, Error **errp)
611{
612 PIIX4PMState *s = PIIX4_PM(obj);
613
614 return s->cpu_hotplug_legacy;
615}
616
617static void piix4_set_cpu_hotplug_legacy(Object *obj, bool value, Error **errp)
618{
619 PIIX4PMState *s = PIIX4_PM(obj);
620
621 assert(!value);
622 if (s->cpu_hotplug_legacy && value == false) {
623 acpi_switch_to_modern_cphp(&s->gpe_cpu, &s->cpuhp_state,
624 PIIX4_CPU_HOTPLUG_IO_BASE);
625 }
626 s->cpu_hotplug_legacy = value;
627}
628
629static void piix4_acpi_system_hot_add_init(MemoryRegion *parent,
630 PCIBus *bus, PIIX4PMState *s)
631{
632 memory_region_init_io(&s->io_gpe, OBJECT(s), &piix4_gpe_ops, s,
633 "acpi-gpe0", GPE_LEN);
634 memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe);
635
636 acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent,
637 s->use_acpi_pci_hotplug);
638
639 s->cpu_hotplug_legacy = true;
640 object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy",
641 piix4_get_cpu_hotplug_legacy,
642 piix4_set_cpu_hotplug_legacy,
643 NULL);
644 legacy_acpi_cpu_hotplug_init(parent, OBJECT(s), &s->gpe_cpu,
645 PIIX4_CPU_HOTPLUG_IO_BASE);
646
647 if (s->acpi_memory_hotplug.is_enabled) {
648 acpi_memory_hotplug_init(parent, OBJECT(s), &s->acpi_memory_hotplug,
649 ACPI_MEMORY_HOTPLUG_BASE);
650 }
651}
652
653static void piix4_ospm_status(AcpiDeviceIf *adev, ACPIOSTInfoList ***list)
654{
655 PIIX4PMState *s = PIIX4_PM(adev);
656
657 acpi_memory_ospm_status(&s->acpi_memory_hotplug, list);
658 if (!s->cpu_hotplug_legacy) {
659 acpi_cpu_ospm_status(&s->cpuhp_state, list);
660 }
661}
662
663static void piix4_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
664{
665 PIIX4PMState *s = PIIX4_PM(adev);
666
667 acpi_send_gpe_event(&s->ar, s->irq, ev);
668}
669
670static Property piix4_pm_properties[] = {
671 DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
672 DEFINE_PROP_UINT8(ACPI_PM_PROP_S3_DISABLED, PIIX4PMState, disable_s3, 0),
673 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_DISABLED, PIIX4PMState, disable_s4, 0),
674 DEFINE_PROP_UINT8(ACPI_PM_PROP_S4_VAL, PIIX4PMState, s4_val, 2),
675 DEFINE_PROP_BOOL("acpi-pci-hotplug-with-bridge-support", PIIX4PMState,
676 use_acpi_pci_hotplug, true),
677 DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState,
678 acpi_memory_hotplug.is_enabled, true),
679 DEFINE_PROP_END_OF_LIST(),
680};
681
682static void piix4_pm_class_init(ObjectClass *klass, void *data)
683{
684 DeviceClass *dc = DEVICE_CLASS(klass);
685 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
686 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
687 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
688
689 k->realize = piix4_pm_realize;
690 k->config_write = pm_write_config;
691 k->vendor_id = PCI_VENDOR_ID_INTEL;
692 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_3;
693 k->revision = 0x03;
694 k->class_id = PCI_CLASS_BRIDGE_OTHER;
695 dc->desc = "PM";
696 dc->vmsd = &vmstate_acpi;
697 dc->props = piix4_pm_properties;
698 /*
699 * Reason: part of PIIX4 southbridge, needs to be wired up,
700 * e.g. by mips_malta_init()
701 */
702 dc->user_creatable = false;
703 dc->hotpluggable = false;
704 hc->pre_plug = piix4_device_pre_plug_cb;
705 hc->plug = piix4_device_plug_cb;
706 hc->unplug_request = piix4_device_unplug_request_cb;
707 hc->unplug = piix4_device_unplug_cb;
708 adevc->ospm_status = piix4_ospm_status;
709 adevc->send_event = piix4_send_gpe;
710 adevc->madt_cpu = pc_madt_cpu_entry;
711}
712
713static const TypeInfo piix4_pm_info = {
714 .name = TYPE_PIIX4_PM,
715 .parent = TYPE_PCI_DEVICE,
716 .instance_size = sizeof(PIIX4PMState),
717 .class_init = piix4_pm_class_init,
718 .interfaces = (InterfaceInfo[]) {
719 { TYPE_HOTPLUG_HANDLER },
720 { TYPE_ACPI_DEVICE_IF },
721 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
722 { }
723 }
724};
725
726static void piix4_pm_register_types(void)
727{
728 type_register_static(&piix4_pm_info);
729}
730
731type_init(piix4_pm_register_types)
732