1 | /* omap_sx1.c Support for the Siemens SX1 smartphone emulation. |
2 | * |
3 | * Copyright (C) 2008 |
4 | * Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> |
5 | * Copyright (C) 2007 Vladimir Ananiev <vovan888@gmail.com> |
6 | * |
7 | * based on PalmOne's (TM) PDAs support (palm.c) |
8 | */ |
9 | |
10 | /* |
11 | * PalmOne's (TM) PDAs. |
12 | * |
13 | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org> |
14 | * |
15 | * This program is free software; you can redistribute it and/or |
16 | * modify it under the terms of the GNU General Public License as |
17 | * published by the Free Software Foundation; either version 2 of |
18 | * the License, or (at your option) any later version. |
19 | * |
20 | * This program is distributed in the hope that it will be useful, |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
23 | * GNU General Public License for more details. |
24 | * |
25 | * You should have received a copy of the GNU General Public License along |
26 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
27 | */ |
28 | #include "qemu/osdep.h" |
29 | #include "qapi/error.h" |
30 | #include "ui/console.h" |
31 | #include "hw/arm/omap.h" |
32 | #include "hw/boards.h" |
33 | #include "hw/arm/boot.h" |
34 | #include "hw/block/flash.h" |
35 | #include "sysemu/qtest.h" |
36 | #include "exec/address-spaces.h" |
37 | #include "cpu.h" |
38 | |
39 | /*****************************************************************************/ |
40 | /* Siemens SX1 Cellphone V1 */ |
41 | /* - ARM OMAP310 processor |
42 | * - SRAM 192 kB |
43 | * - SDRAM 32 MB at 0x10000000 |
44 | * - Boot flash 16 MB at 0x00000000 |
45 | * - Application flash 8 MB at 0x04000000 |
46 | * - 3 serial ports |
47 | * - 1 SecureDigital |
48 | * - 1 LCD display |
49 | * - 1 RTC |
50 | */ |
51 | |
52 | /*****************************************************************************/ |
53 | /* Siemens SX1 Cellphone V2 */ |
54 | /* - ARM OMAP310 processor |
55 | * - SRAM 192 kB |
56 | * - SDRAM 32 MB at 0x10000000 |
57 | * - Boot flash 32 MB at 0x00000000 |
58 | * - 3 serial ports |
59 | * - 1 SecureDigital |
60 | * - 1 LCD display |
61 | * - 1 RTC |
62 | */ |
63 | |
64 | static uint64_t static_read(void *opaque, hwaddr offset, |
65 | unsigned size) |
66 | { |
67 | uint32_t *val = (uint32_t *) opaque; |
68 | uint32_t mask = (4 / size) - 1; |
69 | |
70 | return *val >> ((offset & mask) << 3); |
71 | } |
72 | |
73 | static void static_write(void *opaque, hwaddr offset, |
74 | uint64_t value, unsigned size) |
75 | { |
76 | #ifdef SPY |
77 | printf("%s: value %" PRIx64 " %u bytes written at 0x%x\n" , |
78 | __func__, value, size, (int)offset); |
79 | #endif |
80 | } |
81 | |
82 | static const MemoryRegionOps static_ops = { |
83 | .read = static_read, |
84 | .write = static_write, |
85 | .endianness = DEVICE_NATIVE_ENDIAN, |
86 | }; |
87 | |
88 | #define sdram_size 0x02000000 |
89 | #define sector_size (128 * 1024) |
90 | #define flash0_size (16 * 1024 * 1024) |
91 | #define flash1_size ( 8 * 1024 * 1024) |
92 | #define flash2_size (32 * 1024 * 1024) |
93 | #define total_ram_v1 (sdram_size + flash0_size + flash1_size + OMAP15XX_SRAM_SIZE) |
94 | #define total_ram_v2 (sdram_size + flash2_size + OMAP15XX_SRAM_SIZE) |
95 | |
96 | static struct arm_boot_info sx1_binfo = { |
97 | .loader_start = OMAP_EMIFF_BASE, |
98 | .ram_size = sdram_size, |
99 | .board_id = 0x265, |
100 | }; |
101 | |
102 | static void sx1_init(MachineState *machine, const int version) |
103 | { |
104 | struct omap_mpu_state_s *mpu; |
105 | MemoryRegion *address_space = get_system_memory(); |
106 | MemoryRegion *flash = g_new(MemoryRegion, 1); |
107 | MemoryRegion *cs = g_new(MemoryRegion, 4); |
108 | static uint32_t cs0val = 0x00213090; |
109 | static uint32_t cs1val = 0x00215070; |
110 | static uint32_t cs2val = 0x00001139; |
111 | static uint32_t cs3val = 0x00001139; |
112 | DriveInfo *dinfo; |
113 | int fl_idx; |
114 | uint32_t flash_size = flash0_size; |
115 | int be; |
116 | |
117 | if (version == 2) { |
118 | flash_size = flash2_size; |
119 | } |
120 | |
121 | mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, |
122 | machine->cpu_type); |
123 | |
124 | /* External Flash (EMIFS) */ |
125 | memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0" , flash_size, |
126 | &error_fatal); |
127 | memory_region_set_readonly(flash, true); |
128 | memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash); |
129 | |
130 | memory_region_init_io(&cs[0], NULL, &static_ops, &cs0val, |
131 | "sx1.cs0" , OMAP_CS0_SIZE - flash_size); |
132 | memory_region_add_subregion(address_space, |
133 | OMAP_CS0_BASE + flash_size, &cs[0]); |
134 | |
135 | |
136 | memory_region_init_io(&cs[2], NULL, &static_ops, &cs2val, |
137 | "sx1.cs2" , OMAP_CS2_SIZE); |
138 | memory_region_add_subregion(address_space, |
139 | OMAP_CS2_BASE, &cs[2]); |
140 | |
141 | memory_region_init_io(&cs[3], NULL, &static_ops, &cs3val, |
142 | "sx1.cs3" , OMAP_CS3_SIZE); |
143 | memory_region_add_subregion(address_space, |
144 | OMAP_CS2_BASE, &cs[3]); |
145 | |
146 | fl_idx = 0; |
147 | #ifdef TARGET_WORDS_BIGENDIAN |
148 | be = 1; |
149 | #else |
150 | be = 0; |
151 | #endif |
152 | |
153 | if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { |
154 | if (!pflash_cfi01_register(OMAP_CS0_BASE, |
155 | "omap_sx1.flash0-1" , flash_size, |
156 | blk_by_legacy_dinfo(dinfo), |
157 | sector_size, 4, 0, 0, 0, 0, be)) { |
158 | fprintf(stderr, "qemu: Error registering flash memory %d.\n" , |
159 | fl_idx); |
160 | } |
161 | fl_idx++; |
162 | } |
163 | |
164 | if ((version == 1) && |
165 | (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { |
166 | MemoryRegion *flash_1 = g_new(MemoryRegion, 1); |
167 | memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0" , |
168 | flash1_size, &error_fatal); |
169 | memory_region_set_readonly(flash_1, true); |
170 | memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1); |
171 | |
172 | memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, |
173 | "sx1.cs1" , OMAP_CS1_SIZE - flash1_size); |
174 | memory_region_add_subregion(address_space, |
175 | OMAP_CS1_BASE + flash1_size, &cs[1]); |
176 | |
177 | if (!pflash_cfi01_register(OMAP_CS1_BASE, |
178 | "omap_sx1.flash1-1" , flash1_size, |
179 | blk_by_legacy_dinfo(dinfo), |
180 | sector_size, 4, 0, 0, 0, 0, be)) { |
181 | fprintf(stderr, "qemu: Error registering flash memory %d.\n" , |
182 | fl_idx); |
183 | } |
184 | fl_idx++; |
185 | } else { |
186 | memory_region_init_io(&cs[1], NULL, &static_ops, &cs1val, |
187 | "sx1.cs1" , OMAP_CS1_SIZE); |
188 | memory_region_add_subregion(address_space, |
189 | OMAP_CS1_BASE, &cs[1]); |
190 | } |
191 | |
192 | if (!machine->kernel_filename && !fl_idx && !qtest_enabled()) { |
193 | error_report("Kernel or Flash image must be specified" ); |
194 | exit(1); |
195 | } |
196 | |
197 | /* Load the kernel. */ |
198 | arm_load_kernel(mpu->cpu, machine, &sx1_binfo); |
199 | |
200 | /* TODO: fix next line */ |
201 | //~ qemu_console_resize(ds, 640, 480); |
202 | } |
203 | |
204 | static void sx1_init_v1(MachineState *machine) |
205 | { |
206 | sx1_init(machine, 1); |
207 | } |
208 | |
209 | static void sx1_init_v2(MachineState *machine) |
210 | { |
211 | sx1_init(machine, 2); |
212 | } |
213 | |
214 | static void sx1_machine_v2_class_init(ObjectClass *oc, void *data) |
215 | { |
216 | MachineClass *mc = MACHINE_CLASS(oc); |
217 | |
218 | mc->desc = "Siemens SX1 (OMAP310) V2" ; |
219 | mc->init = sx1_init_v2; |
220 | mc->ignore_memory_transaction_failures = true; |
221 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t" ); |
222 | } |
223 | |
224 | static const TypeInfo sx1_machine_v2_type = { |
225 | .name = MACHINE_TYPE_NAME("sx1" ), |
226 | .parent = TYPE_MACHINE, |
227 | .class_init = sx1_machine_v2_class_init, |
228 | }; |
229 | |
230 | static void sx1_machine_v1_class_init(ObjectClass *oc, void *data) |
231 | { |
232 | MachineClass *mc = MACHINE_CLASS(oc); |
233 | |
234 | mc->desc = "Siemens SX1 (OMAP310) V1" ; |
235 | mc->init = sx1_init_v1; |
236 | mc->ignore_memory_transaction_failures = true; |
237 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("ti925t" ); |
238 | } |
239 | |
240 | static const TypeInfo sx1_machine_v1_type = { |
241 | .name = MACHINE_TYPE_NAME("sx1-v1" ), |
242 | .parent = TYPE_MACHINE, |
243 | .class_init = sx1_machine_v1_class_init, |
244 | }; |
245 | |
246 | static void sx1_machine_init(void) |
247 | { |
248 | type_register_static(&sx1_machine_v1_type); |
249 | type_register_static(&sx1_machine_v2_type); |
250 | } |
251 | |
252 | type_init(sx1_machine_init) |
253 | |