1 | /* |
2 | * ARM RealView Baseboard System emulation. |
3 | * |
4 | * Copyright (c) 2006-2007 CodeSourcery. |
5 | * Written by Paul Brook |
6 | * |
7 | * This code is licensed under the GPL. |
8 | */ |
9 | |
10 | #include "qemu/osdep.h" |
11 | #include "qapi/error.h" |
12 | #include "cpu.h" |
13 | #include "hw/sysbus.h" |
14 | #include "hw/arm/boot.h" |
15 | #include "hw/arm/primecell.h" |
16 | #include "hw/net/lan9118.h" |
17 | #include "hw/net/smc91c111.h" |
18 | #include "hw/pci/pci.h" |
19 | #include "net/net.h" |
20 | #include "sysemu/sysemu.h" |
21 | #include "hw/boards.h" |
22 | #include "hw/i2c/i2c.h" |
23 | #include "exec/address-spaces.h" |
24 | #include "qemu/error-report.h" |
25 | #include "hw/char/pl011.h" |
26 | #include "hw/cpu/a9mpcore.h" |
27 | #include "hw/intc/realview_gic.h" |
28 | #include "hw/irq.h" |
29 | |
30 | #define SMP_BOOT_ADDR 0xe0000000 |
31 | #define SMP_BOOTREG_ADDR 0x10000030 |
32 | |
33 | /* Board init. */ |
34 | |
35 | static struct arm_boot_info realview_binfo = { |
36 | .smp_loader_start = SMP_BOOT_ADDR, |
37 | .smp_bootreg_addr = SMP_BOOTREG_ADDR, |
38 | }; |
39 | |
40 | /* The following two lists must be consistent. */ |
41 | enum realview_board_type { |
42 | BOARD_EB, |
43 | BOARD_EB_MPCORE, |
44 | BOARD_PB_A8, |
45 | BOARD_PBX_A9, |
46 | }; |
47 | |
48 | static const int realview_board_id[] = { |
49 | 0x33b, |
50 | 0x33b, |
51 | 0x769, |
52 | 0x76d |
53 | }; |
54 | |
55 | static void realview_init(MachineState *machine, |
56 | enum realview_board_type board_type) |
57 | { |
58 | ARMCPU *cpu = NULL; |
59 | CPUARMState *env; |
60 | MemoryRegion *sysmem = get_system_memory(); |
61 | MemoryRegion *ram_lo; |
62 | MemoryRegion *ram_hi = g_new(MemoryRegion, 1); |
63 | MemoryRegion *ram_alias = g_new(MemoryRegion, 1); |
64 | MemoryRegion *ram_hack = g_new(MemoryRegion, 1); |
65 | DeviceState *dev, *sysctl, *gpio2, *pl041; |
66 | SysBusDevice *busdev; |
67 | qemu_irq pic[64]; |
68 | qemu_irq mmc_irq[2]; |
69 | PCIBus *pci_bus = NULL; |
70 | NICInfo *nd; |
71 | I2CBus *i2c; |
72 | int n; |
73 | unsigned int smp_cpus = machine->smp.cpus; |
74 | int done_nic = 0; |
75 | qemu_irq cpu_irq[4]; |
76 | int is_mpcore = 0; |
77 | int is_pb = 0; |
78 | uint32_t proc_id = 0; |
79 | uint32_t sys_id; |
80 | ram_addr_t low_ram_size; |
81 | ram_addr_t ram_size = machine->ram_size; |
82 | hwaddr periphbase = 0; |
83 | |
84 | switch (board_type) { |
85 | case BOARD_EB: |
86 | break; |
87 | case BOARD_EB_MPCORE: |
88 | is_mpcore = 1; |
89 | periphbase = 0x10100000; |
90 | break; |
91 | case BOARD_PB_A8: |
92 | is_pb = 1; |
93 | break; |
94 | case BOARD_PBX_A9: |
95 | is_mpcore = 1; |
96 | is_pb = 1; |
97 | periphbase = 0x1f000000; |
98 | break; |
99 | } |
100 | |
101 | for (n = 0; n < smp_cpus; n++) { |
102 | Object *cpuobj = object_new(machine->cpu_type); |
103 | |
104 | /* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board |
105 | * does not currently support EL3 so the CPU EL3 property is disabled |
106 | * before realization. |
107 | */ |
108 | if (object_property_find(cpuobj, "has_el3" , NULL)) { |
109 | object_property_set_bool(cpuobj, false, "has_el3" , &error_fatal); |
110 | } |
111 | |
112 | if (is_pb && is_mpcore) { |
113 | object_property_set_int(cpuobj, periphbase, "reset-cbar" , |
114 | &error_fatal); |
115 | } |
116 | |
117 | object_property_set_bool(cpuobj, true, "realized" , &error_fatal); |
118 | |
119 | cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ); |
120 | } |
121 | cpu = ARM_CPU(first_cpu); |
122 | env = &cpu->env; |
123 | if (arm_feature(env, ARM_FEATURE_V7)) { |
124 | if (is_mpcore) { |
125 | proc_id = 0x0c000000; |
126 | } else { |
127 | proc_id = 0x0e000000; |
128 | } |
129 | } else if (arm_feature(env, ARM_FEATURE_V6K)) { |
130 | proc_id = 0x06000000; |
131 | } else if (arm_feature(env, ARM_FEATURE_V6)) { |
132 | proc_id = 0x04000000; |
133 | } else { |
134 | proc_id = 0x02000000; |
135 | } |
136 | |
137 | if (is_pb && ram_size > 0x20000000) { |
138 | /* Core tile RAM. */ |
139 | ram_lo = g_new(MemoryRegion, 1); |
140 | low_ram_size = ram_size - 0x20000000; |
141 | ram_size = 0x20000000; |
142 | memory_region_init_ram(ram_lo, NULL, "realview.lowmem" , low_ram_size, |
143 | &error_fatal); |
144 | memory_region_add_subregion(sysmem, 0x20000000, ram_lo); |
145 | } |
146 | |
147 | memory_region_init_ram(ram_hi, NULL, "realview.highmem" , ram_size, |
148 | &error_fatal); |
149 | low_ram_size = ram_size; |
150 | if (low_ram_size > 0x10000000) |
151 | low_ram_size = 0x10000000; |
152 | /* SDRAM at address zero. */ |
153 | memory_region_init_alias(ram_alias, NULL, "realview.alias" , |
154 | ram_hi, 0, low_ram_size); |
155 | memory_region_add_subregion(sysmem, 0, ram_alias); |
156 | if (is_pb) { |
157 | /* And again at a high address. */ |
158 | memory_region_add_subregion(sysmem, 0x70000000, ram_hi); |
159 | } else { |
160 | ram_size = low_ram_size; |
161 | } |
162 | |
163 | sys_id = is_pb ? 0x01780500 : 0xc1400400; |
164 | sysctl = qdev_create(NULL, "realview_sysctl" ); |
165 | qdev_prop_set_uint32(sysctl, "sys_id" , sys_id); |
166 | qdev_prop_set_uint32(sysctl, "proc_id" , proc_id); |
167 | qdev_init_nofail(sysctl); |
168 | sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, 0x10000000); |
169 | |
170 | if (is_mpcore) { |
171 | dev = qdev_create(NULL, is_pb ? TYPE_A9MPCORE_PRIV : "realview_mpcore" ); |
172 | qdev_prop_set_uint32(dev, "num-cpu" , smp_cpus); |
173 | qdev_init_nofail(dev); |
174 | busdev = SYS_BUS_DEVICE(dev); |
175 | sysbus_mmio_map(busdev, 0, periphbase); |
176 | for (n = 0; n < smp_cpus; n++) { |
177 | sysbus_connect_irq(busdev, n, cpu_irq[n]); |
178 | } |
179 | sysbus_create_varargs("l2x0" , periphbase + 0x2000, NULL); |
180 | /* Both A9 and 11MPCore put the GIC CPU i/f at base + 0x100 */ |
181 | realview_binfo.gic_cpu_if_addr = periphbase + 0x100; |
182 | } else { |
183 | uint32_t gic_addr = is_pb ? 0x1e000000 : 0x10040000; |
184 | /* For now just create the nIRQ GIC, and ignore the others. */ |
185 | dev = sysbus_create_simple(TYPE_REALVIEW_GIC, gic_addr, cpu_irq[0]); |
186 | } |
187 | for (n = 0; n < 64; n++) { |
188 | pic[n] = qdev_get_gpio_in(dev, n); |
189 | } |
190 | |
191 | pl041 = qdev_create(NULL, "pl041" ); |
192 | qdev_prop_set_uint32(pl041, "nc_fifo_depth" , 512); |
193 | qdev_init_nofail(pl041); |
194 | sysbus_mmio_map(SYS_BUS_DEVICE(pl041), 0, 0x10004000); |
195 | sysbus_connect_irq(SYS_BUS_DEVICE(pl041), 0, pic[19]); |
196 | |
197 | sysbus_create_simple("pl050_keyboard" , 0x10006000, pic[20]); |
198 | sysbus_create_simple("pl050_mouse" , 0x10007000, pic[21]); |
199 | |
200 | pl011_create(0x10009000, pic[12], serial_hd(0)); |
201 | pl011_create(0x1000a000, pic[13], serial_hd(1)); |
202 | pl011_create(0x1000b000, pic[14], serial_hd(2)); |
203 | pl011_create(0x1000c000, pic[15], serial_hd(3)); |
204 | |
205 | /* DMA controller is optional, apparently. */ |
206 | dev = qdev_create(NULL, "pl081" ); |
207 | object_property_set_link(OBJECT(dev), OBJECT(sysmem), "downstream" , |
208 | &error_fatal); |
209 | qdev_init_nofail(dev); |
210 | busdev = SYS_BUS_DEVICE(dev); |
211 | sysbus_mmio_map(busdev, 0, 0x10030000); |
212 | sysbus_connect_irq(busdev, 0, pic[24]); |
213 | |
214 | sysbus_create_simple("sp804" , 0x10011000, pic[4]); |
215 | sysbus_create_simple("sp804" , 0x10012000, pic[5]); |
216 | |
217 | sysbus_create_simple("pl061" , 0x10013000, pic[6]); |
218 | sysbus_create_simple("pl061" , 0x10014000, pic[7]); |
219 | gpio2 = sysbus_create_simple("pl061" , 0x10015000, pic[8]); |
220 | |
221 | sysbus_create_simple("pl111" , 0x10020000, pic[23]); |
222 | |
223 | dev = sysbus_create_varargs("pl181" , 0x10005000, pic[17], pic[18], NULL); |
224 | /* Wire up MMC card detect and read-only signals. These have |
225 | * to go to both the PL061 GPIO and the sysctl register. |
226 | * Note that the PL181 orders these lines (readonly,inserted) |
227 | * and the PL061 has them the other way about. Also the card |
228 | * detect line is inverted. |
229 | */ |
230 | mmc_irq[0] = qemu_irq_split( |
231 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), |
232 | qdev_get_gpio_in(gpio2, 1)); |
233 | mmc_irq[1] = qemu_irq_split( |
234 | qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), |
235 | qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); |
236 | qdev_connect_gpio_out(dev, 0, mmc_irq[0]); |
237 | qdev_connect_gpio_out(dev, 1, mmc_irq[1]); |
238 | |
239 | sysbus_create_simple("pl031" , 0x10017000, pic[10]); |
240 | |
241 | if (!is_pb) { |
242 | dev = qdev_create(NULL, "realview_pci" ); |
243 | busdev = SYS_BUS_DEVICE(dev); |
244 | qdev_init_nofail(dev); |
245 | sysbus_mmio_map(busdev, 0, 0x10019000); /* PCI controller registers */ |
246 | sysbus_mmio_map(busdev, 1, 0x60000000); /* PCI self-config */ |
247 | sysbus_mmio_map(busdev, 2, 0x61000000); /* PCI config */ |
248 | sysbus_mmio_map(busdev, 3, 0x62000000); /* PCI I/O */ |
249 | sysbus_mmio_map(busdev, 4, 0x63000000); /* PCI memory window 1 */ |
250 | sysbus_mmio_map(busdev, 5, 0x64000000); /* PCI memory window 2 */ |
251 | sysbus_mmio_map(busdev, 6, 0x68000000); /* PCI memory window 3 */ |
252 | sysbus_connect_irq(busdev, 0, pic[48]); |
253 | sysbus_connect_irq(busdev, 1, pic[49]); |
254 | sysbus_connect_irq(busdev, 2, pic[50]); |
255 | sysbus_connect_irq(busdev, 3, pic[51]); |
256 | pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci" ); |
257 | if (machine_usb(machine)) { |
258 | pci_create_simple(pci_bus, -1, "pci-ohci" ); |
259 | } |
260 | n = drive_get_max_bus(IF_SCSI); |
261 | while (n >= 0) { |
262 | dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a" )); |
263 | lsi53c8xx_handle_legacy_cmdline(dev); |
264 | n--; |
265 | } |
266 | } |
267 | for(n = 0; n < nb_nics; n++) { |
268 | nd = &nd_table[n]; |
269 | |
270 | if (!done_nic && (!nd->model || |
271 | strcmp(nd->model, is_pb ? "lan9118" : "smc91c111" ) == 0)) { |
272 | if (is_pb) { |
273 | lan9118_init(nd, 0x4e000000, pic[28]); |
274 | } else { |
275 | smc91c111_init(nd, 0x4e000000, pic[28]); |
276 | } |
277 | done_nic = 1; |
278 | } else { |
279 | if (pci_bus) { |
280 | pci_nic_init_nofail(nd, pci_bus, "rtl8139" , NULL); |
281 | } |
282 | } |
283 | } |
284 | |
285 | dev = sysbus_create_simple("versatile_i2c" , 0x10002000, NULL); |
286 | i2c = (I2CBus *)qdev_get_child_bus(dev, "i2c" ); |
287 | i2c_create_slave(i2c, "ds1338" , 0x68); |
288 | |
289 | /* Memory map for RealView Emulation Baseboard: */ |
290 | /* 0x10000000 System registers. */ |
291 | /* 0x10001000 System controller. */ |
292 | /* 0x10002000 Two-Wire Serial Bus. */ |
293 | /* 0x10003000 Reserved. */ |
294 | /* 0x10004000 AACI. */ |
295 | /* 0x10005000 MCI. */ |
296 | /* 0x10006000 KMI0. */ |
297 | /* 0x10007000 KMI1. */ |
298 | /* 0x10008000 Character LCD. (EB) */ |
299 | /* 0x10009000 UART0. */ |
300 | /* 0x1000a000 UART1. */ |
301 | /* 0x1000b000 UART2. */ |
302 | /* 0x1000c000 UART3. */ |
303 | /* 0x1000d000 SSPI. */ |
304 | /* 0x1000e000 SCI. */ |
305 | /* 0x1000f000 Reserved. */ |
306 | /* 0x10010000 Watchdog. */ |
307 | /* 0x10011000 Timer 0+1. */ |
308 | /* 0x10012000 Timer 2+3. */ |
309 | /* 0x10013000 GPIO 0. */ |
310 | /* 0x10014000 GPIO 1. */ |
311 | /* 0x10015000 GPIO 2. */ |
312 | /* 0x10002000 Two-Wire Serial Bus - DVI. (PB) */ |
313 | /* 0x10017000 RTC. */ |
314 | /* 0x10018000 DMC. */ |
315 | /* 0x10019000 PCI controller config. */ |
316 | /* 0x10020000 CLCD. */ |
317 | /* 0x10030000 DMA Controller. */ |
318 | /* 0x10040000 GIC1. (EB) */ |
319 | /* 0x10050000 GIC2. (EB) */ |
320 | /* 0x10060000 GIC3. (EB) */ |
321 | /* 0x10070000 GIC4. (EB) */ |
322 | /* 0x10080000 SMC. */ |
323 | /* 0x1e000000 GIC1. (PB) */ |
324 | /* 0x1e001000 GIC2. (PB) */ |
325 | /* 0x1e002000 GIC3. (PB) */ |
326 | /* 0x1e003000 GIC4. (PB) */ |
327 | /* 0x40000000 NOR flash. */ |
328 | /* 0x44000000 DoC flash. */ |
329 | /* 0x48000000 SRAM. */ |
330 | /* 0x4c000000 Configuration flash. */ |
331 | /* 0x4e000000 Ethernet. */ |
332 | /* 0x4f000000 USB. */ |
333 | /* 0x50000000 PISMO. */ |
334 | /* 0x54000000 PISMO. */ |
335 | /* 0x58000000 PISMO. */ |
336 | /* 0x5c000000 PISMO. */ |
337 | /* 0x60000000 PCI. */ |
338 | /* 0x60000000 PCI Self Config. */ |
339 | /* 0x61000000 PCI Config. */ |
340 | /* 0x62000000 PCI IO. */ |
341 | /* 0x63000000 PCI mem 0. */ |
342 | /* 0x64000000 PCI mem 1. */ |
343 | /* 0x68000000 PCI mem 2. */ |
344 | |
345 | /* ??? Hack to map an additional page of ram for the secondary CPU |
346 | startup code. I guess this works on real hardware because the |
347 | BootROM happens to be in ROM/flash or in memory that isn't clobbered |
348 | until after Linux boots the secondary CPUs. */ |
349 | memory_region_init_ram(ram_hack, NULL, "realview.hack" , 0x1000, |
350 | &error_fatal); |
351 | memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); |
352 | |
353 | realview_binfo.ram_size = ram_size; |
354 | realview_binfo.nb_cpus = smp_cpus; |
355 | realview_binfo.board_id = realview_board_id[board_type]; |
356 | realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); |
357 | arm_load_kernel(ARM_CPU(first_cpu), machine, &realview_binfo); |
358 | } |
359 | |
360 | static void realview_eb_init(MachineState *machine) |
361 | { |
362 | realview_init(machine, BOARD_EB); |
363 | } |
364 | |
365 | static void realview_eb_mpcore_init(MachineState *machine) |
366 | { |
367 | realview_init(machine, BOARD_EB_MPCORE); |
368 | } |
369 | |
370 | static void realview_pb_a8_init(MachineState *machine) |
371 | { |
372 | realview_init(machine, BOARD_PB_A8); |
373 | } |
374 | |
375 | static void realview_pbx_a9_init(MachineState *machine) |
376 | { |
377 | realview_init(machine, BOARD_PBX_A9); |
378 | } |
379 | |
380 | static void realview_eb_class_init(ObjectClass *oc, void *data) |
381 | { |
382 | MachineClass *mc = MACHINE_CLASS(oc); |
383 | |
384 | mc->desc = "ARM RealView Emulation Baseboard (ARM926EJ-S)" ; |
385 | mc->init = realview_eb_init; |
386 | mc->block_default_type = IF_SCSI; |
387 | mc->ignore_memory_transaction_failures = true; |
388 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926" ); |
389 | } |
390 | |
391 | static const TypeInfo realview_eb_type = { |
392 | .name = MACHINE_TYPE_NAME("realview-eb" ), |
393 | .parent = TYPE_MACHINE, |
394 | .class_init = realview_eb_class_init, |
395 | }; |
396 | |
397 | static void realview_eb_mpcore_class_init(ObjectClass *oc, void *data) |
398 | { |
399 | MachineClass *mc = MACHINE_CLASS(oc); |
400 | |
401 | mc->desc = "ARM RealView Emulation Baseboard (ARM11MPCore)" ; |
402 | mc->init = realview_eb_mpcore_init; |
403 | mc->block_default_type = IF_SCSI; |
404 | mc->max_cpus = 4; |
405 | mc->ignore_memory_transaction_failures = true; |
406 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm11mpcore" ); |
407 | } |
408 | |
409 | static const TypeInfo realview_eb_mpcore_type = { |
410 | .name = MACHINE_TYPE_NAME("realview-eb-mpcore" ), |
411 | .parent = TYPE_MACHINE, |
412 | .class_init = realview_eb_mpcore_class_init, |
413 | }; |
414 | |
415 | static void realview_pb_a8_class_init(ObjectClass *oc, void *data) |
416 | { |
417 | MachineClass *mc = MACHINE_CLASS(oc); |
418 | |
419 | mc->desc = "ARM RealView Platform Baseboard for Cortex-A8" ; |
420 | mc->init = realview_pb_a8_init; |
421 | mc->ignore_memory_transaction_failures = true; |
422 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a8" ); |
423 | } |
424 | |
425 | static const TypeInfo realview_pb_a8_type = { |
426 | .name = MACHINE_TYPE_NAME("realview-pb-a8" ), |
427 | .parent = TYPE_MACHINE, |
428 | .class_init = realview_pb_a8_class_init, |
429 | }; |
430 | |
431 | static void realview_pbx_a9_class_init(ObjectClass *oc, void *data) |
432 | { |
433 | MachineClass *mc = MACHINE_CLASS(oc); |
434 | |
435 | mc->desc = "ARM RealView Platform Baseboard Explore for Cortex-A9" ; |
436 | mc->init = realview_pbx_a9_init; |
437 | mc->max_cpus = 4; |
438 | mc->ignore_memory_transaction_failures = true; |
439 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9" ); |
440 | } |
441 | |
442 | static const TypeInfo realview_pbx_a9_type = { |
443 | .name = MACHINE_TYPE_NAME("realview-pbx-a9" ), |
444 | .parent = TYPE_MACHINE, |
445 | .class_init = realview_pbx_a9_class_init, |
446 | }; |
447 | |
448 | static void realview_machine_init(void) |
449 | { |
450 | type_register_static(&realview_eb_type); |
451 | type_register_static(&realview_eb_mpcore_type); |
452 | type_register_static(&realview_pb_a8_type); |
453 | type_register_static(&realview_pbx_a9_type); |
454 | } |
455 | |
456 | type_init(realview_machine_init) |
457 | |