1/*
2 * ARM mach-virt emulation
3 *
4 * Copyright (c) 2013 Linaro Limited
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * Emulate a virtual board which works by passing Linux all the information
19 * it needs about what devices are present via the device tree.
20 * There are some restrictions about what we can do here:
21 * + we can only present devices whose Linux drivers will work based
22 * purely on the device tree with no platform data at all
23 * + we want to present a very stripped-down minimalist platform,
24 * both because this reduces the security attack surface from the guest
25 * and also because it reduces our exposure to being broken when
26 * the kernel updates its device tree bindings and requires further
27 * information in a device binding that we aren't providing.
28 * This is essentially the same approach kvmtool uses.
29 */
30
31#include "qemu/osdep.h"
32#include "qemu-common.h"
33#include "qemu/units.h"
34#include "qemu/option.h"
35#include "qapi/error.h"
36#include "hw/sysbus.h"
37#include "hw/boards.h"
38#include "hw/arm/boot.h"
39#include "hw/arm/primecell.h"
40#include "hw/arm/virt.h"
41#include "hw/block/flash.h"
42#include "hw/vfio/vfio-calxeda-xgmac.h"
43#include "hw/vfio/vfio-amd-xgbe.h"
44#include "hw/display/ramfb.h"
45#include "net/net.h"
46#include "sysemu/device_tree.h"
47#include "sysemu/numa.h"
48#include "sysemu/runstate.h"
49#include "sysemu/sysemu.h"
50#include "sysemu/kvm.h"
51#include "hw/loader.h"
52#include "exec/address-spaces.h"
53#include "qemu/bitops.h"
54#include "qemu/error-report.h"
55#include "qemu/module.h"
56#include "hw/pci-host/gpex.h"
57#include "hw/arm/sysbus-fdt.h"
58#include "hw/platform-bus.h"
59#include "hw/qdev-properties.h"
60#include "hw/arm/fdt.h"
61#include "hw/intc/arm_gic.h"
62#include "hw/intc/arm_gicv3_common.h"
63#include "hw/irq.h"
64#include "kvm_arm.h"
65#include "hw/firmware/smbios.h"
66#include "qapi/visitor.h"
67#include "standard-headers/linux/input.h"
68#include "hw/arm/smmuv3.h"
69#include "hw/acpi/acpi.h"
70#include "target/arm/internals.h"
71
72#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
73 static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
74 void *data) \
75 { \
76 MachineClass *mc = MACHINE_CLASS(oc); \
77 virt_machine_##major##_##minor##_options(mc); \
78 mc->desc = "QEMU " # major "." # minor " ARM Virtual Machine"; \
79 if (latest) { \
80 mc->alias = "virt"; \
81 } \
82 } \
83 static const TypeInfo machvirt_##major##_##minor##_info = { \
84 .name = MACHINE_TYPE_NAME("virt-" # major "." # minor), \
85 .parent = TYPE_VIRT_MACHINE, \
86 .class_init = virt_##major##_##minor##_class_init, \
87 }; \
88 static void machvirt_machine_##major##_##minor##_init(void) \
89 { \
90 type_register_static(&machvirt_##major##_##minor##_info); \
91 } \
92 type_init(machvirt_machine_##major##_##minor##_init);
93
94#define DEFINE_VIRT_MACHINE_AS_LATEST(major, minor) \
95 DEFINE_VIRT_MACHINE_LATEST(major, minor, true)
96#define DEFINE_VIRT_MACHINE(major, minor) \
97 DEFINE_VIRT_MACHINE_LATEST(major, minor, false)
98
99
100/* Number of external interrupt lines to configure the GIC with */
101#define NUM_IRQS 256
102
103#define PLATFORM_BUS_NUM_IRQS 64
104
105/* Legacy RAM limit in GB (< version 4.0) */
106#define LEGACY_RAMLIMIT_GB 255
107#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
108
109/* Addresses and sizes of our components.
110 * 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
111 * 128MB..256MB is used for miscellaneous device I/O.
112 * 256MB..1GB is reserved for possible future PCI support (ie where the
113 * PCI memory window will go if we add a PCI host controller).
114 * 1GB and up is RAM (which may happily spill over into the
115 * high memory region beyond 4GB).
116 * This represents a compromise between how much RAM can be given to
117 * a 32 bit VM and leaving space for expansion and in particular for PCI.
118 * Note that devices should generally be placed at multiples of 0x10000,
119 * to accommodate guests using 64K pages.
120 */
121static const MemMapEntry base_memmap[] = {
122 /* Space up to 0x8000000 is reserved for a boot ROM */
123 [VIRT_FLASH] = { 0, 0x08000000 },
124 [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
125 /* GIC distributor and CPU interfaces sit inside the CPU peripheral space */
126 [VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
127 [VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
128 [VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
129 [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
130 [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
131 /* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
132 [VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
133 /* This redistributor space allows up to 2*64kB*123 CPUs */
134 [VIRT_GIC_REDIST] = { 0x080A0000, 0x00F60000 },
135 [VIRT_UART] = { 0x09000000, 0x00001000 },
136 [VIRT_RTC] = { 0x09010000, 0x00001000 },
137 [VIRT_FW_CFG] = { 0x09020000, 0x00000018 },
138 [VIRT_GPIO] = { 0x09030000, 0x00001000 },
139 [VIRT_SECURE_UART] = { 0x09040000, 0x00001000 },
140 [VIRT_SMMU] = { 0x09050000, 0x00020000 },
141 [VIRT_MMIO] = { 0x0a000000, 0x00000200 },
142 /* ...repeating for a total of NUM_VIRTIO_TRANSPORTS, each of that size */
143 [VIRT_PLATFORM_BUS] = { 0x0c000000, 0x02000000 },
144 [VIRT_SECURE_MEM] = { 0x0e000000, 0x01000000 },
145 [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
146 [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
147 [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
148 /* Actual RAM size depends on initial RAM and device memory settings */
149 [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
150};
151
152/*
153 * Highmem IO Regions: This memory map is floating, located after the RAM.
154 * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
155 * top of the RAM, so that its base get the same alignment as the size,
156 * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
157 * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
158 * Note the extended_memmap is sized so that it eventually also includes the
159 * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
160 * index of base_memmap).
161 */
162static MemMapEntry extended_memmap[] = {
163 /* Additional 64 MB redist region (can contain up to 512 redistributors) */
164 [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
165 [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
166 /* Second PCIe window */
167 [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
168};
169
170static const int a15irqmap[] = {
171 [VIRT_UART] = 1,
172 [VIRT_RTC] = 2,
173 [VIRT_PCIE] = 3, /* ... to 6 */
174 [VIRT_GPIO] = 7,
175 [VIRT_SECURE_UART] = 8,
176 [VIRT_MMIO] = 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */
177 [VIRT_GIC_V2M] = 48, /* ...to 48 + NUM_GICV2M_SPIS - 1 */
178 [VIRT_SMMU] = 74, /* ...to 74 + NUM_SMMU_IRQS - 1 */
179 [VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
180};
181
182static const char *valid_cpus[] = {
183 ARM_CPU_TYPE_NAME("cortex-a7"),
184 ARM_CPU_TYPE_NAME("cortex-a15"),
185 ARM_CPU_TYPE_NAME("cortex-a53"),
186 ARM_CPU_TYPE_NAME("cortex-a57"),
187 ARM_CPU_TYPE_NAME("cortex-a72"),
188 ARM_CPU_TYPE_NAME("host"),
189 ARM_CPU_TYPE_NAME("max"),
190};
191
192static bool cpu_type_valid(const char *cpu)
193{
194 int i;
195
196 for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
197 if (strcmp(cpu, valid_cpus[i]) == 0) {
198 return true;
199 }
200 }
201 return false;
202}
203
204static void create_fdt(VirtMachineState *vms)
205{
206 MachineState *ms = MACHINE(vms);
207 int nb_numa_nodes = ms->numa_state->num_nodes;
208 void *fdt = create_device_tree(&vms->fdt_size);
209
210 if (!fdt) {
211 error_report("create_device_tree() failed");
212 exit(1);
213 }
214
215 vms->fdt = fdt;
216
217 /* Header */
218 qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
219 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
220 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
221
222 /* /chosen must exist for load_dtb to fill in necessary properties later */
223 qemu_fdt_add_subnode(fdt, "/chosen");
224
225 /* Clock node, for the benefit of the UART. The kernel device tree
226 * binding documentation claims the PL011 node clock properties are
227 * optional but in practice if you omit them the kernel refuses to
228 * probe for the device.
229 */
230 vms->clock_phandle = qemu_fdt_alloc_phandle(fdt);
231 qemu_fdt_add_subnode(fdt, "/apb-pclk");
232 qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock");
233 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0);
234 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000);
235 qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names",
236 "clk24mhz");
237 qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle);
238
239 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) {
240 int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t);
241 uint32_t *matrix = g_malloc0(size);
242 int idx, i, j;
243
244 for (i = 0; i < nb_numa_nodes; i++) {
245 for (j = 0; j < nb_numa_nodes; j++) {
246 idx = (i * nb_numa_nodes + j) * 3;
247 matrix[idx + 0] = cpu_to_be32(i);
248 matrix[idx + 1] = cpu_to_be32(j);
249 matrix[idx + 2] =
250 cpu_to_be32(ms->numa_state->nodes[i].distance[j]);
251 }
252 }
253
254 qemu_fdt_add_subnode(fdt, "/distance-map");
255 qemu_fdt_setprop_string(fdt, "/distance-map", "compatible",
256 "numa-distance-map-v1");
257 qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix",
258 matrix, size);
259 g_free(matrix);
260 }
261}
262
263static void fdt_add_timer_nodes(const VirtMachineState *vms)
264{
265 /* On real hardware these interrupts are level-triggered.
266 * On KVM they were edge-triggered before host kernel version 4.4,
267 * and level-triggered afterwards.
268 * On emulated QEMU they are level-triggered.
269 *
270 * Getting the DTB info about them wrong is awkward for some
271 * guest kernels:
272 * pre-4.8 ignore the DT and leave the interrupt configured
273 * with whatever the GIC reset value (or the bootloader) left it at
274 * 4.8 before rc6 honour the incorrect data by programming it back
275 * into the GIC, causing problems
276 * 4.8rc6 and later ignore the DT and always write "level triggered"
277 * into the GIC
278 *
279 * For backwards-compatibility, virt-2.8 and earlier will continue
280 * to say these are edge-triggered, but later machines will report
281 * the correct information.
282 */
283 ARMCPU *armcpu;
284 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
285 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
286
287 if (vmc->claim_edge_triggered_timers) {
288 irqflags = GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
289 }
290
291 if (vms->gic_version == 2) {
292 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
293 GIC_FDT_IRQ_PPI_CPU_WIDTH,
294 (1 << vms->smp_cpus) - 1);
295 }
296
297 qemu_fdt_add_subnode(vms->fdt, "/timer");
298
299 armcpu = ARM_CPU(qemu_get_cpu(0));
300 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
301 const char compat[] = "arm,armv8-timer\0arm,armv7-timer";
302 qemu_fdt_setprop(vms->fdt, "/timer", "compatible",
303 compat, sizeof(compat));
304 } else {
305 qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible",
306 "arm,armv7-timer");
307 }
308 qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0);
309 qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts",
310 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflags,
311 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqflags,
312 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags,
313 GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqflags);
314}
315
316static void fdt_add_cpu_nodes(const VirtMachineState *vms)
317{
318 int cpu;
319 int addr_cells = 1;
320 const MachineState *ms = MACHINE(vms);
321
322 /*
323 * From Documentation/devicetree/bindings/arm/cpus.txt
324 * On ARM v8 64-bit systems value should be set to 2,
325 * that corresponds to the MPIDR_EL1 register size.
326 * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs
327 * in the system, #address-cells can be set to 1, since
328 * MPIDR_EL1[63:32] bits are not used for CPUs
329 * identification.
330 *
331 * Here we actually don't know whether our system is 32- or 64-bit one.
332 * The simplest way to go is to examine affinity IDs of all our CPUs. If
333 * at least one of them has Aff3 populated, we set #address-cells to 2.
334 */
335 for (cpu = 0; cpu < vms->smp_cpus; cpu++) {
336 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
337
338 if (armcpu->mp_affinity & ARM_AFF3_MASK) {
339 addr_cells = 2;
340 break;
341 }
342 }
343
344 qemu_fdt_add_subnode(vms->fdt, "/cpus");
345 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells);
346 qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0);
347
348 for (cpu = vms->smp_cpus - 1; cpu >= 0; cpu--) {
349 char *nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
350 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
351 CPUState *cs = CPU(armcpu);
352
353 qemu_fdt_add_subnode(vms->fdt, nodename);
354 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu");
355 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
356 armcpu->dtb_compatible);
357
358 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
359 && vms->smp_cpus > 1) {
360 qemu_fdt_setprop_string(vms->fdt, nodename,
361 "enable-method", "psci");
362 }
363
364 if (addr_cells == 2) {
365 qemu_fdt_setprop_u64(vms->fdt, nodename, "reg",
366 armcpu->mp_affinity);
367 } else {
368 qemu_fdt_setprop_cell(vms->fdt, nodename, "reg",
369 armcpu->mp_affinity);
370 }
371
372 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
373 qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id",
374 ms->possible_cpus->cpus[cs->cpu_index].props.node_id);
375 }
376
377 g_free(nodename);
378 }
379}
380
381static void fdt_add_its_gic_node(VirtMachineState *vms)
382{
383 char *nodename;
384
385 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
386 nodename = g_strdup_printf("/intc/its@%" PRIx64,
387 vms->memmap[VIRT_GIC_ITS].base);
388 qemu_fdt_add_subnode(vms->fdt, nodename);
389 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
390 "arm,gic-v3-its");
391 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
392 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
393 2, vms->memmap[VIRT_GIC_ITS].base,
394 2, vms->memmap[VIRT_GIC_ITS].size);
395 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
396 g_free(nodename);
397}
398
399static void fdt_add_v2m_gic_node(VirtMachineState *vms)
400{
401 char *nodename;
402
403 nodename = g_strdup_printf("/intc/v2m@%" PRIx64,
404 vms->memmap[VIRT_GIC_V2M].base);
405 vms->msi_phandle = qemu_fdt_alloc_phandle(vms->fdt);
406 qemu_fdt_add_subnode(vms->fdt, nodename);
407 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
408 "arm,gic-v2m-frame");
409 qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0);
410 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
411 2, vms->memmap[VIRT_GIC_V2M].base,
412 2, vms->memmap[VIRT_GIC_V2M].size);
413 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle);
414 g_free(nodename);
415}
416
417static void fdt_add_gic_node(VirtMachineState *vms)
418{
419 char *nodename;
420
421 vms->gic_phandle = qemu_fdt_alloc_phandle(vms->fdt);
422 qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phandle);
423
424 nodename = g_strdup_printf("/intc@%" PRIx64,
425 vms->memmap[VIRT_GIC_DIST].base);
426 qemu_fdt_add_subnode(vms->fdt, nodename);
427 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3);
428 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0);
429 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
430 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
431 qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
432 if (vms->gic_version == 3) {
433 int nb_redist_regions = virt_gicv3_redist_region_count(vms);
434
435 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
436 "arm,gic-v3");
437
438 qemu_fdt_setprop_cell(vms->fdt, nodename,
439 "#redistributor-regions", nb_redist_regions);
440
441 if (nb_redist_regions == 1) {
442 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
443 2, vms->memmap[VIRT_GIC_DIST].base,
444 2, vms->memmap[VIRT_GIC_DIST].size,
445 2, vms->memmap[VIRT_GIC_REDIST].base,
446 2, vms->memmap[VIRT_GIC_REDIST].size);
447 } else {
448 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
449 2, vms->memmap[VIRT_GIC_DIST].base,
450 2, vms->memmap[VIRT_GIC_DIST].size,
451 2, vms->memmap[VIRT_GIC_REDIST].base,
452 2, vms->memmap[VIRT_GIC_REDIST].size,
453 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
454 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
455 }
456
457 if (vms->virt) {
458 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
459 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
460 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
461 }
462 } else {
463 /* 'cortex-a15-gic' means 'GIC v2' */
464 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
465 "arm,cortex-a15-gic");
466 if (!vms->virt) {
467 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
468 2, vms->memmap[VIRT_GIC_DIST].base,
469 2, vms->memmap[VIRT_GIC_DIST].size,
470 2, vms->memmap[VIRT_GIC_CPU].base,
471 2, vms->memmap[VIRT_GIC_CPU].size);
472 } else {
473 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
474 2, vms->memmap[VIRT_GIC_DIST].base,
475 2, vms->memmap[VIRT_GIC_DIST].size,
476 2, vms->memmap[VIRT_GIC_CPU].base,
477 2, vms->memmap[VIRT_GIC_CPU].size,
478 2, vms->memmap[VIRT_GIC_HYP].base,
479 2, vms->memmap[VIRT_GIC_HYP].size,
480 2, vms->memmap[VIRT_GIC_VCPU].base,
481 2, vms->memmap[VIRT_GIC_VCPU].size);
482 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
483 GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
484 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
485 }
486 }
487
488 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
489 g_free(nodename);
490}
491
492static void fdt_add_pmu_nodes(const VirtMachineState *vms)
493{
494 CPUState *cpu;
495 ARMCPU *armcpu;
496 uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
497
498 CPU_FOREACH(cpu) {
499 armcpu = ARM_CPU(cpu);
500 if (!arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
501 return;
502 }
503 if (kvm_enabled()) {
504 if (kvm_irqchip_in_kernel()) {
505 kvm_arm_pmu_set_irq(cpu, PPI(VIRTUAL_PMU_IRQ));
506 }
507 kvm_arm_pmu_init(cpu);
508 }
509 }
510
511 if (vms->gic_version == 2) {
512 irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
513 GIC_FDT_IRQ_PPI_CPU_WIDTH,
514 (1 << vms->smp_cpus) - 1);
515 }
516
517 armcpu = ARM_CPU(qemu_get_cpu(0));
518 qemu_fdt_add_subnode(vms->fdt, "/pmu");
519 if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) {
520 const char compat[] = "arm,armv8-pmuv3";
521 qemu_fdt_setprop(vms->fdt, "/pmu", "compatible",
522 compat, sizeof(compat));
523 qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts",
524 GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqflags);
525 }
526}
527
528static void create_its(VirtMachineState *vms, DeviceState *gicdev)
529{
530 const char *itsclass = its_class_name();
531 DeviceState *dev;
532
533 if (!itsclass) {
534 /* Do nothing if not supported */
535 return;
536 }
537
538 dev = qdev_create(NULL, itsclass);
539
540 object_property_set_link(OBJECT(dev), OBJECT(gicdev), "parent-gicv3",
541 &error_abort);
542 qdev_init_nofail(dev);
543 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
544
545 fdt_add_its_gic_node(vms);
546}
547
548static void create_v2m(VirtMachineState *vms, qemu_irq *pic)
549{
550 int i;
551 int irq = vms->irqmap[VIRT_GIC_V2M];
552 DeviceState *dev;
553
554 dev = qdev_create(NULL, "arm-gicv2m");
555 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base);
556 qdev_prop_set_uint32(dev, "base-spi", irq);
557 qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS);
558 qdev_init_nofail(dev);
559
560 for (i = 0; i < NUM_GICV2M_SPIS; i++) {
561 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
562 }
563
564 fdt_add_v2m_gic_node(vms);
565}
566
567static void create_gic(VirtMachineState *vms, qemu_irq *pic)
568{
569 MachineState *ms = MACHINE(vms);
570 /* We create a standalone GIC */
571 DeviceState *gicdev;
572 SysBusDevice *gicbusdev;
573 const char *gictype;
574 int type = vms->gic_version, i;
575 unsigned int smp_cpus = ms->smp.cpus;
576 uint32_t nb_redist_regions = 0;
577
578 gictype = (type == 3) ? gicv3_class_name() : gic_class_name();
579
580 gicdev = qdev_create(NULL, gictype);
581 qdev_prop_set_uint32(gicdev, "revision", type);
582 qdev_prop_set_uint32(gicdev, "num-cpu", smp_cpus);
583 /* Note that the num-irq property counts both internal and external
584 * interrupts; there are always 32 of the former (mandated by GIC spec).
585 */
586 qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
587 if (!kvm_irqchip_in_kernel()) {
588 qdev_prop_set_bit(gicdev, "has-security-extensions", vms->secure);
589 }
590
591 if (type == 3) {
592 uint32_t redist0_capacity =
593 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
594 uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
595
596 nb_redist_regions = virt_gicv3_redist_region_count(vms);
597
598 qdev_prop_set_uint32(gicdev, "len-redist-region-count",
599 nb_redist_regions);
600 qdev_prop_set_uint32(gicdev, "redist-region-count[0]", redist0_count);
601
602 if (nb_redist_regions == 2) {
603 uint32_t redist1_capacity =
604 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
605
606 qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
607 MIN(smp_cpus - redist0_count, redist1_capacity));
608 }
609 } else {
610 if (!kvm_irqchip_in_kernel()) {
611 qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
612 vms->virt);
613 }
614 }
615 qdev_init_nofail(gicdev);
616 gicbusdev = SYS_BUS_DEVICE(gicdev);
617 sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base);
618 if (type == 3) {
619 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
620 if (nb_redist_regions == 2) {
621 sysbus_mmio_map(gicbusdev, 2,
622 vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
623 }
624 } else {
625 sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
626 if (vms->virt) {
627 sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
628 sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
629 }
630 }
631
632 /* Wire the outputs from each CPU's generic timer and the GICv3
633 * maintenance interrupt signal to the appropriate GIC PPI inputs,
634 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
635 */
636 for (i = 0; i < smp_cpus; i++) {
637 DeviceState *cpudev = DEVICE(qemu_get_cpu(i));
638 int ppibase = NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS;
639 int irq;
640 /* Mapping from the output timer irq lines from the CPU to the
641 * GIC PPI inputs we use for the virt board.
642 */
643 const int timer_irq[] = {
644 [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,
645 [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,
646 [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,
647 [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ,
648 };
649
650 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
651 qdev_connect_gpio_out(cpudev, irq,
652 qdev_get_gpio_in(gicdev,
653 ppibase + timer_irq[irq]));
654 }
655
656 if (type == 3) {
657 qemu_irq irq = qdev_get_gpio_in(gicdev,
658 ppibase + ARCH_GIC_MAINT_IRQ);
659 qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
660 0, irq);
661 } else if (vms->virt) {
662 qemu_irq irq = qdev_get_gpio_in(gicdev,
663 ppibase + ARCH_GIC_MAINT_IRQ);
664 sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
665 }
666
667 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
668 qdev_get_gpio_in(gicdev, ppibase
669 + VIRTUAL_PMU_IRQ));
670
671 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
672 sysbus_connect_irq(gicbusdev, i + smp_cpus,
673 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
674 sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus,
675 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
676 sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus,
677 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
678 }
679
680 for (i = 0; i < NUM_IRQS; i++) {
681 pic[i] = qdev_get_gpio_in(gicdev, i);
682 }
683
684 fdt_add_gic_node(vms);
685
686 if (type == 3 && vms->its) {
687 create_its(vms, gicdev);
688 } else if (type == 2) {
689 create_v2m(vms, pic);
690 }
691}
692
693static void create_uart(const VirtMachineState *vms, qemu_irq *pic, int uart,
694 MemoryRegion *mem, Chardev *chr)
695{
696 char *nodename;
697 hwaddr base = vms->memmap[uart].base;
698 hwaddr size = vms->memmap[uart].size;
699 int irq = vms->irqmap[uart];
700 const char compat[] = "arm,pl011\0arm,primecell";
701 const char clocknames[] = "uartclk\0apb_pclk";
702 DeviceState *dev = qdev_create(NULL, "pl011");
703 SysBusDevice *s = SYS_BUS_DEVICE(dev);
704
705 qdev_prop_set_chr(dev, "chardev", chr);
706 qdev_init_nofail(dev);
707 memory_region_add_subregion(mem, base,
708 sysbus_mmio_get_region(s, 0));
709 sysbus_connect_irq(s, 0, pic[irq]);
710
711 nodename = g_strdup_printf("/pl011@%" PRIx64, base);
712 qemu_fdt_add_subnode(vms->fdt, nodename);
713 /* Note that we can't use setprop_string because of the embedded NUL */
714 qemu_fdt_setprop(vms->fdt, nodename, "compatible",
715 compat, sizeof(compat));
716 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
717 2, base, 2, size);
718 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
719 GIC_FDT_IRQ_TYPE_SPI, irq,
720 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
721 qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks",
722 vms->clock_phandle, vms->clock_phandle);
723 qemu_fdt_setprop(vms->fdt, nodename, "clock-names",
724 clocknames, sizeof(clocknames));
725
726 if (uart == VIRT_UART) {
727 qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodename);
728 } else {
729 /* Mark as not usable by the normal world */
730 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
731 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
732
733 qemu_fdt_add_subnode(vms->fdt, "/secure-chosen");
734 qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path",
735 nodename);
736 }
737
738 g_free(nodename);
739}
740
741static void create_rtc(const VirtMachineState *vms, qemu_irq *pic)
742{
743 char *nodename;
744 hwaddr base = vms->memmap[VIRT_RTC].base;
745 hwaddr size = vms->memmap[VIRT_RTC].size;
746 int irq = vms->irqmap[VIRT_RTC];
747 const char compat[] = "arm,pl031\0arm,primecell";
748
749 sysbus_create_simple("pl031", base, pic[irq]);
750
751 nodename = g_strdup_printf("/pl031@%" PRIx64, base);
752 qemu_fdt_add_subnode(vms->fdt, nodename);
753 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
754 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
755 2, base, 2, size);
756 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
757 GIC_FDT_IRQ_TYPE_SPI, irq,
758 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
759 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
760 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
761 g_free(nodename);
762}
763
764static DeviceState *gpio_key_dev;
765static void virt_powerdown_req(Notifier *n, void *opaque)
766{
767 /* use gpio Pin 3 for power button event */
768 qemu_set_irq(qdev_get_gpio_in(gpio_key_dev, 0), 1);
769}
770
771static Notifier virt_system_powerdown_notifier = {
772 .notify = virt_powerdown_req
773};
774
775static void create_gpio(const VirtMachineState *vms, qemu_irq *pic)
776{
777 char *nodename;
778 DeviceState *pl061_dev;
779 hwaddr base = vms->memmap[VIRT_GPIO].base;
780 hwaddr size = vms->memmap[VIRT_GPIO].size;
781 int irq = vms->irqmap[VIRT_GPIO];
782 const char compat[] = "arm,pl061\0arm,primecell";
783
784 pl061_dev = sysbus_create_simple("pl061", base, pic[irq]);
785
786 uint32_t phandle = qemu_fdt_alloc_phandle(vms->fdt);
787 nodename = g_strdup_printf("/pl061@%" PRIx64, base);
788 qemu_fdt_add_subnode(vms->fdt, nodename);
789 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
790 2, base, 2, size);
791 qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(compat));
792 qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2);
793 qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0);
794 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
795 GIC_FDT_IRQ_TYPE_SPI, irq,
796 GIC_FDT_IRQ_FLAGS_LEVEL_HI);
797 qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle);
798 qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk");
799 qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle);
800
801 gpio_key_dev = sysbus_create_simple("gpio-key", -1,
802 qdev_get_gpio_in(pl061_dev, 3));
803 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys");
804 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-keys");
805 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0);
806 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1);
807
808 qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff");
809 qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff",
810 "label", "GPIO Key Poweroff");
811 qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code",
812 KEY_POWER);
813 qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff",
814 "gpios", phandle, 3, 0);
815
816 /* connect powerdown request */
817 qemu_register_powerdown_notifier(&virt_system_powerdown_notifier);
818
819 g_free(nodename);
820}
821
822static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
823{
824 int i;
825 hwaddr size = vms->memmap[VIRT_MMIO].size;
826
827 /* We create the transports in forwards order. Since qbus_realize()
828 * prepends (not appends) new child buses, the incrementing loop below will
829 * create a list of virtio-mmio buses with decreasing base addresses.
830 *
831 * When a -device option is processed from the command line,
832 * qbus_find_recursive() picks the next free virtio-mmio bus in forwards
833 * order. The upshot is that -device options in increasing command line
834 * order are mapped to virtio-mmio buses with decreasing base addresses.
835 *
836 * When this code was originally written, that arrangement ensured that the
837 * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, etc) to
838 * the first -device on the command line. (The end-to-end order is a
839 * function of this loop, qbus_realize(), qbus_find_recursive(), and the
840 * guest kernel's name-to-address assignment strategy.)
841 *
842 * Meanwhile, the kernel's traversal seems to have been reversed; see eg.
843 * the message, if not necessarily the code, of commit 70161ff336.
844 * Therefore the loop now establishes the inverse of the original intent.
845 *
846 * Unfortunately, we can't counteract the kernel change by reversing the
847 * loop; it would break existing command lines.
848 *
849 * In any case, the kernel makes no guarantee about the stability of
850 * enumeration order of virtio devices (as demonstrated by it changing
851 * between kernel versions). For reliable and stable identification
852 * of disks users must use UUIDs or similar mechanisms.
853 */
854 for (i = 0; i < NUM_VIRTIO_TRANSPORTS; i++) {
855 int irq = vms->irqmap[VIRT_MMIO] + i;
856 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
857
858 sysbus_create_simple("virtio-mmio", base, pic[irq]);
859 }
860
861 /* We add dtb nodes in reverse order so that they appear in the finished
862 * device tree lowest address first.
863 *
864 * Note that this mapping is independent of the loop above. The previous
865 * loop influences virtio device to virtio transport assignment, whereas
866 * this loop controls how virtio transports are laid out in the dtb.
867 */
868 for (i = NUM_VIRTIO_TRANSPORTS - 1; i >= 0; i--) {
869 char *nodename;
870 int irq = vms->irqmap[VIRT_MMIO] + i;
871 hwaddr base = vms->memmap[VIRT_MMIO].base + i * size;
872
873 nodename = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
874 qemu_fdt_add_subnode(vms->fdt, nodename);
875 qemu_fdt_setprop_string(vms->fdt, nodename,
876 "compatible", "virtio,mmio");
877 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
878 2, base, 2, size);
879 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
880 GIC_FDT_IRQ_TYPE_SPI, irq,
881 GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
882 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
883 g_free(nodename);
884 }
885}
886
887#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
888
889static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
890 const char *name,
891 const char *alias_prop_name)
892{
893 /*
894 * Create a single flash device. We use the same parameters as
895 * the flash devices on the Versatile Express board.
896 */
897 DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
898
899 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
900 qdev_prop_set_uint8(dev, "width", 4);
901 qdev_prop_set_uint8(dev, "device-width", 2);
902 qdev_prop_set_bit(dev, "big-endian", false);
903 qdev_prop_set_uint16(dev, "id0", 0x89);
904 qdev_prop_set_uint16(dev, "id1", 0x18);
905 qdev_prop_set_uint16(dev, "id2", 0x00);
906 qdev_prop_set_uint16(dev, "id3", 0x00);
907 qdev_prop_set_string(dev, "name", name);
908 object_property_add_child(OBJECT(vms), name, OBJECT(dev),
909 &error_abort);
910 object_property_add_alias(OBJECT(vms), alias_prop_name,
911 OBJECT(dev), "drive", &error_abort);
912 return PFLASH_CFI01(dev);
913}
914
915static void virt_flash_create(VirtMachineState *vms)
916{
917 vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
918 vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
919}
920
921static void virt_flash_map1(PFlashCFI01 *flash,
922 hwaddr base, hwaddr size,
923 MemoryRegion *sysmem)
924{
925 DeviceState *dev = DEVICE(flash);
926
927 assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
928 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
929 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
930 qdev_init_nofail(dev);
931
932 memory_region_add_subregion(sysmem, base,
933 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
934 0));
935}
936
937static void virt_flash_map(VirtMachineState *vms,
938 MemoryRegion *sysmem,
939 MemoryRegion *secure_sysmem)
940{
941 /*
942 * Map two flash devices to fill the VIRT_FLASH space in the memmap.
943 * sysmem is the system memory space. secure_sysmem is the secure view
944 * of the system, and the first flash device should be made visible only
945 * there. The second flash device is visible to both secure and nonsecure.
946 * If sysmem == secure_sysmem this means there is no separate Secure
947 * address space and both flash devices are generally visible.
948 */
949 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
950 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
951
952 virt_flash_map1(vms->flash[0], flashbase, flashsize,
953 secure_sysmem);
954 virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
955 sysmem);
956}
957
958static void virt_flash_fdt(VirtMachineState *vms,
959 MemoryRegion *sysmem,
960 MemoryRegion *secure_sysmem)
961{
962 hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
963 hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
964 char *nodename;
965
966 if (sysmem == secure_sysmem) {
967 /* Report both flash devices as a single node in the DT */
968 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
969 qemu_fdt_add_subnode(vms->fdt, nodename);
970 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
971 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
972 2, flashbase, 2, flashsize,
973 2, flashbase + flashsize, 2, flashsize);
974 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
975 g_free(nodename);
976 } else {
977 /*
978 * Report the devices as separate nodes so we can mark one as
979 * only visible to the secure world.
980 */
981 nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
982 qemu_fdt_add_subnode(vms->fdt, nodename);
983 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
984 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
985 2, flashbase, 2, flashsize);
986 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
987 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
988 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
989 g_free(nodename);
990
991 nodename = g_strdup_printf("/flash@%" PRIx64, flashbase);
992 qemu_fdt_add_subnode(vms->fdt, nodename);
993 qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-flash");
994 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
995 2, flashbase + flashsize, 2, flashsize);
996 qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
997 g_free(nodename);
998 }
999}
1000
1001static bool virt_firmware_init(VirtMachineState *vms,
1002 MemoryRegion *sysmem,
1003 MemoryRegion *secure_sysmem)
1004{
1005 int i;
1006 BlockBackend *pflash_blk0;
1007
1008 /* Map legacy -drive if=pflash to machine properties */
1009 for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
1010 pflash_cfi01_legacy_drive(vms->flash[i],
1011 drive_get(IF_PFLASH, 0, i));
1012 }
1013
1014 virt_flash_map(vms, sysmem, secure_sysmem);
1015
1016 pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
1017
1018 if (bios_name) {
1019 char *fname;
1020 MemoryRegion *mr;
1021 int image_size;
1022
1023 if (pflash_blk0) {
1024 error_report("The contents of the first flash device may be "
1025 "specified with -bios or with -drive if=pflash... "
1026 "but you cannot use both options at once");
1027 exit(1);
1028 }
1029
1030 /* Fall back to -bios */
1031
1032 fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1033 if (!fname) {
1034 error_report("Could not find ROM image '%s'", bios_name);
1035 exit(1);
1036 }
1037 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
1038 image_size = load_image_mr(fname, mr);
1039 g_free(fname);
1040 if (image_size < 0) {
1041 error_report("Could not load ROM image '%s'", bios_name);
1042 exit(1);
1043 }
1044 }
1045
1046 return pflash_blk0 || bios_name;
1047}
1048
1049static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
1050{
1051 MachineState *ms = MACHINE(vms);
1052 hwaddr base = vms->memmap[VIRT_FW_CFG].base;
1053 hwaddr size = vms->memmap[VIRT_FW_CFG].size;
1054 FWCfgState *fw_cfg;
1055 char *nodename;
1056
1057 fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, as);
1058 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus);
1059
1060 nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base);
1061 qemu_fdt_add_subnode(vms->fdt, nodename);
1062 qemu_fdt_setprop_string(vms->fdt, nodename,
1063 "compatible", "qemu,fw-cfg-mmio");
1064 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1065 2, base, 2, size);
1066 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1067 g_free(nodename);
1068 return fw_cfg;
1069}
1070
1071static void create_pcie_irq_map(const VirtMachineState *vms,
1072 uint32_t gic_phandle,
1073 int first_irq, const char *nodename)
1074{
1075 int devfn, pin;
1076 uint32_t full_irq_map[4 * 4 * 10] = { 0 };
1077 uint32_t *irq_map = full_irq_map;
1078
1079 for (devfn = 0; devfn <= 0x18; devfn += 0x8) {
1080 for (pin = 0; pin < 4; pin++) {
1081 int irq_type = GIC_FDT_IRQ_TYPE_SPI;
1082 int irq_nr = first_irq + ((pin + PCI_SLOT(devfn)) % PCI_NUM_PINS);
1083 int irq_level = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
1084 int i;
1085
1086 uint32_t map[] = {
1087 devfn << 8, 0, 0, /* devfn */
1088 pin + 1, /* PCI pin */
1089 gic_phandle, 0, 0, irq_type, irq_nr, irq_level }; /* GIC irq */
1090
1091 /* Convert map to big endian */
1092 for (i = 0; i < 10; i++) {
1093 irq_map[i] = cpu_to_be32(map[i]);
1094 }
1095 irq_map += 10;
1096 }
1097 }
1098
1099 qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map",
1100 full_irq_map, sizeof(full_irq_map));
1101
1102 qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask",
1103 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */
1104 0x7 /* PCI irq */);
1105}
1106
1107static void create_smmu(const VirtMachineState *vms, qemu_irq *pic,
1108 PCIBus *bus)
1109{
1110 char *node;
1111 const char compat[] = "arm,smmu-v3";
1112 int irq = vms->irqmap[VIRT_SMMU];
1113 int i;
1114 hwaddr base = vms->memmap[VIRT_SMMU].base;
1115 hwaddr size = vms->memmap[VIRT_SMMU].size;
1116 const char irq_names[] = "eventq\0priq\0cmdq-sync\0gerror";
1117 DeviceState *dev;
1118
1119 if (vms->iommu != VIRT_IOMMU_SMMUV3 || !vms->iommu_phandle) {
1120 return;
1121 }
1122
1123 dev = qdev_create(NULL, "arm-smmuv3");
1124
1125 object_property_set_link(OBJECT(dev), OBJECT(bus), "primary-bus",
1126 &error_abort);
1127 qdev_init_nofail(dev);
1128 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
1129 for (i = 0; i < NUM_SMMU_IRQS; i++) {
1130 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1131 }
1132
1133 node = g_strdup_printf("/smmuv3@%" PRIx64, base);
1134 qemu_fdt_add_subnode(vms->fdt, node);
1135 qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat));
1136 qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size);
1137
1138 qemu_fdt_setprop_cells(vms->fdt, node, "interrupts",
1139 GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1140 GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1141 GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI,
1142 GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI);
1143
1144 qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names,
1145 sizeof(irq_names));
1146
1147 qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle);
1148 qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk");
1149 qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0);
1150
1151 qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1);
1152
1153 qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle);
1154 g_free(node);
1155}
1156
1157static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
1158{
1159 hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
1160 hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
1161 hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
1162 hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
1163 hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
1164 hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
1165 hwaddr base_ecam, size_ecam;
1166 hwaddr base = base_mmio;
1167 int nr_pcie_buses;
1168 int irq = vms->irqmap[VIRT_PCIE];
1169 MemoryRegion *mmio_alias;
1170 MemoryRegion *mmio_reg;
1171 MemoryRegion *ecam_alias;
1172 MemoryRegion *ecam_reg;
1173 DeviceState *dev;
1174 char *nodename;
1175 int i, ecam_id;
1176 PCIHostState *pci;
1177
1178 dev = qdev_create(NULL, TYPE_GPEX_HOST);
1179 qdev_init_nofail(dev);
1180
1181 ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
1182 base_ecam = vms->memmap[ecam_id].base;
1183 size_ecam = vms->memmap[ecam_id].size;
1184 nr_pcie_buses = size_ecam / PCIE_MMCFG_SIZE_MIN;
1185 /* Map only the first size_ecam bytes of ECAM space */
1186 ecam_alias = g_new0(MemoryRegion, 1);
1187 ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
1188 memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam",
1189 ecam_reg, 0, size_ecam);
1190 memory_region_add_subregion(get_system_memory(), base_ecam, ecam_alias);
1191
1192 /* Map the MMIO window into system address space so as to expose
1193 * the section of PCI MMIO space which starts at the same base address
1194 * (ie 1:1 mapping for that part of PCI MMIO space visible through
1195 * the window).
1196 */
1197 mmio_alias = g_new0(MemoryRegion, 1);
1198 mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1);
1199 memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio",
1200 mmio_reg, base_mmio, size_mmio);
1201 memory_region_add_subregion(get_system_memory(), base_mmio, mmio_alias);
1202
1203 if (vms->highmem) {
1204 /* Map high MMIO space */
1205 MemoryRegion *high_mmio_alias = g_new0(MemoryRegion, 1);
1206
1207 memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high",
1208 mmio_reg, base_mmio_high, size_mmio_high);
1209 memory_region_add_subregion(get_system_memory(), base_mmio_high,
1210 high_mmio_alias);
1211 }
1212
1213 /* Map IO port space */
1214 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, base_pio);
1215
1216 for (i = 0; i < GPEX_NUM_IRQS; i++) {
1217 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pic[irq + i]);
1218 gpex_set_irq_num(GPEX_HOST(dev), i, irq + i);
1219 }
1220
1221 pci = PCI_HOST_BRIDGE(dev);
1222 if (pci->bus) {
1223 for (i = 0; i < nb_nics; i++) {
1224 NICInfo *nd = &nd_table[i];
1225
1226 if (!nd->model) {
1227 nd->model = g_strdup("virtio");
1228 }
1229
1230 pci_nic_init_nofail(nd, pci->bus, nd->model, NULL);
1231 }
1232 }
1233
1234 nodename = g_strdup_printf("/pcie@%" PRIx64, base);
1235 qemu_fdt_add_subnode(vms->fdt, nodename);
1236 qemu_fdt_setprop_string(vms->fdt, nodename,
1237 "compatible", "pci-host-ecam-generic");
1238 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci");
1239 qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3);
1240 qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2);
1241 qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0);
1242 qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0,
1243 nr_pcie_buses - 1);
1244 qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0);
1245
1246 if (vms->msi_phandle) {
1247 qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent",
1248 vms->msi_phandle);
1249 }
1250
1251 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
1252 2, base_ecam, 2, size_ecam);
1253
1254 if (vms->highmem) {
1255 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1256 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1257 2, base_pio, 2, size_pio,
1258 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1259 2, base_mmio, 2, size_mmio,
1260 1, FDT_PCI_RANGE_MMIO_64BIT,
1261 2, base_mmio_high,
1262 2, base_mmio_high, 2, size_mmio_high);
1263 } else {
1264 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges",
1265 1, FDT_PCI_RANGE_IOPORT, 2, 0,
1266 2, base_pio, 2, size_pio,
1267 1, FDT_PCI_RANGE_MMIO, 2, base_mmio,
1268 2, base_mmio, 2, size_mmio);
1269 }
1270
1271 qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1);
1272 create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename);
1273
1274 if (vms->iommu) {
1275 vms->iommu_phandle = qemu_fdt_alloc_phandle(vms->fdt);
1276
1277 create_smmu(vms, pic, pci->bus);
1278
1279 qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map",
1280 0x0, vms->iommu_phandle, 0x0, 0x10000);
1281 }
1282
1283 g_free(nodename);
1284}
1285
1286static void create_platform_bus(VirtMachineState *vms, qemu_irq *pic)
1287{
1288 DeviceState *dev;
1289 SysBusDevice *s;
1290 int i;
1291 MemoryRegion *sysmem = get_system_memory();
1292
1293 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
1294 dev->id = TYPE_PLATFORM_BUS_DEVICE;
1295 qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS);
1296 qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].size);
1297 qdev_init_nofail(dev);
1298 vms->platform_bus_dev = dev;
1299
1300 s = SYS_BUS_DEVICE(dev);
1301 for (i = 0; i < PLATFORM_BUS_NUM_IRQS; i++) {
1302 int irqn = vms->irqmap[VIRT_PLATFORM_BUS] + i;
1303 sysbus_connect_irq(s, i, pic[irqn]);
1304 }
1305
1306 memory_region_add_subregion(sysmem,
1307 vms->memmap[VIRT_PLATFORM_BUS].base,
1308 sysbus_mmio_get_region(s, 0));
1309}
1310
1311static void create_secure_ram(VirtMachineState *vms,
1312 MemoryRegion *secure_sysmem)
1313{
1314 MemoryRegion *secram = g_new(MemoryRegion, 1);
1315 char *nodename;
1316 hwaddr base = vms->memmap[VIRT_SECURE_MEM].base;
1317 hwaddr size = vms->memmap[VIRT_SECURE_MEM].size;
1318
1319 memory_region_init_ram(secram, NULL, "virt.secure-ram", size,
1320 &error_fatal);
1321 memory_region_add_subregion(secure_sysmem, base, secram);
1322
1323 nodename = g_strdup_printf("/secram@%" PRIx64, base);
1324 qemu_fdt_add_subnode(vms->fdt, nodename);
1325 qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory");
1326 qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, size);
1327 qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled");
1328 qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay");
1329
1330 g_free(nodename);
1331}
1332
1333static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size)
1334{
1335 const VirtMachineState *board = container_of(binfo, VirtMachineState,
1336 bootinfo);
1337
1338 *fdt_size = board->fdt_size;
1339 return board->fdt;
1340}
1341
1342static void virt_build_smbios(VirtMachineState *vms)
1343{
1344 MachineClass *mc = MACHINE_GET_CLASS(vms);
1345 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1346 uint8_t *smbios_tables, *smbios_anchor;
1347 size_t smbios_tables_len, smbios_anchor_len;
1348 const char *product = "QEMU Virtual Machine";
1349
1350 if (kvm_enabled()) {
1351 product = "KVM Virtual Machine";
1352 }
1353
1354 smbios_set_defaults("QEMU", product,
1355 vmc->smbios_old_sys_ver ? "1.0" : mc->name, false,
1356 true, SMBIOS_ENTRY_POINT_30);
1357
1358 smbios_get_tables(MACHINE(vms), NULL, 0, &smbios_tables, &smbios_tables_len,
1359 &smbios_anchor, &smbios_anchor_len);
1360
1361 if (smbios_anchor) {
1362 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-tables",
1363 smbios_tables, smbios_tables_len);
1364 fw_cfg_add_file(vms->fw_cfg, "etc/smbios/smbios-anchor",
1365 smbios_anchor, smbios_anchor_len);
1366 }
1367}
1368
1369static
1370void virt_machine_done(Notifier *notifier, void *data)
1371{
1372 VirtMachineState *vms = container_of(notifier, VirtMachineState,
1373 machine_done);
1374 MachineState *ms = MACHINE(vms);
1375 ARMCPU *cpu = ARM_CPU(first_cpu);
1376 struct arm_boot_info *info = &vms->bootinfo;
1377 AddressSpace *as = arm_boot_address_space(cpu, info);
1378
1379 /*
1380 * If the user provided a dtb, we assume the dynamic sysbus nodes
1381 * already are integrated there. This corresponds to a use case where
1382 * the dynamic sysbus nodes are complex and their generation is not yet
1383 * supported. In that case the user can take charge of the guest dt
1384 * while qemu takes charge of the qom stuff.
1385 */
1386 if (info->dtb_filename == NULL) {
1387 platform_bus_add_all_fdt_nodes(vms->fdt, "/intc",
1388 vms->memmap[VIRT_PLATFORM_BUS].base,
1389 vms->memmap[VIRT_PLATFORM_BUS].size,
1390 vms->irqmap[VIRT_PLATFORM_BUS]);
1391 }
1392 if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) {
1393 exit(1);
1394 }
1395
1396 virt_acpi_setup(vms);
1397 virt_build_smbios(vms);
1398}
1399
1400static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
1401{
1402 uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
1403 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1404
1405 if (!vmc->disallow_affinity_adjustment) {
1406 /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
1407 * GIC's target-list limitations. 32-bit KVM hosts currently
1408 * always create clusters of 4 CPUs, but that is expected to
1409 * change when they gain support for gicv3. When KVM is enabled
1410 * it will override the changes we make here, therefore our
1411 * purposes are to make TCG consistent (with 64-bit KVM hosts)
1412 * and to improve SGI efficiency.
1413 */
1414 if (vms->gic_version == 3) {
1415 clustersz = GICV3_TARGETLIST_BITS;
1416 } else {
1417 clustersz = GIC_TARGETLIST_BITS;
1418 }
1419 }
1420 return arm_cpu_mp_affinity(idx, clustersz);
1421}
1422
1423static void virt_set_memmap(VirtMachineState *vms)
1424{
1425 MachineState *ms = MACHINE(vms);
1426 hwaddr base, device_memory_base, device_memory_size;
1427 int i;
1428
1429 vms->memmap = extended_memmap;
1430
1431 for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
1432 vms->memmap[i] = base_memmap[i];
1433 }
1434
1435 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
1436 error_report("unsupported number of memory slots: %"PRIu64,
1437 ms->ram_slots);
1438 exit(EXIT_FAILURE);
1439 }
1440
1441 /*
1442 * We compute the base of the high IO region depending on the
1443 * amount of initial and device memory. The device memory start/size
1444 * is aligned on 1GiB. We never put the high IO region below 256GiB
1445 * so that if maxram_size is < 255GiB we keep the legacy memory map.
1446 * The device region size assumes 1GiB page max alignment per slot.
1447 */
1448 device_memory_base =
1449 ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
1450 device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
1451
1452 /* Base address of the high IO region */
1453 base = device_memory_base + ROUND_UP(device_memory_size, GiB);
1454 if (base < device_memory_base) {
1455 error_report("maxmem/slots too huge");
1456 exit(EXIT_FAILURE);
1457 }
1458 if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
1459 base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
1460 }
1461
1462 for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
1463 hwaddr size = extended_memmap[i].size;
1464
1465 base = ROUND_UP(base, size);
1466 vms->memmap[i].base = base;
1467 vms->memmap[i].size = size;
1468 base += size;
1469 }
1470 vms->highest_gpa = base - 1;
1471 if (device_memory_size > 0) {
1472 ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
1473 ms->device_memory->base = device_memory_base;
1474 memory_region_init(&ms->device_memory->mr, OBJECT(vms),
1475 "device-memory", device_memory_size);
1476 }
1477}
1478
1479static void machvirt_init(MachineState *machine)
1480{
1481 VirtMachineState *vms = VIRT_MACHINE(machine);
1482 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
1483 MachineClass *mc = MACHINE_GET_CLASS(machine);
1484 const CPUArchIdList *possible_cpus;
1485 qemu_irq pic[NUM_IRQS];
1486 MemoryRegion *sysmem = get_system_memory();
1487 MemoryRegion *secure_sysmem = NULL;
1488 int n, virt_max_cpus;
1489 MemoryRegion *ram = g_new(MemoryRegion, 1);
1490 bool firmware_loaded;
1491 bool aarch64 = true;
1492 unsigned int smp_cpus = machine->smp.cpus;
1493 unsigned int max_cpus = machine->smp.max_cpus;
1494
1495 /*
1496 * In accelerated mode, the memory map is computed earlier in kvm_type()
1497 * to create a VM with the right number of IPA bits.
1498 */
1499 if (!vms->memmap) {
1500 virt_set_memmap(vms);
1501 }
1502
1503 /* We can probe only here because during property set
1504 * KVM is not available yet
1505 */
1506 if (vms->gic_version <= 0) {
1507 /* "host" or "max" */
1508 if (!kvm_enabled()) {
1509 if (vms->gic_version == 0) {
1510 error_report("gic-version=host requires KVM");
1511 exit(1);
1512 } else {
1513 /* "max": currently means 3 for TCG */
1514 vms->gic_version = 3;
1515 }
1516 } else {
1517 vms->gic_version = kvm_arm_vgic_probe();
1518 if (!vms->gic_version) {
1519 error_report(
1520 "Unable to determine GIC version supported by host");
1521 exit(1);
1522 }
1523 }
1524 }
1525
1526 if (!cpu_type_valid(machine->cpu_type)) {
1527 error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
1528 exit(1);
1529 }
1530
1531 if (vms->secure) {
1532 if (kvm_enabled()) {
1533 error_report("mach-virt: KVM does not support Security extensions");
1534 exit(1);
1535 }
1536
1537 /*
1538 * The Secure view of the world is the same as the NonSecure,
1539 * but with a few extra devices. Create it as a container region
1540 * containing the system memory at low priority; any secure-only
1541 * devices go in at higher priority and take precedence.
1542 */
1543 secure_sysmem = g_new(MemoryRegion, 1);
1544 memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
1545 UINT64_MAX);
1546 memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
1547 }
1548
1549 firmware_loaded = virt_firmware_init(vms, sysmem,
1550 secure_sysmem ?: sysmem);
1551
1552 /* If we have an EL3 boot ROM then the assumption is that it will
1553 * implement PSCI itself, so disable QEMU's internal implementation
1554 * so it doesn't get in the way. Instead of starting secondary
1555 * CPUs in PSCI powerdown state we will start them all running and
1556 * let the boot ROM sort them out.
1557 * The usual case is that we do use QEMU's PSCI implementation;
1558 * if the guest has EL2 then we will use SMC as the conduit,
1559 * and otherwise we will use HVC (for backwards compatibility and
1560 * because if we're using KVM then we must use HVC).
1561 */
1562 if (vms->secure && firmware_loaded) {
1563 vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
1564 } else if (vms->virt) {
1565 vms->psci_conduit = QEMU_PSCI_CONDUIT_SMC;
1566 } else {
1567 vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
1568 }
1569
1570 /* The maximum number of CPUs depends on the GIC version, or on how
1571 * many redistributors we can fit into the memory map.
1572 */
1573 if (vms->gic_version == 3) {
1574 virt_max_cpus =
1575 vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
1576 virt_max_cpus +=
1577 vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
1578 } else {
1579 virt_max_cpus = GIC_NCPU;
1580 }
1581
1582 if (max_cpus > virt_max_cpus) {
1583 error_report("Number of SMP CPUs requested (%d) exceeds max CPUs "
1584 "supported by machine 'mach-virt' (%d)",
1585 max_cpus, virt_max_cpus);
1586 exit(1);
1587 }
1588
1589 vms->smp_cpus = smp_cpus;
1590
1591 if (vms->virt && kvm_enabled()) {
1592 error_report("mach-virt: KVM does not support providing "
1593 "Virtualization extensions to the guest CPU");
1594 exit(1);
1595 }
1596
1597 create_fdt(vms);
1598
1599 possible_cpus = mc->possible_cpu_arch_ids(machine);
1600 for (n = 0; n < possible_cpus->len; n++) {
1601 Object *cpuobj;
1602 CPUState *cs;
1603
1604 if (n >= smp_cpus) {
1605 break;
1606 }
1607
1608 cpuobj = object_new(possible_cpus->cpus[n].type);
1609 object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id,
1610 "mp-affinity", NULL);
1611
1612 cs = CPU(cpuobj);
1613 cs->cpu_index = n;
1614
1615 numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuobj),
1616 &error_fatal);
1617
1618 aarch64 &= object_property_get_bool(cpuobj, "aarch64", NULL);
1619
1620 if (!vms->secure) {
1621 object_property_set_bool(cpuobj, false, "has_el3", NULL);
1622 }
1623
1624 if (!vms->virt && object_property_find(cpuobj, "has_el2", NULL)) {
1625 object_property_set_bool(cpuobj, false, "has_el2", NULL);
1626 }
1627
1628 if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
1629 object_property_set_int(cpuobj, vms->psci_conduit,
1630 "psci-conduit", NULL);
1631
1632 /* Secondary CPUs start in PSCI powered-down state */
1633 if (n > 0) {
1634 object_property_set_bool(cpuobj, true,
1635 "start-powered-off", NULL);
1636 }
1637 }
1638
1639 if (vmc->no_pmu && object_property_find(cpuobj, "pmu", NULL)) {
1640 object_property_set_bool(cpuobj, false, "pmu", NULL);
1641 }
1642
1643 if (object_property_find(cpuobj, "reset-cbar", NULL)) {
1644 object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].base,
1645 "reset-cbar", &error_abort);
1646 }
1647
1648 object_property_set_link(cpuobj, OBJECT(sysmem), "memory",
1649 &error_abort);
1650 if (vms->secure) {
1651 object_property_set_link(cpuobj, OBJECT(secure_sysmem),
1652 "secure-memory", &error_abort);
1653 }
1654
1655 object_property_set_bool(cpuobj, true, "realized", &error_fatal);
1656 object_unref(cpuobj);
1657 }
1658 fdt_add_timer_nodes(vms);
1659 fdt_add_cpu_nodes(vms);
1660
1661 if (!kvm_enabled()) {
1662 ARMCPU *cpu = ARM_CPU(first_cpu);
1663 bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
1664
1665 if (aarch64 && vms->highmem) {
1666 int requested_pa_size, pamax = arm_pamax(cpu);
1667
1668 requested_pa_size = 64 - clz64(vms->highest_gpa);
1669 if (pamax < requested_pa_size) {
1670 error_report("VCPU supports less PA bits (%d) than requested "
1671 "by the memory map (%d)", pamax, requested_pa_size);
1672 exit(1);
1673 }
1674 }
1675 }
1676
1677 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
1678 machine->ram_size);
1679 memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
1680 if (machine->device_memory) {
1681 memory_region_add_subregion(sysmem, machine->device_memory->base,
1682 &machine->device_memory->mr);
1683 }
1684
1685 virt_flash_fdt(vms, sysmem, secure_sysmem ?: sysmem);
1686
1687 create_gic(vms, pic);
1688
1689 fdt_add_pmu_nodes(vms);
1690
1691 create_uart(vms, pic, VIRT_UART, sysmem, serial_hd(0));
1692
1693 if (vms->secure) {
1694 create_secure_ram(vms, secure_sysmem);
1695 create_uart(vms, pic, VIRT_SECURE_UART, secure_sysmem, serial_hd(1));
1696 }
1697
1698 vms->highmem_ecam &= vms->highmem && (!firmware_loaded || aarch64);
1699
1700 create_rtc(vms, pic);
1701
1702 create_pcie(vms, pic);
1703
1704 create_gpio(vms, pic);
1705
1706 /* Create mmio transports, so the user can create virtio backends
1707 * (which will be automatically plugged in to the transports). If
1708 * no backend is created the transport will just sit harmlessly idle.
1709 */
1710 create_virtio_devices(vms, pic);
1711
1712 vms->fw_cfg = create_fw_cfg(vms, &address_space_memory);
1713 rom_set_fw(vms->fw_cfg);
1714
1715 create_platform_bus(vms, pic);
1716
1717 vms->bootinfo.ram_size = machine->ram_size;
1718 vms->bootinfo.nb_cpus = smp_cpus;
1719 vms->bootinfo.board_id = -1;
1720 vms->bootinfo.loader_start = vms->memmap[VIRT_MEM].base;
1721 vms->bootinfo.get_dtb = machvirt_dtb;
1722 vms->bootinfo.skip_dtb_autoload = true;
1723 vms->bootinfo.firmware_loaded = firmware_loaded;
1724 arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo);
1725
1726 vms->machine_done.notify = virt_machine_done;
1727 qemu_add_machine_init_done_notifier(&vms->machine_done);
1728}
1729
1730static bool virt_get_secure(Object *obj, Error **errp)
1731{
1732 VirtMachineState *vms = VIRT_MACHINE(obj);
1733
1734 return vms->secure;
1735}
1736
1737static void virt_set_secure(Object *obj, bool value, Error **errp)
1738{
1739 VirtMachineState *vms = VIRT_MACHINE(obj);
1740
1741 vms->secure = value;
1742}
1743
1744static bool virt_get_virt(Object *obj, Error **errp)
1745{
1746 VirtMachineState *vms = VIRT_MACHINE(obj);
1747
1748 return vms->virt;
1749}
1750
1751static void virt_set_virt(Object *obj, bool value, Error **errp)
1752{
1753 VirtMachineState *vms = VIRT_MACHINE(obj);
1754
1755 vms->virt = value;
1756}
1757
1758static bool virt_get_highmem(Object *obj, Error **errp)
1759{
1760 VirtMachineState *vms = VIRT_MACHINE(obj);
1761
1762 return vms->highmem;
1763}
1764
1765static void virt_set_highmem(Object *obj, bool value, Error **errp)
1766{
1767 VirtMachineState *vms = VIRT_MACHINE(obj);
1768
1769 vms->highmem = value;
1770}
1771
1772static bool virt_get_its(Object *obj, Error **errp)
1773{
1774 VirtMachineState *vms = VIRT_MACHINE(obj);
1775
1776 return vms->its;
1777}
1778
1779static void virt_set_its(Object *obj, bool value, Error **errp)
1780{
1781 VirtMachineState *vms = VIRT_MACHINE(obj);
1782
1783 vms->its = value;
1784}
1785
1786static char *virt_get_gic_version(Object *obj, Error **errp)
1787{
1788 VirtMachineState *vms = VIRT_MACHINE(obj);
1789 const char *val = vms->gic_version == 3 ? "3" : "2";
1790
1791 return g_strdup(val);
1792}
1793
1794static void virt_set_gic_version(Object *obj, const char *value, Error **errp)
1795{
1796 VirtMachineState *vms = VIRT_MACHINE(obj);
1797
1798 if (!strcmp(value, "3")) {
1799 vms->gic_version = 3;
1800 } else if (!strcmp(value, "2")) {
1801 vms->gic_version = 2;
1802 } else if (!strcmp(value, "host")) {
1803 vms->gic_version = 0; /* Will probe later */
1804 } else if (!strcmp(value, "max")) {
1805 vms->gic_version = -1; /* Will probe later */
1806 } else {
1807 error_setg(errp, "Invalid gic-version value");
1808 error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
1809 }
1810}
1811
1812static char *virt_get_iommu(Object *obj, Error **errp)
1813{
1814 VirtMachineState *vms = VIRT_MACHINE(obj);
1815
1816 switch (vms->iommu) {
1817 case VIRT_IOMMU_NONE:
1818 return g_strdup("none");
1819 case VIRT_IOMMU_SMMUV3:
1820 return g_strdup("smmuv3");
1821 default:
1822 g_assert_not_reached();
1823 }
1824}
1825
1826static void virt_set_iommu(Object *obj, const char *value, Error **errp)
1827{
1828 VirtMachineState *vms = VIRT_MACHINE(obj);
1829
1830 if (!strcmp(value, "smmuv3")) {
1831 vms->iommu = VIRT_IOMMU_SMMUV3;
1832 } else if (!strcmp(value, "none")) {
1833 vms->iommu = VIRT_IOMMU_NONE;
1834 } else {
1835 error_setg(errp, "Invalid iommu value");
1836 error_append_hint(errp, "Valid values are none, smmuv3.\n");
1837 }
1838}
1839
1840static CpuInstanceProperties
1841virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
1842{
1843 MachineClass *mc = MACHINE_GET_CLASS(ms);
1844 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms);
1845
1846 assert(cpu_index < possible_cpus->len);
1847 return possible_cpus->cpus[cpu_index].props;
1848}
1849
1850static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx)
1851{
1852 return idx % ms->numa_state->num_nodes;
1853}
1854
1855static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms)
1856{
1857 int n;
1858 unsigned int max_cpus = ms->smp.max_cpus;
1859 VirtMachineState *vms = VIRT_MACHINE(ms);
1860
1861 if (ms->possible_cpus) {
1862 assert(ms->possible_cpus->len == max_cpus);
1863 return ms->possible_cpus;
1864 }
1865
1866 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) +
1867 sizeof(CPUArchId) * max_cpus);
1868 ms->possible_cpus->len = max_cpus;
1869 for (n = 0; n < ms->possible_cpus->len; n++) {
1870 ms->possible_cpus->cpus[n].type = ms->cpu_type;
1871 ms->possible_cpus->cpus[n].arch_id =
1872 virt_cpu_mp_affinity(vms, n);
1873 ms->possible_cpus->cpus[n].props.has_thread_id = true;
1874 ms->possible_cpus->cpus[n].props.thread_id = n;
1875 }
1876 return ms->possible_cpus;
1877}
1878
1879static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev,
1880 DeviceState *dev, Error **errp)
1881{
1882 VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
1883
1884 if (vms->platform_bus_dev) {
1885 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1886 platform_bus_link_device(PLATFORM_BUS_DEVICE(vms->platform_bus_dev),
1887 SYS_BUS_DEVICE(dev));
1888 }
1889 }
1890}
1891
1892static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
1893 DeviceState *dev)
1894{
1895 if (object_dynamic_cast(OBJECT(dev), TYPE_SYS_BUS_DEVICE)) {
1896 return HOTPLUG_HANDLER(machine);
1897 }
1898
1899 return NULL;
1900}
1901
1902/*
1903 * for arm64 kvm_type [7-0] encodes the requested number of bits
1904 * in the IPA address space
1905 */
1906static int virt_kvm_type(MachineState *ms, const char *type_str)
1907{
1908 VirtMachineState *vms = VIRT_MACHINE(ms);
1909 int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
1910 int requested_pa_size;
1911
1912 /* we freeze the memory map to compute the highest gpa */
1913 virt_set_memmap(vms);
1914
1915 requested_pa_size = 64 - clz64(vms->highest_gpa);
1916
1917 if (requested_pa_size > max_vm_pa_size) {
1918 error_report("-m and ,maxmem option values "
1919 "require an IPA range (%d bits) larger than "
1920 "the one supported by the host (%d bits)",
1921 requested_pa_size, max_vm_pa_size);
1922 exit(1);
1923 }
1924 /*
1925 * By default we return 0 which corresponds to an implicit legacy
1926 * 40b IPA setting. Otherwise we return the actual requested PA
1927 * logsize
1928 */
1929 return requested_pa_size > 40 ? requested_pa_size : 0;
1930}
1931
1932static void virt_machine_class_init(ObjectClass *oc, void *data)
1933{
1934 MachineClass *mc = MACHINE_CLASS(oc);
1935 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
1936
1937 mc->init = machvirt_init;
1938 /* Start with max_cpus set to 512, which is the maximum supported by KVM.
1939 * The value may be reduced later when we have more information about the
1940 * configuration of the particular instance.
1941 */
1942 mc->max_cpus = 512;
1943 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_CALXEDA_XGMAC);
1944 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE);
1945 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE);
1946 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM);
1947 mc->block_default_type = IF_VIRTIO;
1948 mc->no_cdrom = 1;
1949 mc->pci_allow_0_address = true;
1950 /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */
1951 mc->minimum_page_bits = 12;
1952 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids;
1953 mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
1954 mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
1955 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
1956 mc->kvm_type = virt_kvm_type;
1957 assert(!mc->get_hotplug_handler);
1958 mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
1959 hc->plug = virt_machine_device_plug_cb;
1960 mc->numa_mem_supported = true;
1961}
1962
1963static void virt_instance_init(Object *obj)
1964{
1965 VirtMachineState *vms = VIRT_MACHINE(obj);
1966 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
1967
1968 /* EL3 is disabled by default on virt: this makes us consistent
1969 * between KVM and TCG for this board, and it also allows us to
1970 * boot UEFI blobs which assume no TrustZone support.
1971 */
1972 vms->secure = false;
1973 object_property_add_bool(obj, "secure", virt_get_secure,
1974 virt_set_secure, NULL);
1975 object_property_set_description(obj, "secure",
1976 "Set on/off to enable/disable the ARM "
1977 "Security Extensions (TrustZone)",
1978 NULL);
1979
1980 /* EL2 is also disabled by default, for similar reasons */
1981 vms->virt = false;
1982 object_property_add_bool(obj, "virtualization", virt_get_virt,
1983 virt_set_virt, NULL);
1984 object_property_set_description(obj, "virtualization",
1985 "Set on/off to enable/disable emulating a "
1986 "guest CPU which implements the ARM "
1987 "Virtualization Extensions",
1988 NULL);
1989
1990 /* High memory is enabled by default */
1991 vms->highmem = true;
1992 object_property_add_bool(obj, "highmem", virt_get_highmem,
1993 virt_set_highmem, NULL);
1994 object_property_set_description(obj, "highmem",
1995 "Set on/off to enable/disable using "
1996 "physical address space above 32 bits",
1997 NULL);
1998 /* Default GIC type is v2 */
1999 vms->gic_version = 2;
2000 object_property_add_str(obj, "gic-version", virt_get_gic_version,
2001 virt_set_gic_version, NULL);
2002 object_property_set_description(obj, "gic-version",
2003 "Set GIC version. "
2004 "Valid values are 2, 3 and host", NULL);
2005
2006 vms->highmem_ecam = !vmc->no_highmem_ecam;
2007
2008 if (vmc->no_its) {
2009 vms->its = false;
2010 } else {
2011 /* Default allows ITS instantiation */
2012 vms->its = true;
2013 object_property_add_bool(obj, "its", virt_get_its,
2014 virt_set_its, NULL);
2015 object_property_set_description(obj, "its",
2016 "Set on/off to enable/disable "
2017 "ITS instantiation",
2018 NULL);
2019 }
2020
2021 /* Default disallows iommu instantiation */
2022 vms->iommu = VIRT_IOMMU_NONE;
2023 object_property_add_str(obj, "iommu", virt_get_iommu, virt_set_iommu, NULL);
2024 object_property_set_description(obj, "iommu",
2025 "Set the IOMMU type. "
2026 "Valid values are none and smmuv3",
2027 NULL);
2028
2029 vms->irqmap = a15irqmap;
2030
2031 virt_flash_create(vms);
2032}
2033
2034static const TypeInfo virt_machine_info = {
2035 .name = TYPE_VIRT_MACHINE,
2036 .parent = TYPE_MACHINE,
2037 .abstract = true,
2038 .instance_size = sizeof(VirtMachineState),
2039 .class_size = sizeof(VirtMachineClass),
2040 .class_init = virt_machine_class_init,
2041 .instance_init = virt_instance_init,
2042 .interfaces = (InterfaceInfo[]) {
2043 { TYPE_HOTPLUG_HANDLER },
2044 { }
2045 },
2046};
2047
2048static void machvirt_machine_init(void)
2049{
2050 type_register_static(&virt_machine_info);
2051}
2052type_init(machvirt_machine_init);
2053
2054static void virt_machine_4_2_options(MachineClass *mc)
2055{
2056}
2057DEFINE_VIRT_MACHINE_AS_LATEST(4, 2)
2058
2059static void virt_machine_4_1_options(MachineClass *mc)
2060{
2061 virt_machine_4_2_options(mc);
2062 compat_props_add(mc->compat_props, hw_compat_4_1, hw_compat_4_1_len);
2063}
2064DEFINE_VIRT_MACHINE(4, 1)
2065
2066static void virt_machine_4_0_options(MachineClass *mc)
2067{
2068 virt_machine_4_1_options(mc);
2069 compat_props_add(mc->compat_props, hw_compat_4_0, hw_compat_4_0_len);
2070}
2071DEFINE_VIRT_MACHINE(4, 0)
2072
2073static void virt_machine_3_1_options(MachineClass *mc)
2074{
2075 virt_machine_4_0_options(mc);
2076 compat_props_add(mc->compat_props, hw_compat_3_1, hw_compat_3_1_len);
2077}
2078DEFINE_VIRT_MACHINE(3, 1)
2079
2080static void virt_machine_3_0_options(MachineClass *mc)
2081{
2082 virt_machine_3_1_options(mc);
2083 compat_props_add(mc->compat_props, hw_compat_3_0, hw_compat_3_0_len);
2084}
2085DEFINE_VIRT_MACHINE(3, 0)
2086
2087static void virt_machine_2_12_options(MachineClass *mc)
2088{
2089 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2090
2091 virt_machine_3_0_options(mc);
2092 compat_props_add(mc->compat_props, hw_compat_2_12, hw_compat_2_12_len);
2093 vmc->no_highmem_ecam = true;
2094 mc->max_cpus = 255;
2095}
2096DEFINE_VIRT_MACHINE(2, 12)
2097
2098static void virt_machine_2_11_options(MachineClass *mc)
2099{
2100 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2101
2102 virt_machine_2_12_options(mc);
2103 compat_props_add(mc->compat_props, hw_compat_2_11, hw_compat_2_11_len);
2104 vmc->smbios_old_sys_ver = true;
2105}
2106DEFINE_VIRT_MACHINE(2, 11)
2107
2108static void virt_machine_2_10_options(MachineClass *mc)
2109{
2110 virt_machine_2_11_options(mc);
2111 compat_props_add(mc->compat_props, hw_compat_2_10, hw_compat_2_10_len);
2112 /* before 2.11 we never faulted accesses to bad addresses */
2113 mc->ignore_memory_transaction_failures = true;
2114}
2115DEFINE_VIRT_MACHINE(2, 10)
2116
2117static void virt_machine_2_9_options(MachineClass *mc)
2118{
2119 virt_machine_2_10_options(mc);
2120 compat_props_add(mc->compat_props, hw_compat_2_9, hw_compat_2_9_len);
2121}
2122DEFINE_VIRT_MACHINE(2, 9)
2123
2124static void virt_machine_2_8_options(MachineClass *mc)
2125{
2126 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2127
2128 virt_machine_2_9_options(mc);
2129 compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len);
2130 /* For 2.8 and earlier we falsely claimed in the DT that
2131 * our timers were edge-triggered, not level-triggered.
2132 */
2133 vmc->claim_edge_triggered_timers = true;
2134}
2135DEFINE_VIRT_MACHINE(2, 8)
2136
2137static void virt_machine_2_7_options(MachineClass *mc)
2138{
2139 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2140
2141 virt_machine_2_8_options(mc);
2142 compat_props_add(mc->compat_props, hw_compat_2_7, hw_compat_2_7_len);
2143 /* ITS was introduced with 2.8 */
2144 vmc->no_its = true;
2145 /* Stick with 1K pages for migration compatibility */
2146 mc->minimum_page_bits = 0;
2147}
2148DEFINE_VIRT_MACHINE(2, 7)
2149
2150static void virt_machine_2_6_options(MachineClass *mc)
2151{
2152 VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
2153
2154 virt_machine_2_7_options(mc);
2155 compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len);
2156 vmc->disallow_affinity_adjustment = true;
2157 /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */
2158 vmc->no_pmu = true;
2159}
2160DEFINE_VIRT_MACHINE(2, 6)
2161