1 | /* |
2 | * Xilinx Zynq Baseboard System emulation. |
3 | * |
4 | * Copyright (c) 2010 Xilinx. |
5 | * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.croshtwaite@petalogix.com) |
6 | * Copyright (c) 2012 Petalogix Pty Ltd. |
7 | * Written by Haibing Ma |
8 | * |
9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License |
11 | * as published by the Free Software Foundation; either version |
12 | * 2 of the License, or (at your option) any later version. |
13 | * |
14 | * You should have received a copy of the GNU General Public License along |
15 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
16 | */ |
17 | |
18 | #include "qemu/osdep.h" |
19 | #include "qapi/error.h" |
20 | #include "cpu.h" |
21 | #include "hw/sysbus.h" |
22 | #include "hw/arm/boot.h" |
23 | #include "net/net.h" |
24 | #include "exec/address-spaces.h" |
25 | #include "sysemu/sysemu.h" |
26 | #include "hw/boards.h" |
27 | #include "hw/block/flash.h" |
28 | #include "hw/loader.h" |
29 | #include "hw/misc/zynq-xadc.h" |
30 | #include "hw/ssi/ssi.h" |
31 | #include "qemu/error-report.h" |
32 | #include "hw/sd/sdhci.h" |
33 | #include "hw/char/cadence_uart.h" |
34 | #include "hw/net/cadence_gem.h" |
35 | #include "hw/cpu/a9mpcore.h" |
36 | |
37 | #define NUM_SPI_FLASHES 4 |
38 | #define NUM_QSPI_FLASHES 2 |
39 | #define NUM_QSPI_BUSSES 2 |
40 | |
41 | #define FLASH_SIZE (64 * 1024 * 1024) |
42 | #define FLASH_SECTOR_SIZE (128 * 1024) |
43 | |
44 | #define IRQ_OFFSET 32 /* pic interrupts start from index 32 */ |
45 | |
46 | #define MPCORE_PERIPHBASE 0xF8F00000 |
47 | #define ZYNQ_BOARD_MIDR 0x413FC090 |
48 | |
49 | static const int dma_irqs[8] = { |
50 | 46, 47, 48, 49, 72, 73, 74, 75 |
51 | }; |
52 | |
53 | #define BOARD_SETUP_ADDR 0x100 |
54 | |
55 | #define SLCR_LOCK_OFFSET 0x004 |
56 | #define SLCR_UNLOCK_OFFSET 0x008 |
57 | #define SLCR_ARM_PLL_OFFSET 0x100 |
58 | |
59 | #define SLCR_XILINX_UNLOCK_KEY 0xdf0d |
60 | #define SLCR_XILINX_LOCK_KEY 0x767b |
61 | |
62 | #define ZYNQ_SDHCI_CAPABILITIES 0x69ec0080 /* Datasheet: UG585 (v1.12.1) */ |
63 | |
64 | #define ARMV7_IMM16(x) (extract32((x), 0, 12) | \ |
65 | extract32((x), 12, 4) << 16) |
66 | |
67 | /* Write immediate val to address r0 + addr. r0 should contain base offset |
68 | * of the SLCR block. Clobbers r1. |
69 | */ |
70 | |
71 | #define SLCR_WRITE(addr, val) \ |
72 | 0xe3001000 + ARMV7_IMM16(extract32((val), 0, 16)), /* movw r1 ... */ \ |
73 | 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ |
74 | 0xe5801000 + (addr) |
75 | |
76 | static void zynq_write_board_setup(ARMCPU *cpu, |
77 | const struct arm_boot_info *info) |
78 | { |
79 | int n; |
80 | uint32_t board_setup_blob[] = { |
81 | 0xe3a004f8, /* mov r0, #0xf8000000 */ |
82 | SLCR_WRITE(SLCR_UNLOCK_OFFSET, SLCR_XILINX_UNLOCK_KEY), |
83 | SLCR_WRITE(SLCR_ARM_PLL_OFFSET, 0x00014008), |
84 | SLCR_WRITE(SLCR_LOCK_OFFSET, SLCR_XILINX_LOCK_KEY), |
85 | 0xe12fff1e, /* bx lr */ |
86 | }; |
87 | for (n = 0; n < ARRAY_SIZE(board_setup_blob); n++) { |
88 | board_setup_blob[n] = tswap32(board_setup_blob[n]); |
89 | } |
90 | rom_add_blob_fixed("board-setup" , board_setup_blob, |
91 | sizeof(board_setup_blob), BOARD_SETUP_ADDR); |
92 | } |
93 | |
94 | static struct arm_boot_info zynq_binfo = {}; |
95 | |
96 | static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) |
97 | { |
98 | DeviceState *dev; |
99 | SysBusDevice *s; |
100 | |
101 | dev = qdev_create(NULL, TYPE_CADENCE_GEM); |
102 | if (nd->used) { |
103 | qemu_check_nic_model(nd, TYPE_CADENCE_GEM); |
104 | qdev_set_nic_properties(dev, nd); |
105 | } |
106 | qdev_init_nofail(dev); |
107 | s = SYS_BUS_DEVICE(dev); |
108 | sysbus_mmio_map(s, 0, base); |
109 | sysbus_connect_irq(s, 0, irq); |
110 | } |
111 | |
112 | static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, |
113 | bool is_qspi) |
114 | { |
115 | DeviceState *dev; |
116 | SysBusDevice *busdev; |
117 | SSIBus *spi; |
118 | DeviceState *flash_dev; |
119 | int i, j; |
120 | int num_busses = is_qspi ? NUM_QSPI_BUSSES : 1; |
121 | int num_ss = is_qspi ? NUM_QSPI_FLASHES : NUM_SPI_FLASHES; |
122 | |
123 | dev = qdev_create(NULL, is_qspi ? "xlnx.ps7-qspi" : "xlnx.ps7-spi" ); |
124 | qdev_prop_set_uint8(dev, "num-txrx-bytes" , is_qspi ? 4 : 1); |
125 | qdev_prop_set_uint8(dev, "num-ss-bits" , num_ss); |
126 | qdev_prop_set_uint8(dev, "num-busses" , num_busses); |
127 | qdev_init_nofail(dev); |
128 | busdev = SYS_BUS_DEVICE(dev); |
129 | sysbus_mmio_map(busdev, 0, base_addr); |
130 | if (is_qspi) { |
131 | sysbus_mmio_map(busdev, 1, 0xFC000000); |
132 | } |
133 | sysbus_connect_irq(busdev, 0, irq); |
134 | |
135 | for (i = 0; i < num_busses; ++i) { |
136 | char bus_name[16]; |
137 | qemu_irq cs_line; |
138 | |
139 | snprintf(bus_name, 16, "spi%d" , i); |
140 | spi = (SSIBus *)qdev_get_child_bus(dev, bus_name); |
141 | |
142 | for (j = 0; j < num_ss; ++j) { |
143 | DriveInfo *dinfo = drive_get_next(IF_MTD); |
144 | flash_dev = ssi_create_slave_no_init(spi, "n25q128" ); |
145 | if (dinfo) { |
146 | qdev_prop_set_drive(flash_dev, "drive" , |
147 | blk_by_legacy_dinfo(dinfo), &error_fatal); |
148 | } |
149 | qdev_init_nofail(flash_dev); |
150 | |
151 | cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); |
152 | sysbus_connect_irq(busdev, i * num_ss + j + 1, cs_line); |
153 | } |
154 | } |
155 | |
156 | } |
157 | |
158 | static void zynq_init(MachineState *machine) |
159 | { |
160 | ram_addr_t ram_size = machine->ram_size; |
161 | ARMCPU *cpu; |
162 | MemoryRegion *address_space_mem = get_system_memory(); |
163 | MemoryRegion *ext_ram = g_new(MemoryRegion, 1); |
164 | MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); |
165 | DeviceState *dev; |
166 | SysBusDevice *busdev; |
167 | qemu_irq pic[64]; |
168 | int n; |
169 | |
170 | cpu = ARM_CPU(object_new(machine->cpu_type)); |
171 | |
172 | /* By default A9 CPUs have EL3 enabled. This board does not |
173 | * currently support EL3 so the CPU EL3 property is disabled before |
174 | * realization. |
175 | */ |
176 | if (object_property_find(OBJECT(cpu), "has_el3" , NULL)) { |
177 | object_property_set_bool(OBJECT(cpu), false, "has_el3" , &error_fatal); |
178 | } |
179 | |
180 | object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr" , |
181 | &error_fatal); |
182 | object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar" , |
183 | &error_fatal); |
184 | object_property_set_bool(OBJECT(cpu), true, "realized" , &error_fatal); |
185 | |
186 | /* max 2GB ram */ |
187 | if (ram_size > 0x80000000) { |
188 | ram_size = 0x80000000; |
189 | } |
190 | |
191 | /* DDR remapped to address zero. */ |
192 | memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram" , |
193 | ram_size); |
194 | memory_region_add_subregion(address_space_mem, 0, ext_ram); |
195 | |
196 | /* 256K of on-chip memory */ |
197 | memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram" , 256 << 10, |
198 | &error_fatal); |
199 | memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); |
200 | |
201 | DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); |
202 | |
203 | /* AMD */ |
204 | pflash_cfi02_register(0xe2000000, "zynq.pflash" , FLASH_SIZE, |
205 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
206 | FLASH_SECTOR_SIZE, 1, |
207 | 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, |
208 | 0); |
209 | |
210 | dev = qdev_create(NULL, "xilinx,zynq_slcr" ); |
211 | qdev_init_nofail(dev); |
212 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); |
213 | |
214 | dev = qdev_create(NULL, TYPE_A9MPCORE_PRIV); |
215 | qdev_prop_set_uint32(dev, "num-cpu" , 1); |
216 | qdev_init_nofail(dev); |
217 | busdev = SYS_BUS_DEVICE(dev); |
218 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); |
219 | sysbus_connect_irq(busdev, 0, |
220 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); |
221 | |
222 | for (n = 0; n < 64; n++) { |
223 | pic[n] = qdev_get_gpio_in(dev, n); |
224 | } |
225 | |
226 | zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET], false); |
227 | zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); |
228 | zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); |
229 | |
230 | sysbus_create_simple("xlnx,ps7-usb" , 0xE0002000, pic[53-IRQ_OFFSET]); |
231 | sysbus_create_simple("xlnx,ps7-usb" , 0xE0003000, pic[76-IRQ_OFFSET]); |
232 | |
233 | cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); |
234 | cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); |
235 | |
236 | sysbus_create_varargs("cadence_ttc" , 0xF8001000, |
237 | pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NULL); |
238 | sysbus_create_varargs("cadence_ttc" , 0xF8002000, |
239 | pic[69-IRQ_OFFSET], pic[70-IRQ_OFFSET], pic[71-IRQ_OFFSET], NULL); |
240 | |
241 | gem_init(&nd_table[0], 0xE000B000, pic[54-IRQ_OFFSET]); |
242 | gem_init(&nd_table[1], 0xE000C000, pic[77-IRQ_OFFSET]); |
243 | |
244 | for (n = 0; n < 2; n++) { |
245 | int hci_irq = n ? 79 : 56; |
246 | hwaddr hci_addr = n ? 0xE0101000 : 0xE0100000; |
247 | DriveInfo *di; |
248 | BlockBackend *blk; |
249 | DeviceState *carddev; |
250 | |
251 | /* Compatible with: |
252 | * - SD Host Controller Specification Version 2.0 Part A2 |
253 | * - SDIO Specification Version 2.0 |
254 | * - MMC Specification Version 3.31 |
255 | */ |
256 | dev = qdev_create(NULL, TYPE_SYSBUS_SDHCI); |
257 | qdev_prop_set_uint8(dev, "sd-spec-version" , 2); |
258 | qdev_prop_set_uint64(dev, "capareg" , ZYNQ_SDHCI_CAPABILITIES); |
259 | qdev_init_nofail(dev); |
260 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, hci_addr); |
261 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[hci_irq - IRQ_OFFSET]); |
262 | |
263 | di = drive_get_next(IF_SD); |
264 | blk = di ? blk_by_legacy_dinfo(di) : NULL; |
265 | carddev = qdev_create(qdev_get_child_bus(dev, "sd-bus" ), TYPE_SD_CARD); |
266 | qdev_prop_set_drive(carddev, "drive" , blk, &error_fatal); |
267 | object_property_set_bool(OBJECT(carddev), true, "realized" , |
268 | &error_fatal); |
269 | } |
270 | |
271 | dev = qdev_create(NULL, TYPE_ZYNQ_XADC); |
272 | qdev_init_nofail(dev); |
273 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8007100); |
274 | sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[39-IRQ_OFFSET]); |
275 | |
276 | dev = qdev_create(NULL, "pl330" ); |
277 | qdev_prop_set_uint8(dev, "num_chnls" , 8); |
278 | qdev_prop_set_uint8(dev, "num_periph_req" , 4); |
279 | qdev_prop_set_uint8(dev, "num_events" , 16); |
280 | |
281 | qdev_prop_set_uint8(dev, "data_width" , 64); |
282 | qdev_prop_set_uint8(dev, "wr_cap" , 8); |
283 | qdev_prop_set_uint8(dev, "wr_q_dep" , 16); |
284 | qdev_prop_set_uint8(dev, "rd_cap" , 8); |
285 | qdev_prop_set_uint8(dev, "rd_q_dep" , 16); |
286 | qdev_prop_set_uint16(dev, "data_buffer_dep" , 256); |
287 | |
288 | qdev_init_nofail(dev); |
289 | busdev = SYS_BUS_DEVICE(dev); |
290 | sysbus_mmio_map(busdev, 0, 0xF8003000); |
291 | sysbus_connect_irq(busdev, 0, pic[45-IRQ_OFFSET]); /* abort irq line */ |
292 | for (n = 0; n < ARRAY_SIZE(dma_irqs); ++n) { /* event irqs */ |
293 | sysbus_connect_irq(busdev, n + 1, pic[dma_irqs[n] - IRQ_OFFSET]); |
294 | } |
295 | |
296 | dev = qdev_create(NULL, "xlnx.ps7-dev-cfg" ); |
297 | qdev_init_nofail(dev); |
298 | busdev = SYS_BUS_DEVICE(dev); |
299 | sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); |
300 | sysbus_mmio_map(busdev, 0, 0xF8007000); |
301 | |
302 | zynq_binfo.ram_size = ram_size; |
303 | zynq_binfo.nb_cpus = 1; |
304 | zynq_binfo.board_id = 0xd32; |
305 | zynq_binfo.loader_start = 0; |
306 | zynq_binfo.board_setup_addr = BOARD_SETUP_ADDR; |
307 | zynq_binfo.write_board_setup = zynq_write_board_setup; |
308 | |
309 | arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); |
310 | } |
311 | |
312 | static void zynq_machine_init(MachineClass *mc) |
313 | { |
314 | mc->desc = "Xilinx Zynq Platform Baseboard for Cortex-A9" ; |
315 | mc->init = zynq_init; |
316 | mc->max_cpus = 1; |
317 | mc->no_sdcard = 1; |
318 | mc->ignore_memory_transaction_failures = true; |
319 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a9" ); |
320 | } |
321 | |
322 | DEFINE_MACHINE("xilinx-zynq-a9" , zynq_machine_init) |
323 | |