1 | /* |
2 | * SD Association Host Standard Specification v2.0 controller emulation |
3 | * |
4 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
5 | * Mitsyanko Igor <i.mitsyanko@samsung.com> |
6 | * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> |
7 | * |
8 | * Based on MMC controller for Samsung S5PC1xx-based board emulation |
9 | * by Alexey Merkulov and Vladimir Monakhov. |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it |
12 | * under the terms of the GNU General Public License as published by the |
13 | * Free Software Foundation; either version 2 of the License, or (at your |
14 | * option) any later version. |
15 | * |
16 | * This program is distributed in the hope that it will be useful, |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
19 | * See the GNU General Public License for more details. |
20 | * |
21 | * You should have received a copy of the GNU _General Public License along |
22 | * with this program; if not, see <http://www.gnu.org/licenses/>. |
23 | */ |
24 | |
25 | #ifndef SDHCI_H |
26 | #define SDHCI_H |
27 | |
28 | #include "hw/pci/pci.h" |
29 | #include "hw/sysbus.h" |
30 | #include "hw/sd/sd.h" |
31 | |
32 | /* SD/MMC host controller state */ |
33 | typedef struct SDHCIState { |
34 | /*< private >*/ |
35 | union { |
36 | PCIDevice pcidev; |
37 | SysBusDevice busdev; |
38 | }; |
39 | |
40 | /*< public >*/ |
41 | SDBus sdbus; |
42 | MemoryRegion iomem; |
43 | AddressSpace sysbus_dma_as; |
44 | AddressSpace *dma_as; |
45 | MemoryRegion *dma_mr; |
46 | const MemoryRegionOps *io_ops; |
47 | |
48 | QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ |
49 | QEMUTimer *transfer_timer; |
50 | qemu_irq irq; |
51 | |
52 | /* Registers cleared on reset */ |
53 | uint32_t sdmasysad; /* SDMA System Address register */ |
54 | uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ |
55 | uint16_t blkcnt; /* Blocks count for current transfer */ |
56 | uint32_t argument; /* Command Argument Register */ |
57 | uint16_t trnmod; /* Transfer Mode Setting Register */ |
58 | uint16_t cmdreg; /* Command Register */ |
59 | uint32_t rspreg[4]; /* Response Registers 0-3 */ |
60 | uint32_t prnsts; /* Present State Register */ |
61 | uint8_t hostctl1; /* Host Control Register */ |
62 | uint8_t pwrcon; /* Power control Register */ |
63 | uint8_t blkgap; /* Block Gap Control Register */ |
64 | uint8_t wakcon; /* WakeUp Control Register */ |
65 | uint16_t clkcon; /* Clock control Register */ |
66 | uint8_t timeoutcon; /* Timeout Control Register */ |
67 | uint8_t admaerr; /* ADMA Error Status Register */ |
68 | uint16_t norintsts; /* Normal Interrupt Status Register */ |
69 | uint16_t errintsts; /* Error Interrupt Status Register */ |
70 | uint16_t norintstsen; /* Normal Interrupt Status Enable Register */ |
71 | uint16_t errintstsen; /* Error Interrupt Status Enable Register */ |
72 | uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */ |
73 | uint16_t errintsigen; /* Error Interrupt Signal Enable Register */ |
74 | uint16_t acmd12errsts; /* Auto CMD12 error status register */ |
75 | uint16_t hostctl2; /* Host Control 2 */ |
76 | uint64_t admasysaddr; /* ADMA System Address Register */ |
77 | |
78 | /* Read-only registers */ |
79 | uint64_t capareg; /* Capabilities Register */ |
80 | uint64_t maxcurr; /* Maximum Current Capabilities Register */ |
81 | uint16_t version; /* Host Controller Version Register */ |
82 | |
83 | uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ |
84 | uint32_t buf_maxsz; |
85 | uint16_t data_count; /* current element in FIFO buffer */ |
86 | uint8_t stopped_state;/* Current SDHC state */ |
87 | bool pending_insert_state; |
88 | /* Buffer Data Port Register - virtual access point to R and W buffers */ |
89 | /* Software Reset Register - always reads as 0 */ |
90 | /* Force Event Auto CMD12 Error Interrupt Reg - write only */ |
91 | /* Force Event Error Interrupt Register- write only */ |
92 | /* RO Host Controller Version Register always reads as 0x2401 */ |
93 | |
94 | /* Configurable properties */ |
95 | bool pending_insert_quirk; /* Quirk for Raspberry Pi card insert int */ |
96 | uint32_t quirks; |
97 | uint8_t sd_spec_version; |
98 | uint8_t uhs_mode; |
99 | } SDHCIState; |
100 | |
101 | /* |
102 | * Controller does not provide transfer-complete interrupt when not |
103 | * busy. |
104 | * |
105 | * NOTE: This definition is taken out of Linux kernel and so the |
106 | * original bit number is preserved |
107 | */ |
108 | #define SDHCI_QUIRK_NO_BUSY_IRQ BIT(14) |
109 | |
110 | #define TYPE_PCI_SDHCI "sdhci-pci" |
111 | #define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI) |
112 | |
113 | #define TYPE_SYSBUS_SDHCI "generic-sdhci" |
114 | #define SYSBUS_SDHCI(obj) \ |
115 | OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI) |
116 | |
117 | #define TYPE_IMX_USDHC "imx-usdhc" |
118 | |
119 | #endif /* SDHCI_H */ |
120 | |