1 | /* |
2 | * QEMU IDE Emulation: PCI cmd646 support. |
3 | * |
4 | * Copyright (c) 2003 Fabrice Bellard |
5 | * Copyright (c) 2006 Openedhand Ltd. |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal |
9 | * in the Software without restriction, including without limitation the rights |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
11 | * copies of the Software, and to permit persons to whom the Software is |
12 | * furnished to do so, subject to the following conditions: |
13 | * |
14 | * The above copyright notice and this permission notice shall be included in |
15 | * all copies or substantial portions of the Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
23 | * THE SOFTWARE. |
24 | */ |
25 | |
26 | #include "qemu/osdep.h" |
27 | #include "hw/pci/pci.h" |
28 | #include "hw/qdev-properties.h" |
29 | #include "migration/vmstate.h" |
30 | #include "qemu/module.h" |
31 | #include "hw/isa/isa.h" |
32 | #include "sysemu/dma.h" |
33 | #include "sysemu/reset.h" |
34 | |
35 | #include "hw/ide/pci.h" |
36 | #include "trace.h" |
37 | |
38 | /* CMD646 specific */ |
39 | #define CFR 0x50 |
40 | #define CFR_INTR_CH0 0x04 |
41 | #define CNTRL 0x51 |
42 | #define CNTRL_EN_CH0 0x04 |
43 | #define CNTRL_EN_CH1 0x08 |
44 | #define ARTTIM23 0x57 |
45 | #define ARTTIM23_INTR_CH1 0x10 |
46 | #define MRDMODE 0x71 |
47 | #define MRDMODE_INTR_CH0 0x04 |
48 | #define MRDMODE_INTR_CH1 0x08 |
49 | #define MRDMODE_BLK_CH0 0x10 |
50 | #define MRDMODE_BLK_CH1 0x20 |
51 | #define UDIDETCR0 0x73 |
52 | #define UDIDETCR1 0x7B |
53 | |
54 | static void cmd646_update_irq(PCIDevice *pd); |
55 | |
56 | static void cmd646_update_dma_interrupts(PCIDevice *pd) |
57 | { |
58 | /* Sync DMA interrupt status from UDMA interrupt status */ |
59 | if (pd->config[MRDMODE] & MRDMODE_INTR_CH0) { |
60 | pd->config[CFR] |= CFR_INTR_CH0; |
61 | } else { |
62 | pd->config[CFR] &= ~CFR_INTR_CH0; |
63 | } |
64 | |
65 | if (pd->config[MRDMODE] & MRDMODE_INTR_CH1) { |
66 | pd->config[ARTTIM23] |= ARTTIM23_INTR_CH1; |
67 | } else { |
68 | pd->config[ARTTIM23] &= ~ARTTIM23_INTR_CH1; |
69 | } |
70 | } |
71 | |
72 | static void cmd646_update_udma_interrupts(PCIDevice *pd) |
73 | { |
74 | /* Sync UDMA interrupt status from DMA interrupt status */ |
75 | if (pd->config[CFR] & CFR_INTR_CH0) { |
76 | pd->config[MRDMODE] |= MRDMODE_INTR_CH0; |
77 | } else { |
78 | pd->config[MRDMODE] &= ~MRDMODE_INTR_CH0; |
79 | } |
80 | |
81 | if (pd->config[ARTTIM23] & ARTTIM23_INTR_CH1) { |
82 | pd->config[MRDMODE] |= MRDMODE_INTR_CH1; |
83 | } else { |
84 | pd->config[MRDMODE] &= ~MRDMODE_INTR_CH1; |
85 | } |
86 | } |
87 | |
88 | static uint64_t bmdma_read(void *opaque, hwaddr addr, |
89 | unsigned size) |
90 | { |
91 | BMDMAState *bm = opaque; |
92 | PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); |
93 | uint32_t val; |
94 | |
95 | if (size != 1) { |
96 | return ((uint64_t)1 << (size * 8)) - 1; |
97 | } |
98 | |
99 | switch(addr & 3) { |
100 | case 0: |
101 | val = bm->cmd; |
102 | break; |
103 | case 1: |
104 | val = pci_dev->config[MRDMODE]; |
105 | break; |
106 | case 2: |
107 | val = bm->status; |
108 | break; |
109 | case 3: |
110 | if (bm == &bm->pci_dev->bmdma[0]) { |
111 | val = pci_dev->config[UDIDETCR0]; |
112 | } else { |
113 | val = pci_dev->config[UDIDETCR1]; |
114 | } |
115 | break; |
116 | default: |
117 | val = 0xff; |
118 | break; |
119 | } |
120 | |
121 | trace_bmdma_read_cmd646(addr, val); |
122 | return val; |
123 | } |
124 | |
125 | static void bmdma_write(void *opaque, hwaddr addr, |
126 | uint64_t val, unsigned size) |
127 | { |
128 | BMDMAState *bm = opaque; |
129 | PCIDevice *pci_dev = PCI_DEVICE(bm->pci_dev); |
130 | |
131 | if (size != 1) { |
132 | return; |
133 | } |
134 | |
135 | trace_bmdma_write_cmd646(addr, val); |
136 | switch(addr & 3) { |
137 | case 0: |
138 | bmdma_cmd_writeb(bm, val); |
139 | break; |
140 | case 1: |
141 | pci_dev->config[MRDMODE] = |
142 | (pci_dev->config[MRDMODE] & ~0x30) | (val & 0x30); |
143 | cmd646_update_dma_interrupts(pci_dev); |
144 | cmd646_update_irq(pci_dev); |
145 | break; |
146 | case 2: |
147 | bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); |
148 | break; |
149 | case 3: |
150 | if (bm == &bm->pci_dev->bmdma[0]) { |
151 | pci_dev->config[UDIDETCR0] = val; |
152 | } else { |
153 | pci_dev->config[UDIDETCR1] = val; |
154 | } |
155 | break; |
156 | } |
157 | } |
158 | |
159 | static const MemoryRegionOps cmd646_bmdma_ops = { |
160 | .read = bmdma_read, |
161 | .write = bmdma_write, |
162 | }; |
163 | |
164 | static void bmdma_setup_bar(PCIIDEState *d) |
165 | { |
166 | BMDMAState *bm; |
167 | int i; |
168 | |
169 | memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma" , 16); |
170 | for(i = 0;i < 2; i++) { |
171 | bm = &d->bmdma[i]; |
172 | memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm, |
173 | "cmd646-bmdma-bus" , 4); |
174 | memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); |
175 | memory_region_init_io(&bm->addr_ioport, OBJECT(d), |
176 | &bmdma_addr_ioport_ops, bm, |
177 | "cmd646-bmdma-ioport" , 4); |
178 | memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); |
179 | } |
180 | } |
181 | |
182 | static void cmd646_update_irq(PCIDevice *pd) |
183 | { |
184 | int pci_level; |
185 | |
186 | pci_level = ((pd->config[MRDMODE] & MRDMODE_INTR_CH0) && |
187 | !(pd->config[MRDMODE] & MRDMODE_BLK_CH0)) || |
188 | ((pd->config[MRDMODE] & MRDMODE_INTR_CH1) && |
189 | !(pd->config[MRDMODE] & MRDMODE_BLK_CH1)); |
190 | pci_set_irq(pd, pci_level); |
191 | } |
192 | |
193 | /* the PCI irq level is the logical OR of the two channels */ |
194 | static void cmd646_set_irq(void *opaque, int channel, int level) |
195 | { |
196 | PCIIDEState *d = opaque; |
197 | PCIDevice *pd = PCI_DEVICE(d); |
198 | int irq_mask; |
199 | |
200 | irq_mask = MRDMODE_INTR_CH0 << channel; |
201 | if (level) { |
202 | pd->config[MRDMODE] |= irq_mask; |
203 | } else { |
204 | pd->config[MRDMODE] &= ~irq_mask; |
205 | } |
206 | cmd646_update_dma_interrupts(pd); |
207 | cmd646_update_irq(pd); |
208 | } |
209 | |
210 | static void cmd646_reset(void *opaque) |
211 | { |
212 | PCIIDEState *d = opaque; |
213 | unsigned int i; |
214 | |
215 | for (i = 0; i < 2; i++) { |
216 | ide_bus_reset(&d->bus[i]); |
217 | } |
218 | } |
219 | |
220 | static uint32_t cmd646_pci_config_read(PCIDevice *d, |
221 | uint32_t address, int len) |
222 | { |
223 | return pci_default_read_config(d, address, len); |
224 | } |
225 | |
226 | static void cmd646_pci_config_write(PCIDevice *d, uint32_t addr, uint32_t val, |
227 | int l) |
228 | { |
229 | uint32_t i; |
230 | |
231 | pci_default_write_config(d, addr, val, l); |
232 | |
233 | for (i = addr; i < addr + l; i++) { |
234 | switch (i) { |
235 | case CFR: |
236 | case ARTTIM23: |
237 | cmd646_update_udma_interrupts(d); |
238 | break; |
239 | case MRDMODE: |
240 | cmd646_update_dma_interrupts(d); |
241 | break; |
242 | } |
243 | } |
244 | |
245 | cmd646_update_irq(d); |
246 | } |
247 | |
248 | /* CMD646 PCI IDE controller */ |
249 | static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) |
250 | { |
251 | PCIIDEState *d = PCI_IDE(dev); |
252 | uint8_t *pci_conf = dev->config; |
253 | qemu_irq *irq; |
254 | int i; |
255 | |
256 | pci_conf[PCI_CLASS_PROG] = 0x8f; |
257 | |
258 | pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0 |
259 | if (d->secondary) { |
260 | /* XXX: if not enabled, really disable the seconday IDE controller */ |
261 | pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */ |
262 | } |
263 | |
264 | /* Set write-to-clear interrupt bits */ |
265 | dev->wmask[CFR] = 0x0; |
266 | dev->w1cmask[CFR] = CFR_INTR_CH0; |
267 | dev->wmask[ARTTIM23] = 0x0; |
268 | dev->w1cmask[ARTTIM23] = ARTTIM23_INTR_CH1; |
269 | dev->wmask[MRDMODE] = 0x0; |
270 | dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; |
271 | |
272 | memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, |
273 | &d->bus[0], "cmd646-data0" , 8); |
274 | pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); |
275 | |
276 | memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, |
277 | &d->bus[0], "cmd646-cmd0" , 4); |
278 | pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); |
279 | |
280 | memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, |
281 | &d->bus[1], "cmd646-data1" , 8); |
282 | pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); |
283 | |
284 | memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, |
285 | &d->bus[1], "cmd646-cmd1" , 4); |
286 | pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); |
287 | |
288 | bmdma_setup_bar(d); |
289 | pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); |
290 | |
291 | /* TODO: RST# value should be 0 */ |
292 | pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 |
293 | |
294 | irq = qemu_allocate_irqs(cmd646_set_irq, d, 2); |
295 | for (i = 0; i < 2; i++) { |
296 | ide_bus_new(&d->bus[i], sizeof(d->bus[i]), DEVICE(dev), i, 2); |
297 | ide_init2(&d->bus[i], irq[i]); |
298 | |
299 | bmdma_init(&d->bus[i], &d->bmdma[i], d); |
300 | d->bmdma[i].bus = &d->bus[i]; |
301 | ide_register_restart_cb(&d->bus[i]); |
302 | } |
303 | |
304 | vmstate_register(DEVICE(dev), 0, &vmstate_ide_pci, d); |
305 | qemu_register_reset(cmd646_reset, d); |
306 | } |
307 | |
308 | static void pci_cmd646_ide_exitfn(PCIDevice *dev) |
309 | { |
310 | PCIIDEState *d = PCI_IDE(dev); |
311 | unsigned i; |
312 | |
313 | for (i = 0; i < 2; ++i) { |
314 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); |
315 | memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); |
316 | } |
317 | } |
318 | |
319 | void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table, |
320 | int secondary_ide_enabled) |
321 | { |
322 | PCIDevice *dev; |
323 | |
324 | dev = pci_create(bus, -1, "cmd646-ide" ); |
325 | qdev_prop_set_uint32(&dev->qdev, "secondary" , secondary_ide_enabled); |
326 | qdev_init_nofail(&dev->qdev); |
327 | |
328 | pci_ide_create_devs(dev, hd_table); |
329 | } |
330 | |
331 | static Property cmd646_ide_properties[] = { |
332 | DEFINE_PROP_UINT32("secondary" , PCIIDEState, secondary, 0), |
333 | DEFINE_PROP_END_OF_LIST(), |
334 | }; |
335 | |
336 | static void cmd646_ide_class_init(ObjectClass *klass, void *data) |
337 | { |
338 | DeviceClass *dc = DEVICE_CLASS(klass); |
339 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
340 | |
341 | k->realize = pci_cmd646_ide_realize; |
342 | k->exit = pci_cmd646_ide_exitfn; |
343 | k->vendor_id = PCI_VENDOR_ID_CMD; |
344 | k->device_id = PCI_DEVICE_ID_CMD_646; |
345 | k->revision = 0x07; |
346 | k->class_id = PCI_CLASS_STORAGE_IDE; |
347 | k->config_read = cmd646_pci_config_read; |
348 | k->config_write = cmd646_pci_config_write; |
349 | dc->props = cmd646_ide_properties; |
350 | set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); |
351 | } |
352 | |
353 | static const TypeInfo cmd646_ide_info = { |
354 | .name = "cmd646-ide" , |
355 | .parent = TYPE_PCI_IDE, |
356 | .class_init = cmd646_ide_class_init, |
357 | }; |
358 | |
359 | static void cmd646_ide_register_types(void) |
360 | { |
361 | type_register_static(&cmd646_ide_info); |
362 | } |
363 | |
364 | type_init(cmd646_ide_register_types) |
365 | |