1 | /* |
2 | * VT82C686B south bridge support |
3 | * |
4 | * Copyright (c) 2008 yajin (yajin@vm-kernel.org) |
5 | * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) |
6 | * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) |
7 | * This code is licensed under the GNU GPL v2. |
8 | * |
9 | * Contributions after 2012-01-13 are licensed under the terms of the |
10 | * GNU GPL, version 2 or (at your option) any later version. |
11 | */ |
12 | |
13 | #include "qemu/osdep.h" |
14 | #include "hw/isa/vt82c686.h" |
15 | #include "hw/i2c/i2c.h" |
16 | #include "hw/pci/pci.h" |
17 | #include "hw/qdev-properties.h" |
18 | #include "hw/isa/isa.h" |
19 | #include "hw/isa/superio.h" |
20 | #include "hw/sysbus.h" |
21 | #include "migration/vmstate.h" |
22 | #include "hw/mips/mips.h" |
23 | #include "hw/isa/apm.h" |
24 | #include "hw/acpi/acpi.h" |
25 | #include "hw/i2c/pm_smbus.h" |
26 | #include "sysemu/reset.h" |
27 | #include "qemu/module.h" |
28 | #include "qemu/timer.h" |
29 | #include "exec/address-spaces.h" |
30 | |
31 | //#define DEBUG_VT82C686B |
32 | |
33 | #ifdef DEBUG_VT82C686B |
34 | #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) |
35 | #else |
36 | #define DPRINTF(fmt, ...) |
37 | #endif |
38 | |
39 | typedef struct SuperIOConfig |
40 | { |
41 | uint8_t config[0x100]; |
42 | uint8_t index; |
43 | uint8_t data; |
44 | } SuperIOConfig; |
45 | |
46 | typedef struct VT82C686BState { |
47 | PCIDevice dev; |
48 | MemoryRegion superio; |
49 | SuperIOConfig superio_conf; |
50 | } VT82C686BState; |
51 | |
52 | #define TYPE_VT82C686B_DEVICE "VT82C686B" |
53 | #define VT82C686B_DEVICE(obj) \ |
54 | OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE) |
55 | |
56 | static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, |
57 | unsigned size) |
58 | { |
59 | SuperIOConfig *superio_conf = opaque; |
60 | |
61 | DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n" , addr, data); |
62 | if (addr == 0x3f0) { |
63 | superio_conf->index = data & 0xff; |
64 | } else { |
65 | bool can_write = true; |
66 | /* 0x3f1 */ |
67 | switch (superio_conf->index) { |
68 | case 0x00 ... 0xdf: |
69 | case 0xe4: |
70 | case 0xe5: |
71 | case 0xe9 ... 0xed: |
72 | case 0xf3: |
73 | case 0xf5: |
74 | case 0xf7: |
75 | case 0xf9 ... 0xfb: |
76 | case 0xfd ... 0xff: |
77 | can_write = false; |
78 | break; |
79 | case 0xe7: |
80 | if ((data & 0xff) != 0xfe) { |
81 | DPRINTF("change uart 1 base. unsupported yet\n" ); |
82 | can_write = false; |
83 | } |
84 | break; |
85 | case 0xe8: |
86 | if ((data & 0xff) != 0xbe) { |
87 | DPRINTF("change uart 2 base. unsupported yet\n" ); |
88 | can_write = false; |
89 | } |
90 | break; |
91 | default: |
92 | break; |
93 | |
94 | } |
95 | if (can_write) { |
96 | superio_conf->config[superio_conf->index] = data & 0xff; |
97 | } |
98 | } |
99 | } |
100 | |
101 | static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) |
102 | { |
103 | SuperIOConfig *superio_conf = opaque; |
104 | |
105 | DPRINTF("superio_ioport_readb address 0x%x\n" , addr); |
106 | return (superio_conf->config[superio_conf->index]); |
107 | } |
108 | |
109 | static const MemoryRegionOps superio_ops = { |
110 | .read = superio_ioport_readb, |
111 | .write = superio_ioport_writeb, |
112 | .endianness = DEVICE_NATIVE_ENDIAN, |
113 | .impl = { |
114 | .min_access_size = 1, |
115 | .max_access_size = 1, |
116 | }, |
117 | }; |
118 | |
119 | static void vt82c686b_reset(void * opaque) |
120 | { |
121 | PCIDevice *d = opaque; |
122 | uint8_t *pci_conf = d->config; |
123 | VT82C686BState *vt82c = VT82C686B_DEVICE(d); |
124 | |
125 | pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); |
126 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | |
127 | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); |
128 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
129 | |
130 | pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ |
131 | pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ |
132 | pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ |
133 | pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ |
134 | pci_conf[0x59] = 0x04; |
135 | pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ |
136 | pci_conf[0x5f] = 0x04; |
137 | pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ |
138 | |
139 | vt82c->superio_conf.config[0xe0] = 0x3c; |
140 | vt82c->superio_conf.config[0xe2] = 0x03; |
141 | vt82c->superio_conf.config[0xe3] = 0xfc; |
142 | vt82c->superio_conf.config[0xe6] = 0xde; |
143 | vt82c->superio_conf.config[0xe7] = 0xfe; |
144 | vt82c->superio_conf.config[0xe8] = 0xbe; |
145 | } |
146 | |
147 | /* write config pci function0 registers. PCI-ISA bridge */ |
148 | static void vt82c686b_write_config(PCIDevice * d, uint32_t address, |
149 | uint32_t val, int len) |
150 | { |
151 | VT82C686BState *vt686 = VT82C686B_DEVICE(d); |
152 | |
153 | DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n" , |
154 | address, val, len); |
155 | |
156 | pci_default_write_config(d, address, val, len); |
157 | if (address == 0x85) { /* enable or disable super IO configure */ |
158 | memory_region_set_enabled(&vt686->superio, val & 0x2); |
159 | } |
160 | } |
161 | |
162 | #define ACPI_DBG_IO_ADDR 0xb044 |
163 | |
164 | typedef struct VT686PMState { |
165 | PCIDevice dev; |
166 | MemoryRegion io; |
167 | ACPIREGS ar; |
168 | APMState apm; |
169 | PMSMBus smb; |
170 | uint32_t smb_io_base; |
171 | } VT686PMState; |
172 | |
173 | typedef struct VT686AC97State { |
174 | PCIDevice dev; |
175 | } VT686AC97State; |
176 | |
177 | typedef struct VT686MC97State { |
178 | PCIDevice dev; |
179 | } VT686MC97State; |
180 | |
181 | #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" |
182 | #define VT82C686B_PM_DEVICE(obj) \ |
183 | OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE) |
184 | |
185 | #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" |
186 | #define VT82C686B_MC97_DEVICE(obj) \ |
187 | OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE) |
188 | |
189 | #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" |
190 | #define VT82C686B_AC97_DEVICE(obj) \ |
191 | OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE) |
192 | |
193 | static void pm_update_sci(VT686PMState *s) |
194 | { |
195 | int sci_level, pmsts; |
196 | |
197 | pmsts = acpi_pm1_evt_get_sts(&s->ar); |
198 | sci_level = (((pmsts & s->ar.pm1.evt.en) & |
199 | (ACPI_BITMASK_RT_CLOCK_ENABLE | |
200 | ACPI_BITMASK_POWER_BUTTON_ENABLE | |
201 | ACPI_BITMASK_GLOBAL_LOCK_ENABLE | |
202 | ACPI_BITMASK_TIMER_ENABLE)) != 0); |
203 | pci_set_irq(&s->dev, sci_level); |
204 | /* schedule a timer interruption if needed */ |
205 | acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && |
206 | !(pmsts & ACPI_BITMASK_TIMER_STATUS)); |
207 | } |
208 | |
209 | static void pm_tmr_timer(ACPIREGS *ar) |
210 | { |
211 | VT686PMState *s = container_of(ar, VT686PMState, ar); |
212 | pm_update_sci(s); |
213 | } |
214 | |
215 | static void pm_io_space_update(VT686PMState *s) |
216 | { |
217 | uint32_t pm_io_base; |
218 | |
219 | pm_io_base = pci_get_long(s->dev.config + 0x40); |
220 | pm_io_base &= 0xffc0; |
221 | |
222 | memory_region_transaction_begin(); |
223 | memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); |
224 | memory_region_set_address(&s->io, pm_io_base); |
225 | memory_region_transaction_commit(); |
226 | } |
227 | |
228 | static void pm_write_config(PCIDevice *d, |
229 | uint32_t address, uint32_t val, int len) |
230 | { |
231 | DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n" , |
232 | address, val, len); |
233 | pci_default_write_config(d, address, val, len); |
234 | } |
235 | |
236 | static int vmstate_acpi_post_load(void *opaque, int version_id) |
237 | { |
238 | VT686PMState *s = opaque; |
239 | |
240 | pm_io_space_update(s); |
241 | return 0; |
242 | } |
243 | |
244 | static const VMStateDescription vmstate_acpi = { |
245 | .name = "vt82c686b_pm" , |
246 | .version_id = 1, |
247 | .minimum_version_id = 1, |
248 | .post_load = vmstate_acpi_post_load, |
249 | .fields = (VMStateField[]) { |
250 | VMSTATE_PCI_DEVICE(dev, VT686PMState), |
251 | VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), |
252 | VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), |
253 | VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), |
254 | VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), |
255 | VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), |
256 | VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), |
257 | VMSTATE_END_OF_LIST() |
258 | } |
259 | }; |
260 | |
261 | /* |
262 | * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() |
263 | * just register a PCI device now, functionalities will be implemented later. |
264 | */ |
265 | |
266 | static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) |
267 | { |
268 | VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); |
269 | uint8_t *pci_conf = s->dev.config; |
270 | |
271 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
272 | PCI_COMMAND_PARITY); |
273 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | |
274 | PCI_STATUS_DEVSEL_MEDIUM); |
275 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); |
276 | } |
277 | |
278 | void vt82c686b_ac97_init(PCIBus *bus, int devfn) |
279 | { |
280 | PCIDevice *dev; |
281 | |
282 | dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE); |
283 | qdev_init_nofail(&dev->qdev); |
284 | } |
285 | |
286 | static void via_ac97_class_init(ObjectClass *klass, void *data) |
287 | { |
288 | DeviceClass *dc = DEVICE_CLASS(klass); |
289 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
290 | |
291 | k->realize = vt82c686b_ac97_realize; |
292 | k->vendor_id = PCI_VENDOR_ID_VIA; |
293 | k->device_id = PCI_DEVICE_ID_VIA_AC97; |
294 | k->revision = 0x50; |
295 | k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; |
296 | set_bit(DEVICE_CATEGORY_SOUND, dc->categories); |
297 | dc->desc = "AC97" ; |
298 | } |
299 | |
300 | static const TypeInfo via_ac97_info = { |
301 | .name = TYPE_VT82C686B_AC97_DEVICE, |
302 | .parent = TYPE_PCI_DEVICE, |
303 | .instance_size = sizeof(VT686AC97State), |
304 | .class_init = via_ac97_class_init, |
305 | .interfaces = (InterfaceInfo[]) { |
306 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
307 | { }, |
308 | }, |
309 | }; |
310 | |
311 | static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) |
312 | { |
313 | VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); |
314 | uint8_t *pci_conf = s->dev.config; |
315 | |
316 | pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | |
317 | PCI_COMMAND_VGA_PALETTE); |
318 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); |
319 | pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); |
320 | } |
321 | |
322 | void vt82c686b_mc97_init(PCIBus *bus, int devfn) |
323 | { |
324 | PCIDevice *dev; |
325 | |
326 | dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE); |
327 | qdev_init_nofail(&dev->qdev); |
328 | } |
329 | |
330 | static void via_mc97_class_init(ObjectClass *klass, void *data) |
331 | { |
332 | DeviceClass *dc = DEVICE_CLASS(klass); |
333 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
334 | |
335 | k->realize = vt82c686b_mc97_realize; |
336 | k->vendor_id = PCI_VENDOR_ID_VIA; |
337 | k->device_id = PCI_DEVICE_ID_VIA_MC97; |
338 | k->class_id = PCI_CLASS_COMMUNICATION_OTHER; |
339 | k->revision = 0x30; |
340 | set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); |
341 | dc->desc = "MC97" ; |
342 | } |
343 | |
344 | static const TypeInfo via_mc97_info = { |
345 | .name = TYPE_VT82C686B_MC97_DEVICE, |
346 | .parent = TYPE_PCI_DEVICE, |
347 | .instance_size = sizeof(VT686MC97State), |
348 | .class_init = via_mc97_class_init, |
349 | .interfaces = (InterfaceInfo[]) { |
350 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
351 | { }, |
352 | }, |
353 | }; |
354 | |
355 | /* vt82c686 pm init */ |
356 | static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) |
357 | { |
358 | VT686PMState *s = VT82C686B_PM_DEVICE(dev); |
359 | uint8_t *pci_conf; |
360 | |
361 | pci_conf = s->dev.config; |
362 | pci_set_word(pci_conf + PCI_COMMAND, 0); |
363 | pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | |
364 | PCI_STATUS_DEVSEL_MEDIUM); |
365 | |
366 | /* 0x48-0x4B is Power Management I/O Base */ |
367 | pci_set_long(pci_conf + 0x48, 0x00000001); |
368 | |
369 | /* SMB ports:0xeee0~0xeeef */ |
370 | s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); |
371 | pci_conf[0x90] = s->smb_io_base | 1; |
372 | pci_conf[0x91] = s->smb_io_base >> 8; |
373 | pci_conf[0xd2] = 0x90; |
374 | pm_smbus_init(DEVICE(s), &s->smb, false); |
375 | memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); |
376 | |
377 | apm_init(dev, &s->apm, NULL, s); |
378 | |
379 | memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm" , 64); |
380 | memory_region_set_enabled(&s->io, false); |
381 | memory_region_add_subregion(get_system_io(), 0, &s->io); |
382 | |
383 | acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); |
384 | acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); |
385 | acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); |
386 | } |
387 | |
388 | I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, |
389 | qemu_irq sci_irq) |
390 | { |
391 | PCIDevice *dev; |
392 | VT686PMState *s; |
393 | |
394 | dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE); |
395 | qdev_prop_set_uint32(&dev->qdev, "smb_io_base" , smb_io_base); |
396 | |
397 | s = VT82C686B_PM_DEVICE(dev); |
398 | |
399 | qdev_init_nofail(&dev->qdev); |
400 | |
401 | return s->smb.smbus; |
402 | } |
403 | |
404 | static Property via_pm_properties[] = { |
405 | DEFINE_PROP_UINT32("smb_io_base" , VT686PMState, smb_io_base, 0), |
406 | DEFINE_PROP_END_OF_LIST(), |
407 | }; |
408 | |
409 | static void via_pm_class_init(ObjectClass *klass, void *data) |
410 | { |
411 | DeviceClass *dc = DEVICE_CLASS(klass); |
412 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
413 | |
414 | k->realize = vt82c686b_pm_realize; |
415 | k->config_write = pm_write_config; |
416 | k->vendor_id = PCI_VENDOR_ID_VIA; |
417 | k->device_id = PCI_DEVICE_ID_VIA_ACPI; |
418 | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
419 | k->revision = 0x40; |
420 | dc->desc = "PM" ; |
421 | dc->vmsd = &vmstate_acpi; |
422 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
423 | dc->props = via_pm_properties; |
424 | } |
425 | |
426 | static const TypeInfo via_pm_info = { |
427 | .name = TYPE_VT82C686B_PM_DEVICE, |
428 | .parent = TYPE_PCI_DEVICE, |
429 | .instance_size = sizeof(VT686PMState), |
430 | .class_init = via_pm_class_init, |
431 | .interfaces = (InterfaceInfo[]) { |
432 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
433 | { }, |
434 | }, |
435 | }; |
436 | |
437 | static const VMStateDescription vmstate_via = { |
438 | .name = "vt82c686b" , |
439 | .version_id = 1, |
440 | .minimum_version_id = 1, |
441 | .fields = (VMStateField[]) { |
442 | VMSTATE_PCI_DEVICE(dev, VT82C686BState), |
443 | VMSTATE_END_OF_LIST() |
444 | } |
445 | }; |
446 | |
447 | /* init the PCI-to-ISA bridge */ |
448 | static void vt82c686b_realize(PCIDevice *d, Error **errp) |
449 | { |
450 | VT82C686BState *vt82c = VT82C686B_DEVICE(d); |
451 | uint8_t *pci_conf; |
452 | ISABus *isa_bus; |
453 | uint8_t *wmask; |
454 | int i; |
455 | |
456 | isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), |
457 | pci_address_space_io(d), errp); |
458 | if (!isa_bus) { |
459 | return; |
460 | } |
461 | |
462 | pci_conf = d->config; |
463 | pci_config_set_prog_interface(pci_conf, 0x0); |
464 | |
465 | wmask = d->wmask; |
466 | for (i = 0x00; i < 0xff; i++) { |
467 | if (i<=0x03 || (i>=0x08 && i<=0x3f)) { |
468 | wmask[i] = 0x00; |
469 | } |
470 | } |
471 | |
472 | memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, |
473 | &vt82c->superio_conf, "superio" , 2); |
474 | memory_region_set_enabled(&vt82c->superio, false); |
475 | /* The floppy also uses 0x3f0 and 0x3f1. |
476 | * But we do not emulate a floppy, so just set it here. */ |
477 | memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, |
478 | &vt82c->superio); |
479 | |
480 | qemu_register_reset(vt82c686b_reset, d); |
481 | } |
482 | |
483 | ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) |
484 | { |
485 | PCIDevice *d; |
486 | |
487 | d = pci_create_simple_multifunction(bus, devfn, true, |
488 | TYPE_VT82C686B_DEVICE); |
489 | |
490 | return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0" )); |
491 | } |
492 | |
493 | static void via_class_init(ObjectClass *klass, void *data) |
494 | { |
495 | DeviceClass *dc = DEVICE_CLASS(klass); |
496 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
497 | |
498 | k->realize = vt82c686b_realize; |
499 | k->config_write = vt82c686b_write_config; |
500 | k->vendor_id = PCI_VENDOR_ID_VIA; |
501 | k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; |
502 | k->class_id = PCI_CLASS_BRIDGE_ISA; |
503 | k->revision = 0x40; |
504 | dc->desc = "ISA bridge" ; |
505 | dc->vmsd = &vmstate_via; |
506 | /* |
507 | * Reason: part of VIA VT82C686 southbridge, needs to be wired up, |
508 | * e.g. by mips_fulong2e_init() |
509 | */ |
510 | dc->user_creatable = false; |
511 | } |
512 | |
513 | static const TypeInfo via_info = { |
514 | .name = TYPE_VT82C686B_DEVICE, |
515 | .parent = TYPE_PCI_DEVICE, |
516 | .instance_size = sizeof(VT82C686BState), |
517 | .class_init = via_class_init, |
518 | .interfaces = (InterfaceInfo[]) { |
519 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
520 | { }, |
521 | }, |
522 | }; |
523 | |
524 | static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) |
525 | { |
526 | ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); |
527 | |
528 | sc->serial.count = 2; |
529 | sc->parallel.count = 1; |
530 | sc->ide.count = 0; |
531 | sc->floppy.count = 1; |
532 | } |
533 | |
534 | static const TypeInfo via_superio_info = { |
535 | .name = TYPE_VT82C686B_SUPERIO, |
536 | .parent = TYPE_ISA_SUPERIO, |
537 | .instance_size = sizeof(ISASuperIODevice), |
538 | .class_size = sizeof(ISASuperIOClass), |
539 | .class_init = vt82c686b_superio_class_init, |
540 | }; |
541 | |
542 | static void vt82c686b_register_types(void) |
543 | { |
544 | type_register_static(&via_ac97_info); |
545 | type_register_static(&via_mc97_info); |
546 | type_register_static(&via_pm_info); |
547 | type_register_static(&via_superio_info); |
548 | type_register_static(&via_info); |
549 | } |
550 | |
551 | type_init(vt82c686b_register_types) |
552 | |