1 | /* |
2 | * Coherent Processing System emulation. |
3 | * |
4 | * Copyright (c) 2016 Imagination Technologies |
5 | * |
6 | * This library is free software; you can redistribute it and/or |
7 | * modify it under the terms of the GNU Lesser General Public |
8 | * License as published by the Free Software Foundation; either |
9 | * version 2 of the License, or (at your option) any later version. |
10 | * |
11 | * This library is distributed in the hope that it will be useful, |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
14 | * Lesser General Public License for more details. |
15 | * |
16 | * You should have received a copy of the GNU Lesser General Public |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
18 | */ |
19 | |
20 | #include "qemu/osdep.h" |
21 | #include "qapi/error.h" |
22 | #include "qemu/module.h" |
23 | #include "hw/mips/cps.h" |
24 | #include "hw/mips/mips.h" |
25 | #include "hw/qdev-properties.h" |
26 | #include "hw/mips/cpudevs.h" |
27 | #include "sysemu/kvm.h" |
28 | #include "sysemu/reset.h" |
29 | |
30 | qemu_irq get_cps_irq(MIPSCPSState *s, int pin_number) |
31 | { |
32 | assert(pin_number < s->num_irq); |
33 | return s->gic.irq_state[pin_number].irq; |
34 | } |
35 | |
36 | static void mips_cps_init(Object *obj) |
37 | { |
38 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
39 | MIPSCPSState *s = MIPS_CPS(obj); |
40 | |
41 | /* |
42 | * Cover entire address space as there do not seem to be any |
43 | * constraints for the base address of CPC and GIC. |
44 | */ |
45 | memory_region_init(&s->container, obj, "mips-cps-container" , UINT64_MAX); |
46 | sysbus_init_mmio(sbd, &s->container); |
47 | } |
48 | |
49 | static void main_cpu_reset(void *opaque) |
50 | { |
51 | MIPSCPU *cpu = opaque; |
52 | CPUState *cs = CPU(cpu); |
53 | |
54 | cpu_reset(cs); |
55 | |
56 | /* All VPs are halted on reset. Leave powering up to CPC. */ |
57 | cs->halted = 1; |
58 | } |
59 | |
60 | static bool cpu_mips_itu_supported(CPUMIPSState *env) |
61 | { |
62 | bool is_mt = (env->CP0_Config5 & (1 << CP0C5_VP)) || |
63 | (env->CP0_Config3 & (1 << CP0C3_MT)); |
64 | |
65 | return is_mt && !kvm_enabled(); |
66 | } |
67 | |
68 | static void mips_cps_realize(DeviceState *dev, Error **errp) |
69 | { |
70 | MIPSCPSState *s = MIPS_CPS(dev); |
71 | CPUMIPSState *env; |
72 | MIPSCPU *cpu; |
73 | int i; |
74 | Error *err = NULL; |
75 | target_ulong gcr_base; |
76 | bool itu_present = false; |
77 | bool saar_present = false; |
78 | |
79 | for (i = 0; i < s->num_vp; i++) { |
80 | cpu = MIPS_CPU(cpu_create(s->cpu_type)); |
81 | |
82 | /* Init internal devices */ |
83 | cpu_mips_irq_init_cpu(cpu); |
84 | cpu_mips_clock_init(cpu); |
85 | |
86 | env = &cpu->env; |
87 | if (cpu_mips_itu_supported(env)) { |
88 | itu_present = true; |
89 | /* Attach ITC Tag to the VP */ |
90 | env->itc_tag = mips_itu_get_tag_region(&s->itu); |
91 | env->itu = &s->itu; |
92 | } |
93 | qemu_register_reset(main_cpu_reset, cpu); |
94 | } |
95 | |
96 | cpu = MIPS_CPU(first_cpu); |
97 | env = &cpu->env; |
98 | saar_present = (bool)env->saarp; |
99 | |
100 | /* Inter-Thread Communication Unit */ |
101 | if (itu_present) { |
102 | sysbus_init_child_obj(OBJECT(dev), "itu" , &s->itu, sizeof(s->itu), |
103 | TYPE_MIPS_ITU); |
104 | object_property_set_int(OBJECT(&s->itu), 16, "num-fifo" , &err); |
105 | object_property_set_int(OBJECT(&s->itu), 16, "num-semaphores" , &err); |
106 | object_property_set_bool(OBJECT(&s->itu), saar_present, "saar-present" , |
107 | &err); |
108 | if (saar_present) { |
109 | qdev_prop_set_ptr(DEVICE(&s->itu), "saar" , (void *)&env->CP0_SAAR); |
110 | } |
111 | object_property_set_bool(OBJECT(&s->itu), true, "realized" , &err); |
112 | if (err != NULL) { |
113 | error_propagate(errp, err); |
114 | return; |
115 | } |
116 | |
117 | memory_region_add_subregion(&s->container, 0, |
118 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->itu), 0)); |
119 | } |
120 | |
121 | /* Cluster Power Controller */ |
122 | sysbus_init_child_obj(OBJECT(dev), "cpc" , &s->cpc, sizeof(s->cpc), |
123 | TYPE_MIPS_CPC); |
124 | object_property_set_int(OBJECT(&s->cpc), s->num_vp, "num-vp" , &err); |
125 | object_property_set_int(OBJECT(&s->cpc), 1, "vp-start-running" , &err); |
126 | object_property_set_bool(OBJECT(&s->cpc), true, "realized" , &err); |
127 | if (err != NULL) { |
128 | error_propagate(errp, err); |
129 | return; |
130 | } |
131 | |
132 | memory_region_add_subregion(&s->container, 0, |
133 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->cpc), 0)); |
134 | |
135 | /* Global Interrupt Controller */ |
136 | sysbus_init_child_obj(OBJECT(dev), "gic" , &s->gic, sizeof(s->gic), |
137 | TYPE_MIPS_GIC); |
138 | object_property_set_int(OBJECT(&s->gic), s->num_vp, "num-vp" , &err); |
139 | object_property_set_int(OBJECT(&s->gic), 128, "num-irq" , &err); |
140 | object_property_set_bool(OBJECT(&s->gic), true, "realized" , &err); |
141 | if (err != NULL) { |
142 | error_propagate(errp, err); |
143 | return; |
144 | } |
145 | |
146 | memory_region_add_subregion(&s->container, 0, |
147 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gic), 0)); |
148 | |
149 | /* Global Configuration Registers */ |
150 | gcr_base = env->CP0_CMGCRBase << 4; |
151 | |
152 | sysbus_init_child_obj(OBJECT(dev), "gcr" , &s->gcr, sizeof(s->gcr), |
153 | TYPE_MIPS_GCR); |
154 | object_property_set_int(OBJECT(&s->gcr), s->num_vp, "num-vp" , &err); |
155 | object_property_set_int(OBJECT(&s->gcr), 0x800, "gcr-rev" , &err); |
156 | object_property_set_int(OBJECT(&s->gcr), gcr_base, "gcr-base" , &err); |
157 | object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->gic.mr), "gic" , &err); |
158 | object_property_set_link(OBJECT(&s->gcr), OBJECT(&s->cpc.mr), "cpc" , &err); |
159 | object_property_set_bool(OBJECT(&s->gcr), true, "realized" , &err); |
160 | if (err != NULL) { |
161 | error_propagate(errp, err); |
162 | return; |
163 | } |
164 | |
165 | memory_region_add_subregion(&s->container, gcr_base, |
166 | sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->gcr), 0)); |
167 | } |
168 | |
169 | static Property mips_cps_properties[] = { |
170 | DEFINE_PROP_UINT32("num-vp" , MIPSCPSState, num_vp, 1), |
171 | DEFINE_PROP_UINT32("num-irq" , MIPSCPSState, num_irq, 256), |
172 | DEFINE_PROP_STRING("cpu-type" , MIPSCPSState, cpu_type), |
173 | DEFINE_PROP_END_OF_LIST() |
174 | }; |
175 | |
176 | static void mips_cps_class_init(ObjectClass *klass, void *data) |
177 | { |
178 | DeviceClass *dc = DEVICE_CLASS(klass); |
179 | |
180 | dc->realize = mips_cps_realize; |
181 | dc->props = mips_cps_properties; |
182 | } |
183 | |
184 | static const TypeInfo mips_cps_info = { |
185 | .name = TYPE_MIPS_CPS, |
186 | .parent = TYPE_SYS_BUS_DEVICE, |
187 | .instance_size = sizeof(MIPSCPSState), |
188 | .instance_init = mips_cps_init, |
189 | .class_init = mips_cps_class_init, |
190 | }; |
191 | |
192 | static void mips_cps_register_types(void) |
193 | { |
194 | type_register_static(&mips_cps_info); |
195 | } |
196 | |
197 | type_init(mips_cps_register_types) |
198 | |