1/*
2 * ASPEED SDRAM Memory Controller
3 *
4 * Copyright (C) 2016 IBM Corp.
5 *
6 * This code is licensed under the GPL version 2 or later. See
7 * the COPYING file in the top-level directory.
8 */
9
10#include "qemu/osdep.h"
11#include "qemu/log.h"
12#include "qemu/module.h"
13#include "qemu/error-report.h"
14#include "hw/misc/aspeed_sdmc.h"
15#include "hw/misc/aspeed_scu.h"
16#include "hw/qdev-properties.h"
17#include "migration/vmstate.h"
18#include "qapi/error.h"
19#include "trace.h"
20
21/* Protection Key Register */
22#define R_PROT (0x00 / 4)
23#define PROT_KEY_UNLOCK 0xFC600309
24
25/* Configuration Register */
26#define R_CONF (0x04 / 4)
27
28/* Control/Status Register #1 (ast2500) */
29#define R_STATUS1 (0x60 / 4)
30#define PHY_BUSY_STATE BIT(0)
31
32#define R_ECC_TEST_CTRL (0x70 / 4)
33#define ECC_TEST_FINISHED BIT(12)
34#define ECC_TEST_FAIL BIT(13)
35
36/*
37 * Configuration register Ox4 (for Aspeed AST2400 SOC)
38 *
39 * These are for the record and future use. ASPEED_SDMC_DRAM_SIZE is
40 * what we care about right now as it is checked by U-Boot to
41 * determine the RAM size.
42 */
43
44#define ASPEED_SDMC_RESERVED 0xFFFFF800 /* 31:11 reserved */
45#define ASPEED_SDMC_AST2300_COMPAT (1 << 10)
46#define ASPEED_SDMC_SCRAMBLE_PATTERN (1 << 9)
47#define ASPEED_SDMC_DATA_SCRAMBLE (1 << 8)
48#define ASPEED_SDMC_ECC_ENABLE (1 << 7)
49#define ASPEED_SDMC_VGA_COMPAT (1 << 6) /* readonly */
50#define ASPEED_SDMC_DRAM_BANK (1 << 5)
51#define ASPEED_SDMC_DRAM_BURST (1 << 4)
52#define ASPEED_SDMC_VGA_APERTURE(x) ((x & 0x3) << 2) /* readonly */
53#define ASPEED_SDMC_VGA_8MB 0x0
54#define ASPEED_SDMC_VGA_16MB 0x1
55#define ASPEED_SDMC_VGA_32MB 0x2
56#define ASPEED_SDMC_VGA_64MB 0x3
57#define ASPEED_SDMC_DRAM_SIZE(x) (x & 0x3)
58#define ASPEED_SDMC_DRAM_64MB 0x0
59#define ASPEED_SDMC_DRAM_128MB 0x1
60#define ASPEED_SDMC_DRAM_256MB 0x2
61#define ASPEED_SDMC_DRAM_512MB 0x3
62
63#define ASPEED_SDMC_READONLY_MASK \
64 (ASPEED_SDMC_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
65 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
66/*
67 * Configuration register Ox4 (for Aspeed AST2500 SOC and higher)
68 *
69 * Incompatibilities are annotated in the list. ASPEED_SDMC_HW_VERSION
70 * should be set to 1 for the AST2500 SOC.
71 */
72#define ASPEED_SDMC_HW_VERSION(x) ((x & 0xf) << 28) /* readonly */
73#define ASPEED_SDMC_SW_VERSION ((x & 0xff) << 20)
74#define ASPEED_SDMC_CACHE_INITIAL_DONE (1 << 19) /* readonly */
75#define ASPEED_SDMC_AST2500_RESERVED 0x7C000 /* 18:14 reserved */
76#define ASPEED_SDMC_CACHE_DDR4_CONF (1 << 13)
77#define ASPEED_SDMC_CACHE_INITIAL (1 << 12)
78#define ASPEED_SDMC_CACHE_RANGE_CTRL (1 << 11)
79#define ASPEED_SDMC_CACHE_ENABLE (1 << 10) /* differs from AST2400 */
80#define ASPEED_SDMC_DRAM_TYPE (1 << 4) /* differs from AST2400 */
81
82/* DRAM size definitions differs */
83#define ASPEED_SDMC_AST2500_128MB 0x0
84#define ASPEED_SDMC_AST2500_256MB 0x1
85#define ASPEED_SDMC_AST2500_512MB 0x2
86#define ASPEED_SDMC_AST2500_1024MB 0x3
87
88#define ASPEED_SDMC_AST2500_READONLY_MASK \
89 (ASPEED_SDMC_HW_VERSION(0xf) | ASPEED_SDMC_CACHE_INITIAL_DONE | \
90 ASPEED_SDMC_AST2500_RESERVED | ASPEED_SDMC_VGA_COMPAT | \
91 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB))
92
93static uint64_t aspeed_sdmc_read(void *opaque, hwaddr addr, unsigned size)
94{
95 AspeedSDMCState *s = ASPEED_SDMC(opaque);
96
97 addr >>= 2;
98
99 if (addr >= ARRAY_SIZE(s->regs)) {
100 qemu_log_mask(LOG_GUEST_ERROR,
101 "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
102 __func__, addr);
103 return 0;
104 }
105
106 return s->regs[addr];
107}
108
109static void aspeed_sdmc_write(void *opaque, hwaddr addr, uint64_t data,
110 unsigned int size)
111{
112 AspeedSDMCState *s = ASPEED_SDMC(opaque);
113
114 addr >>= 2;
115
116 if (addr >= ARRAY_SIZE(s->regs)) {
117 qemu_log_mask(LOG_GUEST_ERROR,
118 "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
119 __func__, addr);
120 return;
121 }
122
123 if (addr == R_PROT) {
124 s->regs[addr] = (data == PROT_KEY_UNLOCK) ? 1 : 0;
125 return;
126 }
127
128 if (!s->regs[R_PROT]) {
129 qemu_log_mask(LOG_GUEST_ERROR, "%s: SDMC is locked!\n", __func__);
130 return;
131 }
132
133 if (addr == R_CONF) {
134 /* Make sure readonly bits are kept */
135 switch (s->silicon_rev) {
136 case AST2400_A0_SILICON_REV:
137 case AST2400_A1_SILICON_REV:
138 data &= ~ASPEED_SDMC_READONLY_MASK;
139 data |= s->fixed_conf;
140 break;
141 case AST2500_A0_SILICON_REV:
142 case AST2500_A1_SILICON_REV:
143 data &= ~ASPEED_SDMC_AST2500_READONLY_MASK;
144 data |= s->fixed_conf;
145 break;
146 default:
147 g_assert_not_reached();
148 }
149 }
150 if (s->silicon_rev == AST2500_A0_SILICON_REV ||
151 s->silicon_rev == AST2500_A1_SILICON_REV) {
152 switch (addr) {
153 case R_STATUS1:
154 /* Will never return 'busy' */
155 data &= ~PHY_BUSY_STATE;
156 break;
157 case R_ECC_TEST_CTRL:
158 /* Always done, always happy */
159 data |= ECC_TEST_FINISHED;
160 data &= ~ECC_TEST_FAIL;
161 break;
162 default:
163 break;
164 }
165 }
166
167 s->regs[addr] = data;
168}
169
170static const MemoryRegionOps aspeed_sdmc_ops = {
171 .read = aspeed_sdmc_read,
172 .write = aspeed_sdmc_write,
173 .endianness = DEVICE_LITTLE_ENDIAN,
174 .valid.min_access_size = 4,
175 .valid.max_access_size = 4,
176};
177
178static int ast2400_rambits(AspeedSDMCState *s)
179{
180 switch (s->ram_size >> 20) {
181 case 64:
182 return ASPEED_SDMC_DRAM_64MB;
183 case 128:
184 return ASPEED_SDMC_DRAM_128MB;
185 case 256:
186 return ASPEED_SDMC_DRAM_256MB;
187 case 512:
188 return ASPEED_SDMC_DRAM_512MB;
189 default:
190 break;
191 }
192
193 /* use a common default */
194 warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 256M",
195 s->ram_size);
196 s->ram_size = 256 << 20;
197 return ASPEED_SDMC_DRAM_256MB;
198}
199
200static int ast2500_rambits(AspeedSDMCState *s)
201{
202 switch (s->ram_size >> 20) {
203 case 128:
204 return ASPEED_SDMC_AST2500_128MB;
205 case 256:
206 return ASPEED_SDMC_AST2500_256MB;
207 case 512:
208 return ASPEED_SDMC_AST2500_512MB;
209 case 1024:
210 return ASPEED_SDMC_AST2500_1024MB;
211 default:
212 break;
213 }
214
215 /* use a common default */
216 warn_report("Invalid RAM size 0x%" PRIx64 ". Using default 512M",
217 s->ram_size);
218 s->ram_size = 512 << 20;
219 return ASPEED_SDMC_AST2500_512MB;
220}
221
222static void aspeed_sdmc_reset(DeviceState *dev)
223{
224 AspeedSDMCState *s = ASPEED_SDMC(dev);
225
226 memset(s->regs, 0, sizeof(s->regs));
227
228 /* Set ram size bit and defaults values */
229 s->regs[R_CONF] = s->fixed_conf;
230}
231
232static void aspeed_sdmc_realize(DeviceState *dev, Error **errp)
233{
234 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
235 AspeedSDMCState *s = ASPEED_SDMC(dev);
236
237 if (!is_supported_silicon_rev(s->silicon_rev)) {
238 error_setg(errp, "Unknown silicon revision: 0x%" PRIx32,
239 s->silicon_rev);
240 return;
241 }
242
243 switch (s->silicon_rev) {
244 case AST2400_A0_SILICON_REV:
245 case AST2400_A1_SILICON_REV:
246 s->ram_bits = ast2400_rambits(s);
247 s->max_ram_size = 512 << 20;
248 s->fixed_conf = ASPEED_SDMC_VGA_COMPAT |
249 ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
250 break;
251 case AST2500_A0_SILICON_REV:
252 case AST2500_A1_SILICON_REV:
253 s->ram_bits = ast2500_rambits(s);
254 s->max_ram_size = 1024 << 20;
255 s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) |
256 ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) |
257 ASPEED_SDMC_CACHE_INITIAL_DONE |
258 ASPEED_SDMC_DRAM_SIZE(s->ram_bits);
259 break;
260 default:
261 g_assert_not_reached();
262 }
263
264 memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_sdmc_ops, s,
265 TYPE_ASPEED_SDMC, 0x1000);
266 sysbus_init_mmio(sbd, &s->iomem);
267}
268
269static const VMStateDescription vmstate_aspeed_sdmc = {
270 .name = "aspeed.sdmc",
271 .version_id = 1,
272 .minimum_version_id = 1,
273 .fields = (VMStateField[]) {
274 VMSTATE_UINT32_ARRAY(regs, AspeedSDMCState, ASPEED_SDMC_NR_REGS),
275 VMSTATE_END_OF_LIST()
276 }
277};
278
279static Property aspeed_sdmc_properties[] = {
280 DEFINE_PROP_UINT32("silicon-rev", AspeedSDMCState, silicon_rev, 0),
281 DEFINE_PROP_UINT64("ram-size", AspeedSDMCState, ram_size, 0),
282 DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0),
283 DEFINE_PROP_END_OF_LIST(),
284};
285
286static void aspeed_sdmc_class_init(ObjectClass *klass, void *data)
287{
288 DeviceClass *dc = DEVICE_CLASS(klass);
289 dc->realize = aspeed_sdmc_realize;
290 dc->reset = aspeed_sdmc_reset;
291 dc->desc = "ASPEED SDRAM Memory Controller";
292 dc->vmsd = &vmstate_aspeed_sdmc;
293 dc->props = aspeed_sdmc_properties;
294}
295
296static const TypeInfo aspeed_sdmc_info = {
297 .name = TYPE_ASPEED_SDMC,
298 .parent = TYPE_SYS_BUS_DEVICE,
299 .instance_size = sizeof(AspeedSDMCState),
300 .class_init = aspeed_sdmc_class_init,
301};
302
303static void aspeed_sdmc_register_types(void)
304{
305 type_register_static(&aspeed_sdmc_info);
306}
307
308type_init(aspeed_sdmc_register_types);
309