1 | /* |
2 | * QEMU PREP PCI host |
3 | * |
4 | * Copyright (c) 2006 Fabrice Bellard |
5 | * Copyright (c) 2011-2013 Andreas Färber |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal |
9 | * in the Software without restriction, including without limitation the rights |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
11 | * copies of the Software, and to permit persons to whom the Software is |
12 | * furnished to do so, subject to the following conditions: |
13 | * |
14 | * The above copyright notice and this permission notice shall be included in |
15 | * all copies or substantial portions of the Software. |
16 | * |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
23 | * THE SOFTWARE. |
24 | */ |
25 | |
26 | #include "qemu/osdep.h" |
27 | #include "qemu-common.h" |
28 | #include "qemu/units.h" |
29 | #include "qapi/error.h" |
30 | #include "hw/pci/pci.h" |
31 | #include "hw/pci/pci_bus.h" |
32 | #include "hw/pci/pci_host.h" |
33 | #include "hw/qdev-properties.h" |
34 | #include "migration/vmstate.h" |
35 | #include "hw/i386/pc.h" |
36 | #include "hw/irq.h" |
37 | #include "hw/loader.h" |
38 | #include "hw/or-irq.h" |
39 | #include "exec/address-spaces.h" |
40 | #include "elf.h" |
41 | |
42 | #define TYPE_RAVEN_PCI_DEVICE "raven" |
43 | #define TYPE_RAVEN_PCI_HOST_BRIDGE "raven-pcihost" |
44 | |
45 | #define RAVEN_PCI_DEVICE(obj) \ |
46 | OBJECT_CHECK(RavenPCIState, (obj), TYPE_RAVEN_PCI_DEVICE) |
47 | |
48 | typedef struct RavenPCIState { |
49 | PCIDevice dev; |
50 | |
51 | uint32_t elf_machine; |
52 | char *bios_name; |
53 | MemoryRegion bios; |
54 | } RavenPCIState; |
55 | |
56 | #define RAVEN_PCI_HOST_BRIDGE(obj) \ |
57 | OBJECT_CHECK(PREPPCIState, (obj), TYPE_RAVEN_PCI_HOST_BRIDGE) |
58 | |
59 | typedef struct PRePPCIState { |
60 | PCIHostState parent_obj; |
61 | |
62 | qemu_or_irq *or_irq; |
63 | qemu_irq pci_irqs[PCI_NUM_PINS]; |
64 | PCIBus pci_bus; |
65 | AddressSpace pci_io_as; |
66 | MemoryRegion pci_io; |
67 | MemoryRegion pci_io_non_contiguous; |
68 | MemoryRegion pci_memory; |
69 | MemoryRegion pci_intack; |
70 | MemoryRegion bm; |
71 | MemoryRegion bm_ram_alias; |
72 | MemoryRegion bm_pci_memory_alias; |
73 | AddressSpace bm_as; |
74 | RavenPCIState pci_dev; |
75 | |
76 | int contiguous_map; |
77 | bool is_legacy_prep; |
78 | } PREPPCIState; |
79 | |
80 | #define BIOS_SIZE (1 * MiB) |
81 | |
82 | static inline uint32_t raven_pci_io_config(hwaddr addr) |
83 | { |
84 | int i; |
85 | |
86 | for (i = 0; i < 11; i++) { |
87 | if ((addr & (1 << (11 + i))) != 0) { |
88 | break; |
89 | } |
90 | } |
91 | return (addr & 0x7ff) | (i << 11); |
92 | } |
93 | |
94 | static void raven_pci_io_write(void *opaque, hwaddr addr, |
95 | uint64_t val, unsigned int size) |
96 | { |
97 | PREPPCIState *s = opaque; |
98 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
99 | pci_data_write(phb->bus, raven_pci_io_config(addr), val, size); |
100 | } |
101 | |
102 | static uint64_t raven_pci_io_read(void *opaque, hwaddr addr, |
103 | unsigned int size) |
104 | { |
105 | PREPPCIState *s = opaque; |
106 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
107 | return pci_data_read(phb->bus, raven_pci_io_config(addr), size); |
108 | } |
109 | |
110 | static const MemoryRegionOps raven_pci_io_ops = { |
111 | .read = raven_pci_io_read, |
112 | .write = raven_pci_io_write, |
113 | .endianness = DEVICE_LITTLE_ENDIAN, |
114 | }; |
115 | |
116 | static uint64_t raven_intack_read(void *opaque, hwaddr addr, |
117 | unsigned int size) |
118 | { |
119 | return pic_read_irq(isa_pic); |
120 | } |
121 | |
122 | static const MemoryRegionOps raven_intack_ops = { |
123 | .read = raven_intack_read, |
124 | .valid = { |
125 | .max_access_size = 1, |
126 | }, |
127 | }; |
128 | |
129 | static inline hwaddr raven_io_address(PREPPCIState *s, |
130 | hwaddr addr) |
131 | { |
132 | if (s->contiguous_map == 0) { |
133 | /* 64 KB contiguous space for IOs */ |
134 | addr &= 0xFFFF; |
135 | } else { |
136 | /* 8 MB non-contiguous space for IOs */ |
137 | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
138 | } |
139 | |
140 | /* FIXME: handle endianness switch */ |
141 | |
142 | return addr; |
143 | } |
144 | |
145 | static uint64_t raven_io_read(void *opaque, hwaddr addr, |
146 | unsigned int size) |
147 | { |
148 | PREPPCIState *s = opaque; |
149 | uint8_t buf[4]; |
150 | |
151 | addr = raven_io_address(s, addr); |
152 | address_space_read(&s->pci_io_as, addr + 0x80000000, |
153 | MEMTXATTRS_UNSPECIFIED, buf, size); |
154 | |
155 | if (size == 1) { |
156 | return buf[0]; |
157 | } else if (size == 2) { |
158 | return lduw_le_p(buf); |
159 | } else if (size == 4) { |
160 | return ldl_le_p(buf); |
161 | } else { |
162 | g_assert_not_reached(); |
163 | } |
164 | } |
165 | |
166 | static void raven_io_write(void *opaque, hwaddr addr, |
167 | uint64_t val, unsigned int size) |
168 | { |
169 | PREPPCIState *s = opaque; |
170 | uint8_t buf[4]; |
171 | |
172 | addr = raven_io_address(s, addr); |
173 | |
174 | if (size == 1) { |
175 | buf[0] = val; |
176 | } else if (size == 2) { |
177 | stw_le_p(buf, val); |
178 | } else if (size == 4) { |
179 | stl_le_p(buf, val); |
180 | } else { |
181 | g_assert_not_reached(); |
182 | } |
183 | |
184 | address_space_write(&s->pci_io_as, addr + 0x80000000, |
185 | MEMTXATTRS_UNSPECIFIED, buf, size); |
186 | } |
187 | |
188 | static const MemoryRegionOps raven_io_ops = { |
189 | .read = raven_io_read, |
190 | .write = raven_io_write, |
191 | .endianness = DEVICE_LITTLE_ENDIAN, |
192 | .impl.max_access_size = 4, |
193 | .valid.unaligned = true, |
194 | }; |
195 | |
196 | static int raven_map_irq(PCIDevice *pci_dev, int irq_num) |
197 | { |
198 | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
199 | } |
200 | |
201 | static void raven_set_irq(void *opaque, int irq_num, int level) |
202 | { |
203 | PREPPCIState *s = opaque; |
204 | |
205 | qemu_set_irq(s->pci_irqs[irq_num], level); |
206 | } |
207 | |
208 | static AddressSpace *raven_pcihost_set_iommu(PCIBus *bus, void *opaque, |
209 | int devfn) |
210 | { |
211 | PREPPCIState *s = opaque; |
212 | |
213 | return &s->bm_as; |
214 | } |
215 | |
216 | static void raven_change_gpio(void *opaque, int n, int level) |
217 | { |
218 | PREPPCIState *s = opaque; |
219 | |
220 | s->contiguous_map = level; |
221 | } |
222 | |
223 | static void raven_pcihost_realizefn(DeviceState *d, Error **errp) |
224 | { |
225 | SysBusDevice *dev = SYS_BUS_DEVICE(d); |
226 | PCIHostState *h = PCI_HOST_BRIDGE(dev); |
227 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(dev); |
228 | MemoryRegion *address_space_mem = get_system_memory(); |
229 | int i; |
230 | |
231 | if (s->is_legacy_prep) { |
232 | for (i = 0; i < PCI_NUM_PINS; i++) { |
233 | sysbus_init_irq(dev, &s->pci_irqs[i]); |
234 | } |
235 | } else { |
236 | /* According to PReP specification section 6.1.6 "System Interrupt |
237 | * Assignments", all PCI interrupts are routed via IRQ 15 */ |
238 | s->or_irq = OR_IRQ(object_new(TYPE_OR_IRQ)); |
239 | object_property_set_int(OBJECT(s->or_irq), PCI_NUM_PINS, "num-lines" , |
240 | &error_fatal); |
241 | object_property_set_bool(OBJECT(s->or_irq), true, "realized" , |
242 | &error_fatal); |
243 | sysbus_init_irq(dev, &s->or_irq->out_irq); |
244 | |
245 | for (i = 0; i < PCI_NUM_PINS; i++) { |
246 | s->pci_irqs[i] = qdev_get_gpio_in(DEVICE(s->or_irq), i); |
247 | } |
248 | } |
249 | |
250 | qdev_init_gpio_in(d, raven_change_gpio, 1); |
251 | |
252 | pci_bus_irqs(&s->pci_bus, raven_set_irq, raven_map_irq, s, PCI_NUM_PINS); |
253 | |
254 | memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_le_ops, s, |
255 | "pci-conf-idx" , 4); |
256 | memory_region_add_subregion(&s->pci_io, 0xcf8, &h->conf_mem); |
257 | |
258 | memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, s, |
259 | "pci-conf-data" , 4); |
260 | memory_region_add_subregion(&s->pci_io, 0xcfc, &h->data_mem); |
261 | |
262 | memory_region_init_io(&h->mmcfg, OBJECT(s), &raven_pci_io_ops, s, |
263 | "pciio" , 0x00400000); |
264 | memory_region_add_subregion(address_space_mem, 0x80800000, &h->mmcfg); |
265 | |
266 | memory_region_init_io(&s->pci_intack, OBJECT(s), &raven_intack_ops, s, |
267 | "pci-intack" , 1); |
268 | memory_region_add_subregion(address_space_mem, 0xbffffff0, &s->pci_intack); |
269 | |
270 | /* TODO Remove once realize propagates to child devices. */ |
271 | object_property_set_bool(OBJECT(&s->pci_bus), true, "realized" , errp); |
272 | object_property_set_bool(OBJECT(&s->pci_dev), true, "realized" , errp); |
273 | } |
274 | |
275 | static void raven_pcihost_initfn(Object *obj) |
276 | { |
277 | PCIHostState *h = PCI_HOST_BRIDGE(obj); |
278 | PREPPCIState *s = RAVEN_PCI_HOST_BRIDGE(obj); |
279 | MemoryRegion *address_space_mem = get_system_memory(); |
280 | DeviceState *pci_dev; |
281 | |
282 | memory_region_init(&s->pci_io, obj, "pci-io" , 0x3f800000); |
283 | memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops, s, |
284 | "pci-io-non-contiguous" , 0x00800000); |
285 | memory_region_init(&s->pci_memory, obj, "pci-memory" , 0x3f000000); |
286 | address_space_init(&s->pci_io_as, &s->pci_io, "raven-io" ); |
287 | |
288 | /* CPU address space */ |
289 | memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_io); |
290 | memory_region_add_subregion_overlap(address_space_mem, 0x80000000, |
291 | &s->pci_io_non_contiguous, 1); |
292 | memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_memory); |
293 | pci_root_bus_new_inplace(&s->pci_bus, sizeof(s->pci_bus), DEVICE(obj), NULL, |
294 | &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); |
295 | |
296 | /* Bus master address space */ |
297 | memory_region_init(&s->bm, obj, "bm-raven" , UINT32_MAX); |
298 | memory_region_init_alias(&s->bm_pci_memory_alias, obj, "bm-pci-memory" , |
299 | &s->pci_memory, 0, |
300 | memory_region_size(&s->pci_memory)); |
301 | memory_region_init_alias(&s->bm_ram_alias, obj, "bm-system" , |
302 | get_system_memory(), 0, 0x80000000); |
303 | memory_region_add_subregion(&s->bm, 0 , &s->bm_pci_memory_alias); |
304 | memory_region_add_subregion(&s->bm, 0x80000000, &s->bm_ram_alias); |
305 | address_space_init(&s->bm_as, &s->bm, "raven-bm" ); |
306 | pci_setup_iommu(&s->pci_bus, raven_pcihost_set_iommu, s); |
307 | |
308 | h->bus = &s->pci_bus; |
309 | |
310 | object_initialize(&s->pci_dev, sizeof(s->pci_dev), TYPE_RAVEN_PCI_DEVICE); |
311 | pci_dev = DEVICE(&s->pci_dev); |
312 | qdev_set_parent_bus(pci_dev, BUS(&s->pci_bus)); |
313 | object_property_set_int(OBJECT(&s->pci_dev), PCI_DEVFN(0, 0), "addr" , |
314 | NULL); |
315 | qdev_prop_set_bit(pci_dev, "multifunction" , false); |
316 | } |
317 | |
318 | static void raven_realize(PCIDevice *d, Error **errp) |
319 | { |
320 | RavenPCIState *s = RAVEN_PCI_DEVICE(d); |
321 | char *filename; |
322 | int bios_size = -1; |
323 | |
324 | d->config[0x0C] = 0x08; // cache_line_size |
325 | d->config[0x0D] = 0x10; // latency_timer |
326 | d->config[0x34] = 0x00; // capabilities_pointer |
327 | |
328 | memory_region_init_ram_nomigrate(&s->bios, OBJECT(s), "bios" , BIOS_SIZE, |
329 | &error_fatal); |
330 | memory_region_set_readonly(&s->bios, true); |
331 | memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), |
332 | &s->bios); |
333 | if (s->bios_name) { |
334 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, s->bios_name); |
335 | if (filename) { |
336 | if (s->elf_machine != EM_NONE) { |
337 | bios_size = load_elf(filename, NULL, NULL, NULL, NULL, |
338 | NULL, NULL, 1, s->elf_machine, 0, 0); |
339 | } |
340 | if (bios_size < 0) { |
341 | bios_size = get_image_size(filename); |
342 | if (bios_size > 0 && bios_size <= BIOS_SIZE) { |
343 | hwaddr bios_addr; |
344 | bios_size = (bios_size + 0xfff) & ~0xfff; |
345 | bios_addr = (uint32_t)(-BIOS_SIZE); |
346 | bios_size = load_image_targphys(filename, bios_addr, |
347 | bios_size); |
348 | } |
349 | } |
350 | } |
351 | g_free(filename); |
352 | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
353 | memory_region_del_subregion(get_system_memory(), &s->bios); |
354 | error_setg(errp, "Could not load bios image '%s'" , s->bios_name); |
355 | return; |
356 | } |
357 | } |
358 | |
359 | vmstate_register_ram_global(&s->bios); |
360 | } |
361 | |
362 | static const VMStateDescription vmstate_raven = { |
363 | .name = "raven" , |
364 | .version_id = 0, |
365 | .minimum_version_id = 0, |
366 | .fields = (VMStateField[]) { |
367 | VMSTATE_PCI_DEVICE(dev, RavenPCIState), |
368 | VMSTATE_END_OF_LIST() |
369 | }, |
370 | }; |
371 | |
372 | static void raven_class_init(ObjectClass *klass, void *data) |
373 | { |
374 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
375 | DeviceClass *dc = DEVICE_CLASS(klass); |
376 | |
377 | k->realize = raven_realize; |
378 | k->vendor_id = PCI_VENDOR_ID_MOTOROLA; |
379 | k->device_id = PCI_DEVICE_ID_MOTOROLA_RAVEN; |
380 | k->revision = 0x00; |
381 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
382 | dc->desc = "PReP Host Bridge - Motorola Raven" ; |
383 | dc->vmsd = &vmstate_raven; |
384 | /* |
385 | * Reason: PCI-facing part of the host bridge, not usable without |
386 | * the host-facing part, which can't be device_add'ed, yet. |
387 | */ |
388 | dc->user_creatable = false; |
389 | } |
390 | |
391 | static const TypeInfo raven_info = { |
392 | .name = TYPE_RAVEN_PCI_DEVICE, |
393 | .parent = TYPE_PCI_DEVICE, |
394 | .instance_size = sizeof(RavenPCIState), |
395 | .class_init = raven_class_init, |
396 | .interfaces = (InterfaceInfo[]) { |
397 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
398 | { }, |
399 | }, |
400 | }; |
401 | |
402 | static Property raven_pcihost_properties[] = { |
403 | DEFINE_PROP_UINT32("elf-machine" , PREPPCIState, pci_dev.elf_machine, |
404 | EM_NONE), |
405 | DEFINE_PROP_STRING("bios-name" , PREPPCIState, pci_dev.bios_name), |
406 | /* Temporary workaround until legacy prep machine is removed */ |
407 | DEFINE_PROP_BOOL("is-legacy-prep" , PREPPCIState, is_legacy_prep, |
408 | false), |
409 | DEFINE_PROP_END_OF_LIST() |
410 | }; |
411 | |
412 | static void raven_pcihost_class_init(ObjectClass *klass, void *data) |
413 | { |
414 | DeviceClass *dc = DEVICE_CLASS(klass); |
415 | |
416 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
417 | dc->realize = raven_pcihost_realizefn; |
418 | dc->props = raven_pcihost_properties; |
419 | dc->fw_name = "pci" ; |
420 | } |
421 | |
422 | static const TypeInfo raven_pcihost_info = { |
423 | .name = TYPE_RAVEN_PCI_HOST_BRIDGE, |
424 | .parent = TYPE_PCI_HOST_BRIDGE, |
425 | .instance_size = sizeof(PREPPCIState), |
426 | .instance_init = raven_pcihost_initfn, |
427 | .class_init = raven_pcihost_class_init, |
428 | }; |
429 | |
430 | static void raven_register_types(void) |
431 | { |
432 | type_register_static(&raven_pcihost_info); |
433 | type_register_static(&raven_info); |
434 | } |
435 | |
436 | type_init(raven_register_types) |
437 | |