1 | /* |
2 | * QEMU Ultrasparc Sabre PCI host (PBM) |
3 | * |
4 | * Copyright (c) 2006 Fabrice Bellard |
5 | * Copyright (c) 2012,2013 Artyom Tarasenko |
6 | * Copyright (c) 2018 Mark Cave-Ayland |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
9 | * of this software and associated documentation files (the "Software"), to deal |
10 | * in the Software without restriction, including without limitation the rights |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
12 | * copies of the Software, and to permit persons to whom the Software is |
13 | * furnished to do so, subject to the following conditions: |
14 | * |
15 | * The above copyright notice and this permission notice shall be included in |
16 | * all copies or substantial portions of the Software. |
17 | * |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
24 | * THE SOFTWARE. |
25 | */ |
26 | |
27 | #include "qemu/osdep.h" |
28 | #include "hw/sysbus.h" |
29 | #include "hw/pci/pci.h" |
30 | #include "hw/pci/pci_host.h" |
31 | #include "hw/qdev-properties.h" |
32 | #include "hw/pci/pci_bridge.h" |
33 | #include "hw/pci/pci_bus.h" |
34 | #include "hw/irq.h" |
35 | #include "hw/pci-bridge/simba.h" |
36 | #include "hw/pci-host/sabre.h" |
37 | #include "exec/address-spaces.h" |
38 | #include "qemu/log.h" |
39 | #include "qemu/module.h" |
40 | #include "sysemu/runstate.h" |
41 | #include "trace.h" |
42 | |
43 | /* |
44 | * Chipset docs: |
45 | * PBM: "UltraSPARC IIi User's Manual", |
46 | * http://www.sun.com/processors/manuals/805-0087.pdf |
47 | */ |
48 | |
49 | #define PBM_PCI_IMR_MASK 0x7fffffff |
50 | #define PBM_PCI_IMR_ENABLED 0x80000000 |
51 | |
52 | #define POR (1U << 31) |
53 | #define SOFT_POR (1U << 30) |
54 | #define SOFT_XIR (1U << 29) |
55 | #define BTN_POR (1U << 28) |
56 | #define BTN_XIR (1U << 27) |
57 | #define RESET_MASK 0xf8000000 |
58 | #define RESET_WCMASK 0x98000000 |
59 | #define RESET_WMASK 0x60000000 |
60 | |
61 | #define NO_IRQ_REQUEST (MAX_IVEC + 1) |
62 | |
63 | static inline void sabre_set_request(SabreState *s, unsigned int irq_num) |
64 | { |
65 | trace_sabre_set_request(irq_num); |
66 | s->irq_request = irq_num; |
67 | qemu_set_irq(s->ivec_irqs[irq_num], 1); |
68 | } |
69 | |
70 | static inline void sabre_check_irqs(SabreState *s) |
71 | { |
72 | unsigned int i; |
73 | |
74 | /* Previous request is not acknowledged, resubmit */ |
75 | if (s->irq_request != NO_IRQ_REQUEST) { |
76 | sabre_set_request(s, s->irq_request); |
77 | return; |
78 | } |
79 | /* no request pending */ |
80 | if (s->pci_irq_in == 0ULL) { |
81 | return; |
82 | } |
83 | for (i = 0; i < 32; i++) { |
84 | if (s->pci_irq_in & (1ULL << i)) { |
85 | if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { |
86 | sabre_set_request(s, i); |
87 | return; |
88 | } |
89 | } |
90 | } |
91 | for (i = 32; i < 64; i++) { |
92 | if (s->pci_irq_in & (1ULL << i)) { |
93 | if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { |
94 | sabre_set_request(s, i); |
95 | break; |
96 | } |
97 | } |
98 | } |
99 | } |
100 | |
101 | static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) |
102 | { |
103 | trace_sabre_clear_request(irq_num); |
104 | qemu_set_irq(s->ivec_irqs[irq_num], 0); |
105 | s->irq_request = NO_IRQ_REQUEST; |
106 | } |
107 | |
108 | static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) |
109 | { |
110 | IOMMUState *is = opaque; |
111 | |
112 | return &is->iommu_as; |
113 | } |
114 | |
115 | static void sabre_config_write(void *opaque, hwaddr addr, |
116 | uint64_t val, unsigned size) |
117 | { |
118 | SabreState *s = opaque; |
119 | |
120 | trace_sabre_config_write(addr, val); |
121 | |
122 | switch (addr & 0xffff) { |
123 | case 0x30 ... 0x4f: /* DMA error registers */ |
124 | /* XXX: not implemented yet */ |
125 | break; |
126 | case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
127 | if (addr & 4) { |
128 | unsigned int ino = (addr & 0x3f) >> 3; |
129 | s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; |
130 | s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; |
131 | if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { |
132 | sabre_clear_request(s, ino); |
133 | } |
134 | sabre_check_irqs(s); |
135 | } |
136 | break; |
137 | case 0x1000 ... 0x107f: /* OBIO interrupt control */ |
138 | if (addr & 4) { |
139 | unsigned int ino = ((addr & 0xff) >> 3); |
140 | s->obio_irq_map[ino] &= PBM_PCI_IMR_MASK; |
141 | s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; |
142 | if ((s->irq_request == (ino | 0x20)) |
143 | && !(val & ~PBM_PCI_IMR_MASK)) { |
144 | sabre_clear_request(s, ino | 0x20); |
145 | } |
146 | sabre_check_irqs(s); |
147 | } |
148 | break; |
149 | case 0x1400 ... 0x14ff: /* PCI interrupt clear */ |
150 | if (addr & 4) { |
151 | unsigned int ino = (addr & 0xff) >> 5; |
152 | if ((s->irq_request / 4) == ino) { |
153 | sabre_clear_request(s, s->irq_request); |
154 | sabre_check_irqs(s); |
155 | } |
156 | } |
157 | break; |
158 | case 0x1800 ... 0x1860: /* OBIO interrupt clear */ |
159 | if (addr & 4) { |
160 | unsigned int ino = ((addr & 0xff) >> 3) | 0x20; |
161 | if (s->irq_request == ino) { |
162 | sabre_clear_request(s, ino); |
163 | sabre_check_irqs(s); |
164 | } |
165 | } |
166 | break; |
167 | case 0x2000 ... 0x202f: /* PCI control */ |
168 | s->pci_control[(addr & 0x3f) >> 2] = val; |
169 | break; |
170 | case 0xf020 ... 0xf027: /* Reset control */ |
171 | if (addr & 4) { |
172 | val &= RESET_MASK; |
173 | s->reset_control &= ~(val & RESET_WCMASK); |
174 | s->reset_control |= val & RESET_WMASK; |
175 | if (val & SOFT_POR) { |
176 | s->nr_resets = 0; |
177 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
178 | } else if (val & SOFT_XIR) { |
179 | qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); |
180 | } |
181 | } |
182 | break; |
183 | case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ |
184 | case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ |
185 | case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ |
186 | case 0xf000 ... 0xf01f: /* FFB config, memory control */ |
187 | /* we don't care */ |
188 | default: |
189 | break; |
190 | } |
191 | } |
192 | |
193 | static uint64_t sabre_config_read(void *opaque, |
194 | hwaddr addr, unsigned size) |
195 | { |
196 | SabreState *s = opaque; |
197 | uint32_t val; |
198 | |
199 | switch (addr & 0xffff) { |
200 | case 0x30 ... 0x4f: /* DMA error registers */ |
201 | val = 0; |
202 | /* XXX: not implemented yet */ |
203 | break; |
204 | case 0xc00 ... 0xc3f: /* PCI interrupt control */ |
205 | if (addr & 4) { |
206 | val = s->pci_irq_map[(addr & 0x3f) >> 3]; |
207 | } else { |
208 | val = 0; |
209 | } |
210 | break; |
211 | case 0x1000 ... 0x107f: /* OBIO interrupt control */ |
212 | if (addr & 4) { |
213 | val = s->obio_irq_map[(addr & 0xff) >> 3]; |
214 | } else { |
215 | val = 0; |
216 | } |
217 | break; |
218 | case 0x1080 ... 0x108f: /* PCI bus error */ |
219 | if (addr & 4) { |
220 | val = s->pci_err_irq_map[(addr & 0xf) >> 3]; |
221 | } else { |
222 | val = 0; |
223 | } |
224 | break; |
225 | case 0x2000 ... 0x202f: /* PCI control */ |
226 | val = s->pci_control[(addr & 0x3f) >> 2]; |
227 | break; |
228 | case 0xf020 ... 0xf027: /* Reset control */ |
229 | if (addr & 4) { |
230 | val = s->reset_control; |
231 | } else { |
232 | val = 0; |
233 | } |
234 | break; |
235 | case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ |
236 | case 0xa400 ... 0xa67f: /* IOMMU diagnostics */ |
237 | case 0xa800 ... 0xa80f: /* Interrupt diagnostics */ |
238 | case 0xf000 ... 0xf01f: /* FFB config, memory control */ |
239 | /* we don't care */ |
240 | default: |
241 | val = 0; |
242 | break; |
243 | } |
244 | trace_sabre_config_read(addr, val); |
245 | |
246 | return val; |
247 | } |
248 | |
249 | static const MemoryRegionOps sabre_config_ops = { |
250 | .read = sabre_config_read, |
251 | .write = sabre_config_write, |
252 | .endianness = DEVICE_BIG_ENDIAN, |
253 | }; |
254 | |
255 | static void sabre_pci_config_write(void *opaque, hwaddr addr, |
256 | uint64_t val, unsigned size) |
257 | { |
258 | SabreState *s = opaque; |
259 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
260 | |
261 | trace_sabre_pci_config_write(addr, val); |
262 | pci_data_write(phb->bus, addr, val, size); |
263 | } |
264 | |
265 | static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, |
266 | unsigned size) |
267 | { |
268 | uint32_t ret; |
269 | SabreState *s = opaque; |
270 | PCIHostState *phb = PCI_HOST_BRIDGE(s); |
271 | |
272 | ret = pci_data_read(phb->bus, addr, size); |
273 | trace_sabre_pci_config_read(addr, ret); |
274 | return ret; |
275 | } |
276 | |
277 | /* The sabre host has an IRQ line for each IRQ line of each slot. */ |
278 | static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) |
279 | { |
280 | /* Return the irq as swizzled by the PBM */ |
281 | return irq_num; |
282 | } |
283 | |
284 | static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) |
285 | { |
286 | /* The on-board devices have fixed (legacy) OBIO intnos */ |
287 | switch (PCI_SLOT(pci_dev->devfn)) { |
288 | case 1: |
289 | /* Onboard NIC */ |
290 | return OBIO_NIC_IRQ; |
291 | case 3: |
292 | /* Onboard IDE */ |
293 | return OBIO_HDD_IRQ; |
294 | default: |
295 | /* Normal intno, fall through */ |
296 | break; |
297 | } |
298 | |
299 | return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; |
300 | } |
301 | |
302 | static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) |
303 | { |
304 | return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; |
305 | } |
306 | |
307 | static void pci_sabre_set_irq(void *opaque, int irq_num, int level) |
308 | { |
309 | SabreState *s = opaque; |
310 | |
311 | trace_sabre_pci_set_irq(irq_num, level); |
312 | |
313 | /* PCI IRQ map onto the first 32 INO. */ |
314 | if (irq_num < 32) { |
315 | if (level) { |
316 | s->pci_irq_in |= 1ULL << irq_num; |
317 | if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { |
318 | sabre_set_request(s, irq_num); |
319 | } |
320 | } else { |
321 | s->pci_irq_in &= ~(1ULL << irq_num); |
322 | } |
323 | } else { |
324 | /* OBIO IRQ map onto the next 32 INO. */ |
325 | if (level) { |
326 | trace_sabre_pci_set_obio_irq(irq_num, level); |
327 | s->pci_irq_in |= 1ULL << irq_num; |
328 | if ((s->irq_request == NO_IRQ_REQUEST) |
329 | && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { |
330 | sabre_set_request(s, irq_num); |
331 | } |
332 | } else { |
333 | s->pci_irq_in &= ~(1ULL << irq_num); |
334 | } |
335 | } |
336 | } |
337 | |
338 | static void sabre_reset(DeviceState *d) |
339 | { |
340 | SabreState *s = SABRE_DEVICE(d); |
341 | PCIDevice *pci_dev; |
342 | unsigned int i; |
343 | uint16_t cmd; |
344 | |
345 | for (i = 0; i < 8; i++) { |
346 | s->pci_irq_map[i] &= PBM_PCI_IMR_MASK; |
347 | } |
348 | for (i = 0; i < 32; i++) { |
349 | s->obio_irq_map[i] &= PBM_PCI_IMR_MASK; |
350 | } |
351 | |
352 | s->irq_request = NO_IRQ_REQUEST; |
353 | s->pci_irq_in = 0ULL; |
354 | |
355 | if (s->nr_resets++ == 0) { |
356 | /* Power on reset */ |
357 | s->reset_control = POR; |
358 | } |
359 | |
360 | /* As this is the busA PCI bridge which contains the on-board devices |
361 | * attached to the ebus, ensure that we initially allow IO transactions |
362 | * so that we get the early serial console until OpenBIOS can properly |
363 | * configure the PCI bridge itself */ |
364 | pci_dev = PCI_DEVICE(s->bridgeA); |
365 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); |
366 | pci_set_word(pci_dev->config + PCI_COMMAND, cmd | PCI_COMMAND_IO); |
367 | pci_bridge_update_mappings(PCI_BRIDGE(pci_dev)); |
368 | } |
369 | |
370 | static const MemoryRegionOps pci_config_ops = { |
371 | .read = sabre_pci_config_read, |
372 | .write = sabre_pci_config_write, |
373 | .endianness = DEVICE_LITTLE_ENDIAN, |
374 | }; |
375 | |
376 | static void sabre_realize(DeviceState *dev, Error **errp) |
377 | { |
378 | SabreState *s = SABRE_DEVICE(dev); |
379 | PCIHostState *phb = PCI_HOST_BRIDGE(dev); |
380 | SysBusDevice *sbd = SYS_BUS_DEVICE(s); |
381 | PCIDevice *pci_dev; |
382 | |
383 | /* sabre_config */ |
384 | sysbus_mmio_map(sbd, 0, s->special_base); |
385 | /* PCI configuration space */ |
386 | sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); |
387 | /* pci_ioport */ |
388 | sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); |
389 | |
390 | memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio" , 0x100000000ULL); |
391 | memory_region_add_subregion(get_system_memory(), s->mem_base, |
392 | &s->pci_mmio); |
393 | |
394 | phb->bus = pci_register_root_bus(dev, "pci" , |
395 | pci_sabre_set_irq, pci_sabre_map_irq, s, |
396 | &s->pci_mmio, |
397 | &s->pci_ioport, |
398 | 0, 32, TYPE_PCI_BUS); |
399 | |
400 | pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); |
401 | |
402 | /* IOMMU */ |
403 | memory_region_add_subregion_overlap(&s->sabre_config, 0x200, |
404 | sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); |
405 | pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); |
406 | |
407 | /* APB secondary busses */ |
408 | pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, |
409 | TYPE_SIMBA_PCI_BRIDGE); |
410 | s->bridgeB = PCI_BRIDGE(pci_dev); |
411 | pci_bridge_map_irq(s->bridgeB, "pciB" , pci_simbaB_map_irq); |
412 | qdev_init_nofail(&pci_dev->qdev); |
413 | |
414 | pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, |
415 | TYPE_SIMBA_PCI_BRIDGE); |
416 | s->bridgeA = PCI_BRIDGE(pci_dev); |
417 | pci_bridge_map_irq(s->bridgeA, "pciA" , pci_simbaA_map_irq); |
418 | qdev_init_nofail(&pci_dev->qdev); |
419 | } |
420 | |
421 | static void sabre_init(Object *obj) |
422 | { |
423 | SabreState *s = SABRE_DEVICE(obj); |
424 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
425 | unsigned int i; |
426 | |
427 | for (i = 0; i < 8; i++) { |
428 | s->pci_irq_map[i] = (0x1f << 6) | (i << 2); |
429 | } |
430 | for (i = 0; i < 2; i++) { |
431 | s->pci_err_irq_map[i] = (0x1f << 6) | 0x30; |
432 | } |
433 | for (i = 0; i < 32; i++) { |
434 | s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; |
435 | } |
436 | qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq" , MAX_IVEC); |
437 | qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq" , MAX_IVEC); |
438 | s->irq_request = NO_IRQ_REQUEST; |
439 | s->pci_irq_in = 0ULL; |
440 | |
441 | /* IOMMU */ |
442 | object_property_add_link(obj, "iommu" , TYPE_SUN4U_IOMMU, |
443 | (Object **) &s->iommu, |
444 | qdev_prop_allow_set_link_before_realize, |
445 | 0, NULL); |
446 | |
447 | /* sabre_config */ |
448 | memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, |
449 | "sabre-config" , 0x10000); |
450 | /* at region 0 */ |
451 | sysbus_init_mmio(sbd, &s->sabre_config); |
452 | |
453 | memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, |
454 | "sabre-pci-config" , 0x1000000); |
455 | /* at region 1 */ |
456 | sysbus_init_mmio(sbd, &s->pci_config); |
457 | |
458 | /* pci_ioport */ |
459 | memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport" , |
460 | 0x1000000); |
461 | |
462 | /* at region 2 */ |
463 | sysbus_init_mmio(sbd, &s->pci_ioport); |
464 | } |
465 | |
466 | static void sabre_pci_realize(PCIDevice *d, Error **errp) |
467 | { |
468 | pci_set_word(d->config + PCI_COMMAND, |
469 | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); |
470 | pci_set_word(d->config + PCI_STATUS, |
471 | PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | |
472 | PCI_STATUS_DEVSEL_MEDIUM); |
473 | } |
474 | |
475 | static void sabre_pci_class_init(ObjectClass *klass, void *data) |
476 | { |
477 | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
478 | DeviceClass *dc = DEVICE_CLASS(klass); |
479 | |
480 | k->realize = sabre_pci_realize; |
481 | k->vendor_id = PCI_VENDOR_ID_SUN; |
482 | k->device_id = PCI_DEVICE_ID_SUN_SABRE; |
483 | k->class_id = PCI_CLASS_BRIDGE_HOST; |
484 | /* |
485 | * PCI-facing part of the host bridge, not usable without the |
486 | * host-facing part, which can't be device_add'ed, yet. |
487 | */ |
488 | dc->user_creatable = false; |
489 | } |
490 | |
491 | static const TypeInfo sabre_pci_info = { |
492 | .name = TYPE_SABRE_PCI_DEVICE, |
493 | .parent = TYPE_PCI_DEVICE, |
494 | .instance_size = sizeof(SabrePCIState), |
495 | .class_init = sabre_pci_class_init, |
496 | .interfaces = (InterfaceInfo[]) { |
497 | { INTERFACE_CONVENTIONAL_PCI_DEVICE }, |
498 | { }, |
499 | }, |
500 | }; |
501 | |
502 | static char *sabre_ofw_unit_address(const SysBusDevice *dev) |
503 | { |
504 | SabreState *s = SABRE_DEVICE(dev); |
505 | |
506 | return g_strdup_printf("%x,%x" , |
507 | (uint32_t)((s->special_base >> 32) & 0xffffffff), |
508 | (uint32_t)(s->special_base & 0xffffffff)); |
509 | } |
510 | |
511 | static Property sabre_properties[] = { |
512 | DEFINE_PROP_UINT64("special-base" , SabreState, special_base, 0), |
513 | DEFINE_PROP_UINT64("mem-base" , SabreState, mem_base, 0), |
514 | DEFINE_PROP_END_OF_LIST(), |
515 | }; |
516 | |
517 | static void sabre_class_init(ObjectClass *klass, void *data) |
518 | { |
519 | DeviceClass *dc = DEVICE_CLASS(klass); |
520 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
521 | |
522 | dc->realize = sabre_realize; |
523 | dc->reset = sabre_reset; |
524 | dc->props = sabre_properties; |
525 | set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); |
526 | dc->fw_name = "pci" ; |
527 | sbc->explicit_ofw_unit_address = sabre_ofw_unit_address; |
528 | } |
529 | |
530 | static const TypeInfo sabre_info = { |
531 | .name = TYPE_SABRE, |
532 | .parent = TYPE_PCI_HOST_BRIDGE, |
533 | .instance_size = sizeof(SabreState), |
534 | .instance_init = sabre_init, |
535 | .class_init = sabre_class_init, |
536 | }; |
537 | |
538 | static void sabre_register_types(void) |
539 | { |
540 | type_register_static(&sabre_info); |
541 | type_register_static(&sabre_pci_info); |
542 | } |
543 | |
544 | type_init(sabre_register_types) |
545 | |