1 | /* |
2 | * QEMU PCI bus manager |
3 | * |
4 | * Copyright (c) 2004 Fabrice Bellard |
5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal |
8 | * in the Software without restriction, including without limitation the rights |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell |
10 | * copies of the Software, and to permit persons to whom the Software is |
11 | * furnished to do so, subject to the following conditions: |
12 | * |
13 | * The above copyright notice and this permission notice shall be included in |
14 | * all copies or substantial portions of the Software. |
15 | * |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN |
22 | * THE SOFTWARE. |
23 | */ |
24 | |
25 | #include "qemu/osdep.h" |
26 | #include "qemu-common.h" |
27 | #include "hw/irq.h" |
28 | #include "hw/pci/pci.h" |
29 | #include "hw/pci/pci_bridge.h" |
30 | #include "hw/pci/pci_bus.h" |
31 | #include "hw/pci/pci_host.h" |
32 | #include "hw/qdev-properties.h" |
33 | #include "migration/qemu-file-types.h" |
34 | #include "migration/vmstate.h" |
35 | #include "monitor/monitor.h" |
36 | #include "net/net.h" |
37 | #include "sysemu/numa.h" |
38 | #include "sysemu/sysemu.h" |
39 | #include "hw/loader.h" |
40 | #include "qemu/error-report.h" |
41 | #include "qemu/range.h" |
42 | #include "trace.h" |
43 | #include "hw/pci/msi.h" |
44 | #include "hw/pci/msix.h" |
45 | #include "exec/address-spaces.h" |
46 | #include "hw/hotplug.h" |
47 | #include "hw/boards.h" |
48 | #include "qapi/error.h" |
49 | #include "qapi/qapi-commands-misc.h" |
50 | #include "qemu/cutils.h" |
51 | |
52 | //#define DEBUG_PCI |
53 | #ifdef DEBUG_PCI |
54 | # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) |
55 | #else |
56 | # define PCI_DPRINTF(format, ...) do { } while (0) |
57 | #endif |
58 | |
59 | bool pci_available = true; |
60 | |
61 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent); |
62 | static char *pcibus_get_dev_path(DeviceState *dev); |
63 | static char *pcibus_get_fw_dev_path(DeviceState *dev); |
64 | static void pcibus_reset(BusState *qbus); |
65 | |
66 | static Property pci_props[] = { |
67 | DEFINE_PROP_PCI_DEVFN("addr" , PCIDevice, devfn, -1), |
68 | DEFINE_PROP_STRING("romfile" , PCIDevice, romfile), |
69 | DEFINE_PROP_UINT32("rombar" , PCIDevice, rom_bar, 1), |
70 | DEFINE_PROP_BIT("multifunction" , PCIDevice, cap_present, |
71 | QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false), |
72 | DEFINE_PROP_BIT("command_serr_enable" , PCIDevice, cap_present, |
73 | QEMU_PCI_CAP_SERR_BITNR, true), |
74 | DEFINE_PROP_BIT("x-pcie-lnksta-dllla" , PCIDevice, cap_present, |
75 | QEMU_PCIE_LNKSTA_DLLLA_BITNR, true), |
76 | DEFINE_PROP_BIT("x-pcie-extcap-init" , PCIDevice, cap_present, |
77 | QEMU_PCIE_EXTCAP_INIT_BITNR, true), |
78 | DEFINE_PROP_END_OF_LIST() |
79 | }; |
80 | |
81 | static const VMStateDescription vmstate_pcibus = { |
82 | .name = "PCIBUS" , |
83 | .version_id = 1, |
84 | .minimum_version_id = 1, |
85 | .fields = (VMStateField[]) { |
86 | VMSTATE_INT32_EQUAL(nirq, PCIBus, NULL), |
87 | VMSTATE_VARRAY_INT32(irq_count, PCIBus, |
88 | nirq, 0, vmstate_info_int32, |
89 | int32_t), |
90 | VMSTATE_END_OF_LIST() |
91 | } |
92 | }; |
93 | |
94 | static void pci_init_bus_master(PCIDevice *pci_dev) |
95 | { |
96 | AddressSpace *dma_as = pci_device_iommu_address_space(pci_dev); |
97 | |
98 | memory_region_init_alias(&pci_dev->bus_master_enable_region, |
99 | OBJECT(pci_dev), "bus master" , |
100 | dma_as->root, 0, memory_region_size(dma_as->root)); |
101 | memory_region_set_enabled(&pci_dev->bus_master_enable_region, false); |
102 | memory_region_add_subregion(&pci_dev->bus_master_container_region, 0, |
103 | &pci_dev->bus_master_enable_region); |
104 | } |
105 | |
106 | static void pcibus_machine_done(Notifier *notifier, void *data) |
107 | { |
108 | PCIBus *bus = container_of(notifier, PCIBus, machine_done); |
109 | int i; |
110 | |
111 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
112 | if (bus->devices[i]) { |
113 | pci_init_bus_master(bus->devices[i]); |
114 | } |
115 | } |
116 | } |
117 | |
118 | static void pci_bus_realize(BusState *qbus, Error **errp) |
119 | { |
120 | PCIBus *bus = PCI_BUS(qbus); |
121 | |
122 | bus->machine_done.notify = pcibus_machine_done; |
123 | qemu_add_machine_init_done_notifier(&bus->machine_done); |
124 | |
125 | vmstate_register(NULL, -1, &vmstate_pcibus, bus); |
126 | } |
127 | |
128 | static void pcie_bus_realize(BusState *qbus, Error **errp) |
129 | { |
130 | PCIBus *bus = PCI_BUS(qbus); |
131 | |
132 | pci_bus_realize(qbus, errp); |
133 | |
134 | /* |
135 | * A PCI-E bus can support extended config space if it's the root |
136 | * bus, or if the bus/bridge above it does as well |
137 | */ |
138 | if (pci_bus_is_root(bus)) { |
139 | bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; |
140 | } else { |
141 | PCIBus *parent_bus = pci_get_bus(bus->parent_dev); |
142 | |
143 | if (pci_bus_allows_extended_config_space(parent_bus)) { |
144 | bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; |
145 | } |
146 | } |
147 | } |
148 | |
149 | static void pci_bus_unrealize(BusState *qbus, Error **errp) |
150 | { |
151 | PCIBus *bus = PCI_BUS(qbus); |
152 | |
153 | qemu_remove_machine_init_done_notifier(&bus->machine_done); |
154 | |
155 | vmstate_unregister(NULL, &vmstate_pcibus, bus); |
156 | } |
157 | |
158 | static int pcibus_num(PCIBus *bus) |
159 | { |
160 | if (pci_bus_is_root(bus)) { |
161 | return 0; /* pci host bridge */ |
162 | } |
163 | return bus->parent_dev->config[PCI_SECONDARY_BUS]; |
164 | } |
165 | |
166 | static uint16_t pcibus_numa_node(PCIBus *bus) |
167 | { |
168 | return NUMA_NODE_UNASSIGNED; |
169 | } |
170 | |
171 | static void pci_bus_class_init(ObjectClass *klass, void *data) |
172 | { |
173 | BusClass *k = BUS_CLASS(klass); |
174 | PCIBusClass *pbc = PCI_BUS_CLASS(klass); |
175 | |
176 | k->print_dev = pcibus_dev_print; |
177 | k->get_dev_path = pcibus_get_dev_path; |
178 | k->get_fw_dev_path = pcibus_get_fw_dev_path; |
179 | k->realize = pci_bus_realize; |
180 | k->unrealize = pci_bus_unrealize; |
181 | k->reset = pcibus_reset; |
182 | |
183 | pbc->bus_num = pcibus_num; |
184 | pbc->numa_node = pcibus_numa_node; |
185 | } |
186 | |
187 | static const TypeInfo pci_bus_info = { |
188 | .name = TYPE_PCI_BUS, |
189 | .parent = TYPE_BUS, |
190 | .instance_size = sizeof(PCIBus), |
191 | .class_size = sizeof(PCIBusClass), |
192 | .class_init = pci_bus_class_init, |
193 | }; |
194 | |
195 | static const TypeInfo pcie_interface_info = { |
196 | .name = INTERFACE_PCIE_DEVICE, |
197 | .parent = TYPE_INTERFACE, |
198 | }; |
199 | |
200 | static const TypeInfo conventional_pci_interface_info = { |
201 | .name = INTERFACE_CONVENTIONAL_PCI_DEVICE, |
202 | .parent = TYPE_INTERFACE, |
203 | }; |
204 | |
205 | static void pcie_bus_class_init(ObjectClass *klass, void *data) |
206 | { |
207 | BusClass *k = BUS_CLASS(klass); |
208 | |
209 | k->realize = pcie_bus_realize; |
210 | } |
211 | |
212 | static const TypeInfo pcie_bus_info = { |
213 | .name = TYPE_PCIE_BUS, |
214 | .parent = TYPE_PCI_BUS, |
215 | .class_init = pcie_bus_class_init, |
216 | }; |
217 | |
218 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num); |
219 | static void pci_update_mappings(PCIDevice *d); |
220 | static void pci_irq_handler(void *opaque, int irq_num, int level); |
221 | static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, Error **); |
222 | static void pci_del_option_rom(PCIDevice *pdev); |
223 | |
224 | static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET; |
225 | static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU; |
226 | |
227 | static QLIST_HEAD(, PCIHostState) pci_host_bridges; |
228 | |
229 | int pci_bar(PCIDevice *d, int reg) |
230 | { |
231 | uint8_t type; |
232 | |
233 | if (reg != PCI_ROM_SLOT) |
234 | return PCI_BASE_ADDRESS_0 + reg * 4; |
235 | |
236 | type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
237 | return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS; |
238 | } |
239 | |
240 | static inline int pci_irq_state(PCIDevice *d, int irq_num) |
241 | { |
242 | return (d->irq_state >> irq_num) & 0x1; |
243 | } |
244 | |
245 | static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level) |
246 | { |
247 | d->irq_state &= ~(0x1 << irq_num); |
248 | d->irq_state |= level << irq_num; |
249 | } |
250 | |
251 | static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change) |
252 | { |
253 | PCIBus *bus; |
254 | for (;;) { |
255 | bus = pci_get_bus(pci_dev); |
256 | irq_num = bus->map_irq(pci_dev, irq_num); |
257 | if (bus->set_irq) |
258 | break; |
259 | pci_dev = bus->parent_dev; |
260 | } |
261 | bus->irq_count[irq_num] += change; |
262 | bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0); |
263 | } |
264 | |
265 | int pci_bus_get_irq_level(PCIBus *bus, int irq_num) |
266 | { |
267 | assert(irq_num >= 0); |
268 | assert(irq_num < bus->nirq); |
269 | return !!bus->irq_count[irq_num]; |
270 | } |
271 | |
272 | /* Update interrupt status bit in config space on interrupt |
273 | * state change. */ |
274 | static void pci_update_irq_status(PCIDevice *dev) |
275 | { |
276 | if (dev->irq_state) { |
277 | dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT; |
278 | } else { |
279 | dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
280 | } |
281 | } |
282 | |
283 | void pci_device_deassert_intx(PCIDevice *dev) |
284 | { |
285 | int i; |
286 | for (i = 0; i < PCI_NUM_PINS; ++i) { |
287 | pci_irq_handler(dev, i, 0); |
288 | } |
289 | } |
290 | |
291 | static void pci_do_device_reset(PCIDevice *dev) |
292 | { |
293 | int r; |
294 | |
295 | pci_device_deassert_intx(dev); |
296 | assert(dev->irq_state == 0); |
297 | |
298 | /* Clear all writable bits */ |
299 | pci_word_test_and_clear_mask(dev->config + PCI_COMMAND, |
300 | pci_get_word(dev->wmask + PCI_COMMAND) | |
301 | pci_get_word(dev->w1cmask + PCI_COMMAND)); |
302 | pci_word_test_and_clear_mask(dev->config + PCI_STATUS, |
303 | pci_get_word(dev->wmask + PCI_STATUS) | |
304 | pci_get_word(dev->w1cmask + PCI_STATUS)); |
305 | dev->config[PCI_CACHE_LINE_SIZE] = 0x0; |
306 | dev->config[PCI_INTERRUPT_LINE] = 0x0; |
307 | for (r = 0; r < PCI_NUM_REGIONS; ++r) { |
308 | PCIIORegion *region = &dev->io_regions[r]; |
309 | if (!region->size) { |
310 | continue; |
311 | } |
312 | |
313 | if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) && |
314 | region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
315 | pci_set_quad(dev->config + pci_bar(dev, r), region->type); |
316 | } else { |
317 | pci_set_long(dev->config + pci_bar(dev, r), region->type); |
318 | } |
319 | } |
320 | pci_update_mappings(dev); |
321 | |
322 | msi_reset(dev); |
323 | msix_reset(dev); |
324 | } |
325 | |
326 | /* |
327 | * This function is called on #RST and FLR. |
328 | * FLR if PCI_EXP_DEVCTL_BCR_FLR is set |
329 | */ |
330 | void pci_device_reset(PCIDevice *dev) |
331 | { |
332 | qdev_reset_all(&dev->qdev); |
333 | pci_do_device_reset(dev); |
334 | } |
335 | |
336 | /* |
337 | * Trigger pci bus reset under a given bus. |
338 | * Called via qbus_reset_all on RST# assert, after the devices |
339 | * have been reset qdev_reset_all-ed already. |
340 | */ |
341 | static void pcibus_reset(BusState *qbus) |
342 | { |
343 | PCIBus *bus = DO_UPCAST(PCIBus, qbus, qbus); |
344 | int i; |
345 | |
346 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
347 | if (bus->devices[i]) { |
348 | pci_do_device_reset(bus->devices[i]); |
349 | } |
350 | } |
351 | |
352 | for (i = 0; i < bus->nirq; i++) { |
353 | assert(bus->irq_count[i] == 0); |
354 | } |
355 | } |
356 | |
357 | static void pci_host_bus_register(DeviceState *host) |
358 | { |
359 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); |
360 | |
361 | QLIST_INSERT_HEAD(&pci_host_bridges, host_bridge, next); |
362 | } |
363 | |
364 | static void pci_host_bus_unregister(DeviceState *host) |
365 | { |
366 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(host); |
367 | |
368 | QLIST_REMOVE(host_bridge, next); |
369 | } |
370 | |
371 | PCIBus *pci_device_root_bus(const PCIDevice *d) |
372 | { |
373 | PCIBus *bus = pci_get_bus(d); |
374 | |
375 | while (!pci_bus_is_root(bus)) { |
376 | d = bus->parent_dev; |
377 | assert(d != NULL); |
378 | |
379 | bus = pci_get_bus(d); |
380 | } |
381 | |
382 | return bus; |
383 | } |
384 | |
385 | const char *pci_root_bus_path(PCIDevice *dev) |
386 | { |
387 | PCIBus *rootbus = pci_device_root_bus(dev); |
388 | PCIHostState *host_bridge = PCI_HOST_BRIDGE(rootbus->qbus.parent); |
389 | PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_GET_CLASS(host_bridge); |
390 | |
391 | assert(host_bridge->bus == rootbus); |
392 | |
393 | if (hc->root_bus_path) { |
394 | return (*hc->root_bus_path)(host_bridge, rootbus); |
395 | } |
396 | |
397 | return rootbus->qbus.name; |
398 | } |
399 | |
400 | static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, |
401 | MemoryRegion *address_space_mem, |
402 | MemoryRegion *address_space_io, |
403 | uint8_t devfn_min) |
404 | { |
405 | assert(PCI_FUNC(devfn_min) == 0); |
406 | bus->devfn_min = devfn_min; |
407 | bus->slot_reserved_mask = 0x0; |
408 | bus->address_space_mem = address_space_mem; |
409 | bus->address_space_io = address_space_io; |
410 | bus->flags |= PCI_BUS_IS_ROOT; |
411 | |
412 | /* host bridge */ |
413 | QLIST_INIT(&bus->child); |
414 | |
415 | pci_host_bus_register(parent); |
416 | } |
417 | |
418 | static void pci_bus_uninit(PCIBus *bus) |
419 | { |
420 | pci_host_bus_unregister(BUS(bus)->parent); |
421 | } |
422 | |
423 | bool pci_bus_is_express(PCIBus *bus) |
424 | { |
425 | return object_dynamic_cast(OBJECT(bus), TYPE_PCIE_BUS); |
426 | } |
427 | |
428 | void pci_root_bus_new_inplace(PCIBus *bus, size_t bus_size, DeviceState *parent, |
429 | const char *name, |
430 | MemoryRegion *address_space_mem, |
431 | MemoryRegion *address_space_io, |
432 | uint8_t devfn_min, const char *typename) |
433 | { |
434 | qbus_create_inplace(bus, bus_size, typename, parent, name); |
435 | pci_root_bus_init(bus, parent, address_space_mem, address_space_io, |
436 | devfn_min); |
437 | } |
438 | |
439 | PCIBus *pci_root_bus_new(DeviceState *parent, const char *name, |
440 | MemoryRegion *address_space_mem, |
441 | MemoryRegion *address_space_io, |
442 | uint8_t devfn_min, const char *typename) |
443 | { |
444 | PCIBus *bus; |
445 | |
446 | bus = PCI_BUS(qbus_create(typename, parent, name)); |
447 | pci_root_bus_init(bus, parent, address_space_mem, address_space_io, |
448 | devfn_min); |
449 | return bus; |
450 | } |
451 | |
452 | void pci_root_bus_cleanup(PCIBus *bus) |
453 | { |
454 | pci_bus_uninit(bus); |
455 | /* the caller of the unplug hotplug handler will delete this device */ |
456 | object_property_set_bool(OBJECT(bus), false, "realized" , NULL); |
457 | } |
458 | |
459 | void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
460 | void *irq_opaque, int nirq) |
461 | { |
462 | bus->set_irq = set_irq; |
463 | bus->map_irq = map_irq; |
464 | bus->irq_opaque = irq_opaque; |
465 | bus->nirq = nirq; |
466 | bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0])); |
467 | } |
468 | |
469 | void pci_bus_irqs_cleanup(PCIBus *bus) |
470 | { |
471 | bus->set_irq = NULL; |
472 | bus->map_irq = NULL; |
473 | bus->irq_opaque = NULL; |
474 | bus->nirq = 0; |
475 | g_free(bus->irq_count); |
476 | } |
477 | |
478 | PCIBus *pci_register_root_bus(DeviceState *parent, const char *name, |
479 | pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
480 | void *irq_opaque, |
481 | MemoryRegion *address_space_mem, |
482 | MemoryRegion *address_space_io, |
483 | uint8_t devfn_min, int nirq, |
484 | const char *typename) |
485 | { |
486 | PCIBus *bus; |
487 | |
488 | bus = pci_root_bus_new(parent, name, address_space_mem, |
489 | address_space_io, devfn_min, typename); |
490 | pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq); |
491 | return bus; |
492 | } |
493 | |
494 | void pci_unregister_root_bus(PCIBus *bus) |
495 | { |
496 | pci_bus_irqs_cleanup(bus); |
497 | pci_root_bus_cleanup(bus); |
498 | } |
499 | |
500 | int pci_bus_num(PCIBus *s) |
501 | { |
502 | return PCI_BUS_GET_CLASS(s)->bus_num(s); |
503 | } |
504 | |
505 | int pci_bus_numa_node(PCIBus *bus) |
506 | { |
507 | return PCI_BUS_GET_CLASS(bus)->numa_node(bus); |
508 | } |
509 | |
510 | static int get_pci_config_device(QEMUFile *f, void *pv, size_t size, |
511 | const VMStateField *field) |
512 | { |
513 | PCIDevice *s = container_of(pv, PCIDevice, config); |
514 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(s); |
515 | uint8_t *config; |
516 | int i; |
517 | |
518 | assert(size == pci_config_size(s)); |
519 | config = g_malloc(size); |
520 | |
521 | qemu_get_buffer(f, config, size); |
522 | for (i = 0; i < size; ++i) { |
523 | if ((config[i] ^ s->config[i]) & |
524 | s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) { |
525 | error_report("%s: Bad config data: i=0x%x read: %x device: %x " |
526 | "cmask: %x wmask: %x w1cmask:%x" , __func__, |
527 | i, config[i], s->config[i], |
528 | s->cmask[i], s->wmask[i], s->w1cmask[i]); |
529 | g_free(config); |
530 | return -EINVAL; |
531 | } |
532 | } |
533 | memcpy(s->config, config, size); |
534 | |
535 | pci_update_mappings(s); |
536 | if (pc->is_bridge) { |
537 | PCIBridge *b = PCI_BRIDGE(s); |
538 | pci_bridge_update_mappings(b); |
539 | } |
540 | |
541 | memory_region_set_enabled(&s->bus_master_enable_region, |
542 | pci_get_word(s->config + PCI_COMMAND) |
543 | & PCI_COMMAND_MASTER); |
544 | |
545 | g_free(config); |
546 | return 0; |
547 | } |
548 | |
549 | /* just put buffer */ |
550 | static int put_pci_config_device(QEMUFile *f, void *pv, size_t size, |
551 | const VMStateField *field, QJSON *vmdesc) |
552 | { |
553 | const uint8_t **v = pv; |
554 | assert(size == pci_config_size(container_of(pv, PCIDevice, config))); |
555 | qemu_put_buffer(f, *v, size); |
556 | |
557 | return 0; |
558 | } |
559 | |
560 | static VMStateInfo vmstate_info_pci_config = { |
561 | .name = "pci config" , |
562 | .get = get_pci_config_device, |
563 | .put = put_pci_config_device, |
564 | }; |
565 | |
566 | static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size, |
567 | const VMStateField *field) |
568 | { |
569 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
570 | uint32_t irq_state[PCI_NUM_PINS]; |
571 | int i; |
572 | for (i = 0; i < PCI_NUM_PINS; ++i) { |
573 | irq_state[i] = qemu_get_be32(f); |
574 | if (irq_state[i] != 0x1 && irq_state[i] != 0) { |
575 | fprintf(stderr, "irq state %d: must be 0 or 1.\n" , |
576 | irq_state[i]); |
577 | return -EINVAL; |
578 | } |
579 | } |
580 | |
581 | for (i = 0; i < PCI_NUM_PINS; ++i) { |
582 | pci_set_irq_state(s, i, irq_state[i]); |
583 | } |
584 | |
585 | return 0; |
586 | } |
587 | |
588 | static int put_pci_irq_state(QEMUFile *f, void *pv, size_t size, |
589 | const VMStateField *field, QJSON *vmdesc) |
590 | { |
591 | int i; |
592 | PCIDevice *s = container_of(pv, PCIDevice, irq_state); |
593 | |
594 | for (i = 0; i < PCI_NUM_PINS; ++i) { |
595 | qemu_put_be32(f, pci_irq_state(s, i)); |
596 | } |
597 | |
598 | return 0; |
599 | } |
600 | |
601 | static VMStateInfo vmstate_info_pci_irq_state = { |
602 | .name = "pci irq state" , |
603 | .get = get_pci_irq_state, |
604 | .put = put_pci_irq_state, |
605 | }; |
606 | |
607 | static bool migrate_is_pcie(void *opaque, int version_id) |
608 | { |
609 | return pci_is_express((PCIDevice *)opaque); |
610 | } |
611 | |
612 | static bool migrate_is_not_pcie(void *opaque, int version_id) |
613 | { |
614 | return !pci_is_express((PCIDevice *)opaque); |
615 | } |
616 | |
617 | const VMStateDescription vmstate_pci_device = { |
618 | .name = "PCIDevice" , |
619 | .version_id = 2, |
620 | .minimum_version_id = 1, |
621 | .fields = (VMStateField[]) { |
622 | VMSTATE_INT32_POSITIVE_LE(version_id, PCIDevice), |
623 | VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, |
624 | migrate_is_not_pcie, |
625 | 0, vmstate_info_pci_config, |
626 | PCI_CONFIG_SPACE_SIZE), |
627 | VMSTATE_BUFFER_UNSAFE_INFO_TEST(config, PCIDevice, |
628 | migrate_is_pcie, |
629 | 0, vmstate_info_pci_config, |
630 | PCIE_CONFIG_SPACE_SIZE), |
631 | VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2, |
632 | vmstate_info_pci_irq_state, |
633 | PCI_NUM_PINS * sizeof(int32_t)), |
634 | VMSTATE_END_OF_LIST() |
635 | } |
636 | }; |
637 | |
638 | |
639 | void pci_device_save(PCIDevice *s, QEMUFile *f) |
640 | { |
641 | /* Clear interrupt status bit: it is implicit |
642 | * in irq_state which we are saving. |
643 | * This makes us compatible with old devices |
644 | * which never set or clear this bit. */ |
645 | s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT; |
646 | vmstate_save_state(f, &vmstate_pci_device, s, NULL); |
647 | /* Restore the interrupt status bit. */ |
648 | pci_update_irq_status(s); |
649 | } |
650 | |
651 | int pci_device_load(PCIDevice *s, QEMUFile *f) |
652 | { |
653 | int ret; |
654 | ret = vmstate_load_state(f, &vmstate_pci_device, s, s->version_id); |
655 | /* Restore the interrupt status bit. */ |
656 | pci_update_irq_status(s); |
657 | return ret; |
658 | } |
659 | |
660 | static void pci_set_default_subsystem_id(PCIDevice *pci_dev) |
661 | { |
662 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
663 | pci_default_sub_vendor_id); |
664 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
665 | pci_default_sub_device_id); |
666 | } |
667 | |
668 | /* |
669 | * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL |
670 | * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error |
671 | */ |
672 | static int pci_parse_devaddr(const char *addr, int *domp, int *busp, |
673 | unsigned int *slotp, unsigned int *funcp) |
674 | { |
675 | const char *p; |
676 | char *e; |
677 | unsigned long val; |
678 | unsigned long dom = 0, bus = 0; |
679 | unsigned int slot = 0; |
680 | unsigned int func = 0; |
681 | |
682 | p = addr; |
683 | val = strtoul(p, &e, 16); |
684 | if (e == p) |
685 | return -1; |
686 | if (*e == ':') { |
687 | bus = val; |
688 | p = e + 1; |
689 | val = strtoul(p, &e, 16); |
690 | if (e == p) |
691 | return -1; |
692 | if (*e == ':') { |
693 | dom = bus; |
694 | bus = val; |
695 | p = e + 1; |
696 | val = strtoul(p, &e, 16); |
697 | if (e == p) |
698 | return -1; |
699 | } |
700 | } |
701 | |
702 | slot = val; |
703 | |
704 | if (funcp != NULL) { |
705 | if (*e != '.') |
706 | return -1; |
707 | |
708 | p = e + 1; |
709 | val = strtoul(p, &e, 16); |
710 | if (e == p) |
711 | return -1; |
712 | |
713 | func = val; |
714 | } |
715 | |
716 | /* if funcp == NULL func is 0 */ |
717 | if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7) |
718 | return -1; |
719 | |
720 | if (*e) |
721 | return -1; |
722 | |
723 | *domp = dom; |
724 | *busp = bus; |
725 | *slotp = slot; |
726 | if (funcp != NULL) |
727 | *funcp = func; |
728 | return 0; |
729 | } |
730 | |
731 | static void pci_init_cmask(PCIDevice *dev) |
732 | { |
733 | pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff); |
734 | pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff); |
735 | dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST; |
736 | dev->cmask[PCI_REVISION_ID] = 0xff; |
737 | dev->cmask[PCI_CLASS_PROG] = 0xff; |
738 | pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff); |
739 | dev->cmask[PCI_HEADER_TYPE] = 0xff; |
740 | dev->cmask[PCI_CAPABILITY_LIST] = 0xff; |
741 | } |
742 | |
743 | static void pci_init_wmask(PCIDevice *dev) |
744 | { |
745 | int config_size = pci_config_size(dev); |
746 | |
747 | dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; |
748 | dev->wmask[PCI_INTERRUPT_LINE] = 0xff; |
749 | pci_set_word(dev->wmask + PCI_COMMAND, |
750 | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | |
751 | PCI_COMMAND_INTX_DISABLE); |
752 | if (dev->cap_present & QEMU_PCI_CAP_SERR) { |
753 | pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR); |
754 | } |
755 | |
756 | memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, |
757 | config_size - PCI_CONFIG_HEADER_SIZE); |
758 | } |
759 | |
760 | static void pci_init_w1cmask(PCIDevice *dev) |
761 | { |
762 | /* |
763 | * Note: It's okay to set w1cmask even for readonly bits as |
764 | * long as their value is hardwired to 0. |
765 | */ |
766 | pci_set_word(dev->w1cmask + PCI_STATUS, |
767 | PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT | |
768 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT | |
769 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY); |
770 | } |
771 | |
772 | static void pci_init_mask_bridge(PCIDevice *d) |
773 | { |
774 | /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and |
775 | PCI_SEC_LETENCY_TIMER */ |
776 | memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4); |
777 | |
778 | /* base and limit */ |
779 | d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff; |
780 | d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff; |
781 | pci_set_word(d->wmask + PCI_MEMORY_BASE, |
782 | PCI_MEMORY_RANGE_MASK & 0xffff); |
783 | pci_set_word(d->wmask + PCI_MEMORY_LIMIT, |
784 | PCI_MEMORY_RANGE_MASK & 0xffff); |
785 | pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE, |
786 | PCI_PREF_RANGE_MASK & 0xffff); |
787 | pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT, |
788 | PCI_PREF_RANGE_MASK & 0xffff); |
789 | |
790 | /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */ |
791 | memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8); |
792 | |
793 | /* Supported memory and i/o types */ |
794 | d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16; |
795 | d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16; |
796 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE, |
797 | PCI_PREF_RANGE_TYPE_64); |
798 | pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT, |
799 | PCI_PREF_RANGE_TYPE_64); |
800 | |
801 | /* |
802 | * TODO: Bridges default to 10-bit VGA decoding but we currently only |
803 | * implement 16-bit decoding (no alias support). |
804 | */ |
805 | pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, |
806 | PCI_BRIDGE_CTL_PARITY | |
807 | PCI_BRIDGE_CTL_SERR | |
808 | PCI_BRIDGE_CTL_ISA | |
809 | PCI_BRIDGE_CTL_VGA | |
810 | PCI_BRIDGE_CTL_VGA_16BIT | |
811 | PCI_BRIDGE_CTL_MASTER_ABORT | |
812 | PCI_BRIDGE_CTL_BUS_RESET | |
813 | PCI_BRIDGE_CTL_FAST_BACK | |
814 | PCI_BRIDGE_CTL_DISCARD | |
815 | PCI_BRIDGE_CTL_SEC_DISCARD | |
816 | PCI_BRIDGE_CTL_DISCARD_SERR); |
817 | /* Below does not do anything as we never set this bit, put here for |
818 | * completeness. */ |
819 | pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL, |
820 | PCI_BRIDGE_CTL_DISCARD_STATUS); |
821 | d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK; |
822 | d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK; |
823 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE, |
824 | PCI_PREF_RANGE_TYPE_MASK); |
825 | pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT, |
826 | PCI_PREF_RANGE_TYPE_MASK); |
827 | } |
828 | |
829 | static void pci_init_multifunction(PCIBus *bus, PCIDevice *dev, Error **errp) |
830 | { |
831 | uint8_t slot = PCI_SLOT(dev->devfn); |
832 | uint8_t func; |
833 | |
834 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { |
835 | dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; |
836 | } |
837 | |
838 | /* |
839 | * multifunction bit is interpreted in two ways as follows. |
840 | * - all functions must set the bit to 1. |
841 | * Example: Intel X53 |
842 | * - function 0 must set the bit, but the rest function (> 0) |
843 | * is allowed to leave the bit to 0. |
844 | * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10, |
845 | * |
846 | * So OS (at least Linux) checks the bit of only function 0, |
847 | * and doesn't see the bit of function > 0. |
848 | * |
849 | * The below check allows both interpretation. |
850 | */ |
851 | if (PCI_FUNC(dev->devfn)) { |
852 | PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)]; |
853 | if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) { |
854 | /* function 0 should set multifunction bit */ |
855 | error_setg(errp, "PCI: single function device can't be populated " |
856 | "in function %x.%x" , slot, PCI_FUNC(dev->devfn)); |
857 | return; |
858 | } |
859 | return; |
860 | } |
861 | |
862 | if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) { |
863 | return; |
864 | } |
865 | /* function 0 indicates single function, so function > 0 must be NULL */ |
866 | for (func = 1; func < PCI_FUNC_MAX; ++func) { |
867 | if (bus->devices[PCI_DEVFN(slot, func)]) { |
868 | error_setg(errp, "PCI: %x.0 indicates single function, " |
869 | "but %x.%x is already populated." , |
870 | slot, slot, func); |
871 | return; |
872 | } |
873 | } |
874 | } |
875 | |
876 | static void pci_config_alloc(PCIDevice *pci_dev) |
877 | { |
878 | int config_size = pci_config_size(pci_dev); |
879 | |
880 | pci_dev->config = g_malloc0(config_size); |
881 | pci_dev->cmask = g_malloc0(config_size); |
882 | pci_dev->wmask = g_malloc0(config_size); |
883 | pci_dev->w1cmask = g_malloc0(config_size); |
884 | pci_dev->used = g_malloc0(config_size); |
885 | } |
886 | |
887 | static void pci_config_free(PCIDevice *pci_dev) |
888 | { |
889 | g_free(pci_dev->config); |
890 | g_free(pci_dev->cmask); |
891 | g_free(pci_dev->wmask); |
892 | g_free(pci_dev->w1cmask); |
893 | g_free(pci_dev->used); |
894 | } |
895 | |
896 | static void do_pci_unregister_device(PCIDevice *pci_dev) |
897 | { |
898 | pci_get_bus(pci_dev)->devices[pci_dev->devfn] = NULL; |
899 | pci_config_free(pci_dev); |
900 | |
901 | if (memory_region_is_mapped(&pci_dev->bus_master_enable_region)) { |
902 | memory_region_del_subregion(&pci_dev->bus_master_container_region, |
903 | &pci_dev->bus_master_enable_region); |
904 | } |
905 | address_space_destroy(&pci_dev->bus_master_as); |
906 | } |
907 | |
908 | /* Extract PCIReqIDCache into BDF format */ |
909 | static uint16_t (PCIReqIDCache *cache) |
910 | { |
911 | uint8_t bus_n; |
912 | uint16_t result; |
913 | |
914 | switch (cache->type) { |
915 | case PCI_REQ_ID_BDF: |
916 | result = pci_get_bdf(cache->dev); |
917 | break; |
918 | case PCI_REQ_ID_SECONDARY_BUS: |
919 | bus_n = pci_dev_bus_num(cache->dev); |
920 | result = PCI_BUILD_BDF(bus_n, 0); |
921 | break; |
922 | default: |
923 | error_report("Invalid PCI requester ID cache type: %d" , |
924 | cache->type); |
925 | exit(1); |
926 | break; |
927 | } |
928 | |
929 | return result; |
930 | } |
931 | |
932 | /* Parse bridges up to the root complex and return requester ID |
933 | * cache for specific device. For full PCIe topology, the cache |
934 | * result would be exactly the same as getting BDF of the device. |
935 | * However, several tricks are required when system mixed up with |
936 | * legacy PCI devices and PCIe-to-PCI bridges. |
937 | * |
938 | * Here we cache the proxy device (and type) not requester ID since |
939 | * bus number might change from time to time. |
940 | */ |
941 | static PCIReqIDCache pci_req_id_cache_get(PCIDevice *dev) |
942 | { |
943 | PCIDevice *parent; |
944 | PCIReqIDCache cache = { |
945 | .dev = dev, |
946 | .type = PCI_REQ_ID_BDF, |
947 | }; |
948 | |
949 | while (!pci_bus_is_root(pci_get_bus(dev))) { |
950 | /* We are under PCI/PCIe bridges */ |
951 | parent = pci_get_bus(dev)->parent_dev; |
952 | if (pci_is_express(parent)) { |
953 | if (pcie_cap_get_type(parent) == PCI_EXP_TYPE_PCI_BRIDGE) { |
954 | /* When we pass through PCIe-to-PCI/PCIX bridges, we |
955 | * override the requester ID using secondary bus |
956 | * number of parent bridge with zeroed devfn |
957 | * (pcie-to-pci bridge spec chap 2.3). */ |
958 | cache.type = PCI_REQ_ID_SECONDARY_BUS; |
959 | cache.dev = dev; |
960 | } |
961 | } else { |
962 | /* Legacy PCI, override requester ID with the bridge's |
963 | * BDF upstream. When the root complex connects to |
964 | * legacy PCI devices (including buses), it can only |
965 | * obtain requester ID info from directly attached |
966 | * devices. If devices are attached under bridges, only |
967 | * the requester ID of the bridge that is directly |
968 | * attached to the root complex can be recognized. */ |
969 | cache.type = PCI_REQ_ID_BDF; |
970 | cache.dev = parent; |
971 | } |
972 | dev = parent; |
973 | } |
974 | |
975 | return cache; |
976 | } |
977 | |
978 | uint16_t pci_requester_id(PCIDevice *dev) |
979 | { |
980 | return pci_req_id_cache_extract(&dev->requester_id_cache); |
981 | } |
982 | |
983 | static bool pci_bus_devfn_available(PCIBus *bus, int devfn) |
984 | { |
985 | return !(bus->devices[devfn]); |
986 | } |
987 | |
988 | static bool pci_bus_devfn_reserved(PCIBus *bus, int devfn) |
989 | { |
990 | return bus->slot_reserved_mask & (1UL << PCI_SLOT(devfn)); |
991 | } |
992 | |
993 | /* -1 for devfn means auto assign */ |
994 | static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, |
995 | const char *name, int devfn, |
996 | Error **errp) |
997 | { |
998 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
999 | PCIConfigReadFunc *config_read = pc->config_read; |
1000 | PCIConfigWriteFunc *config_write = pc->config_write; |
1001 | Error *local_err = NULL; |
1002 | DeviceState *dev = DEVICE(pci_dev); |
1003 | PCIBus *bus = pci_get_bus(pci_dev); |
1004 | |
1005 | /* Only pci bridges can be attached to extra PCI root buses */ |
1006 | if (pci_bus_is_root(bus) && bus->parent_dev && !pc->is_bridge) { |
1007 | error_setg(errp, |
1008 | "PCI: Only PCI/PCIe bridges can be plugged into %s" , |
1009 | bus->parent_dev->name); |
1010 | return NULL; |
1011 | } |
1012 | |
1013 | if (devfn < 0) { |
1014 | for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices); |
1015 | devfn += PCI_FUNC_MAX) { |
1016 | if (pci_bus_devfn_available(bus, devfn) && |
1017 | !pci_bus_devfn_reserved(bus, devfn)) { |
1018 | goto found; |
1019 | } |
1020 | } |
1021 | error_setg(errp, "PCI: no slot/function available for %s, all in use " |
1022 | "or reserved" , name); |
1023 | return NULL; |
1024 | found: ; |
1025 | } else if (pci_bus_devfn_reserved(bus, devfn)) { |
1026 | error_setg(errp, "PCI: slot %d function %d not available for %s," |
1027 | " reserved" , |
1028 | PCI_SLOT(devfn), PCI_FUNC(devfn), name); |
1029 | return NULL; |
1030 | } else if (!pci_bus_devfn_available(bus, devfn)) { |
1031 | error_setg(errp, "PCI: slot %d function %d not available for %s," |
1032 | " in use by %s" , |
1033 | PCI_SLOT(devfn), PCI_FUNC(devfn), name, |
1034 | bus->devices[devfn]->name); |
1035 | return NULL; |
1036 | } else if (dev->hotplugged && |
1037 | pci_get_function_0(pci_dev)) { |
1038 | error_setg(errp, "PCI: slot %d function 0 already ocuppied by %s," |
1039 | " new func %s cannot be exposed to guest." , |
1040 | PCI_SLOT(pci_get_function_0(pci_dev)->devfn), |
1041 | pci_get_function_0(pci_dev)->name, |
1042 | name); |
1043 | |
1044 | return NULL; |
1045 | } |
1046 | |
1047 | pci_dev->devfn = devfn; |
1048 | pci_dev->requester_id_cache = pci_req_id_cache_get(pci_dev); |
1049 | pstrcpy(pci_dev->name, sizeof(pci_dev->name), name); |
1050 | |
1051 | memory_region_init(&pci_dev->bus_master_container_region, OBJECT(pci_dev), |
1052 | "bus master container" , UINT64_MAX); |
1053 | address_space_init(&pci_dev->bus_master_as, |
1054 | &pci_dev->bus_master_container_region, pci_dev->name); |
1055 | |
1056 | if (qdev_hotplug) { |
1057 | pci_init_bus_master(pci_dev); |
1058 | } |
1059 | pci_dev->irq_state = 0; |
1060 | pci_config_alloc(pci_dev); |
1061 | |
1062 | pci_config_set_vendor_id(pci_dev->config, pc->vendor_id); |
1063 | pci_config_set_device_id(pci_dev->config, pc->device_id); |
1064 | pci_config_set_revision(pci_dev->config, pc->revision); |
1065 | pci_config_set_class(pci_dev->config, pc->class_id); |
1066 | |
1067 | if (!pc->is_bridge) { |
1068 | if (pc->subsystem_vendor_id || pc->subsystem_id) { |
1069 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID, |
1070 | pc->subsystem_vendor_id); |
1071 | pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID, |
1072 | pc->subsystem_id); |
1073 | } else { |
1074 | pci_set_default_subsystem_id(pci_dev); |
1075 | } |
1076 | } else { |
1077 | /* subsystem_vendor_id/subsystem_id are only for header type 0 */ |
1078 | assert(!pc->subsystem_vendor_id); |
1079 | assert(!pc->subsystem_id); |
1080 | } |
1081 | pci_init_cmask(pci_dev); |
1082 | pci_init_wmask(pci_dev); |
1083 | pci_init_w1cmask(pci_dev); |
1084 | if (pc->is_bridge) { |
1085 | pci_init_mask_bridge(pci_dev); |
1086 | } |
1087 | pci_init_multifunction(bus, pci_dev, &local_err); |
1088 | if (local_err) { |
1089 | error_propagate(errp, local_err); |
1090 | do_pci_unregister_device(pci_dev); |
1091 | return NULL; |
1092 | } |
1093 | |
1094 | if (!config_read) |
1095 | config_read = pci_default_read_config; |
1096 | if (!config_write) |
1097 | config_write = pci_default_write_config; |
1098 | pci_dev->config_read = config_read; |
1099 | pci_dev->config_write = config_write; |
1100 | bus->devices[devfn] = pci_dev; |
1101 | pci_dev->version_id = 2; /* Current pci device vmstate version */ |
1102 | return pci_dev; |
1103 | } |
1104 | |
1105 | static void pci_unregister_io_regions(PCIDevice *pci_dev) |
1106 | { |
1107 | PCIIORegion *r; |
1108 | int i; |
1109 | |
1110 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1111 | r = &pci_dev->io_regions[i]; |
1112 | if (!r->size || r->addr == PCI_BAR_UNMAPPED) |
1113 | continue; |
1114 | memory_region_del_subregion(r->address_space, r->memory); |
1115 | } |
1116 | |
1117 | pci_unregister_vga(pci_dev); |
1118 | } |
1119 | |
1120 | static void pci_qdev_unrealize(DeviceState *dev, Error **errp) |
1121 | { |
1122 | PCIDevice *pci_dev = PCI_DEVICE(dev); |
1123 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
1124 | |
1125 | pci_unregister_io_regions(pci_dev); |
1126 | pci_del_option_rom(pci_dev); |
1127 | |
1128 | if (pc->exit) { |
1129 | pc->exit(pci_dev); |
1130 | } |
1131 | |
1132 | pci_device_deassert_intx(pci_dev); |
1133 | do_pci_unregister_device(pci_dev); |
1134 | } |
1135 | |
1136 | void pci_register_bar(PCIDevice *pci_dev, int region_num, |
1137 | uint8_t type, MemoryRegion *memory) |
1138 | { |
1139 | PCIIORegion *r; |
1140 | uint32_t addr; /* offset in pci config space */ |
1141 | uint64_t wmask; |
1142 | pcibus_t size = memory_region_size(memory); |
1143 | |
1144 | assert(region_num >= 0); |
1145 | assert(region_num < PCI_NUM_REGIONS); |
1146 | if (size & (size-1)) { |
1147 | error_report("ERROR: PCI region size must be pow2 " |
1148 | "type=0x%x, size=0x%" FMT_PCIBUS"" , type, size); |
1149 | exit(1); |
1150 | } |
1151 | |
1152 | r = &pci_dev->io_regions[region_num]; |
1153 | r->addr = PCI_BAR_UNMAPPED; |
1154 | r->size = size; |
1155 | r->type = type; |
1156 | r->memory = memory; |
1157 | r->address_space = type & PCI_BASE_ADDRESS_SPACE_IO |
1158 | ? pci_get_bus(pci_dev)->address_space_io |
1159 | : pci_get_bus(pci_dev)->address_space_mem; |
1160 | |
1161 | wmask = ~(size - 1); |
1162 | if (region_num == PCI_ROM_SLOT) { |
1163 | /* ROM enable bit is writable */ |
1164 | wmask |= PCI_ROM_ADDRESS_ENABLE; |
1165 | } |
1166 | |
1167 | addr = pci_bar(pci_dev, region_num); |
1168 | pci_set_long(pci_dev->config + addr, type); |
1169 | |
1170 | if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) && |
1171 | r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
1172 | pci_set_quad(pci_dev->wmask + addr, wmask); |
1173 | pci_set_quad(pci_dev->cmask + addr, ~0ULL); |
1174 | } else { |
1175 | pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff); |
1176 | pci_set_long(pci_dev->cmask + addr, 0xffffffff); |
1177 | } |
1178 | } |
1179 | |
1180 | static void pci_update_vga(PCIDevice *pci_dev) |
1181 | { |
1182 | uint16_t cmd; |
1183 | |
1184 | if (!pci_dev->has_vga) { |
1185 | return; |
1186 | } |
1187 | |
1188 | cmd = pci_get_word(pci_dev->config + PCI_COMMAND); |
1189 | |
1190 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_MEM], |
1191 | cmd & PCI_COMMAND_MEMORY); |
1192 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO], |
1193 | cmd & PCI_COMMAND_IO); |
1194 | memory_region_set_enabled(pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI], |
1195 | cmd & PCI_COMMAND_IO); |
1196 | } |
1197 | |
1198 | void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem, |
1199 | MemoryRegion *io_lo, MemoryRegion *io_hi) |
1200 | { |
1201 | PCIBus *bus = pci_get_bus(pci_dev); |
1202 | |
1203 | assert(!pci_dev->has_vga); |
1204 | |
1205 | assert(memory_region_size(mem) == QEMU_PCI_VGA_MEM_SIZE); |
1206 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM] = mem; |
1207 | memory_region_add_subregion_overlap(bus->address_space_mem, |
1208 | QEMU_PCI_VGA_MEM_BASE, mem, 1); |
1209 | |
1210 | assert(memory_region_size(io_lo) == QEMU_PCI_VGA_IO_LO_SIZE); |
1211 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO] = io_lo; |
1212 | memory_region_add_subregion_overlap(bus->address_space_io, |
1213 | QEMU_PCI_VGA_IO_LO_BASE, io_lo, 1); |
1214 | |
1215 | assert(memory_region_size(io_hi) == QEMU_PCI_VGA_IO_HI_SIZE); |
1216 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI] = io_hi; |
1217 | memory_region_add_subregion_overlap(bus->address_space_io, |
1218 | QEMU_PCI_VGA_IO_HI_BASE, io_hi, 1); |
1219 | pci_dev->has_vga = true; |
1220 | |
1221 | pci_update_vga(pci_dev); |
1222 | } |
1223 | |
1224 | void pci_unregister_vga(PCIDevice *pci_dev) |
1225 | { |
1226 | PCIBus *bus = pci_get_bus(pci_dev); |
1227 | |
1228 | if (!pci_dev->has_vga) { |
1229 | return; |
1230 | } |
1231 | |
1232 | memory_region_del_subregion(bus->address_space_mem, |
1233 | pci_dev->vga_regions[QEMU_PCI_VGA_MEM]); |
1234 | memory_region_del_subregion(bus->address_space_io, |
1235 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_LO]); |
1236 | memory_region_del_subregion(bus->address_space_io, |
1237 | pci_dev->vga_regions[QEMU_PCI_VGA_IO_HI]); |
1238 | pci_dev->has_vga = false; |
1239 | } |
1240 | |
1241 | pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num) |
1242 | { |
1243 | return pci_dev->io_regions[region_num].addr; |
1244 | } |
1245 | |
1246 | static pcibus_t pci_bar_address(PCIDevice *d, |
1247 | int reg, uint8_t type, pcibus_t size) |
1248 | { |
1249 | pcibus_t new_addr, last_addr; |
1250 | int bar = pci_bar(d, reg); |
1251 | uint16_t cmd = pci_get_word(d->config + PCI_COMMAND); |
1252 | Object *machine = qdev_get_machine(); |
1253 | ObjectClass *oc = object_get_class(machine); |
1254 | MachineClass *mc = MACHINE_CLASS(oc); |
1255 | bool allow_0_address = mc->pci_allow_0_address; |
1256 | |
1257 | if (type & PCI_BASE_ADDRESS_SPACE_IO) { |
1258 | if (!(cmd & PCI_COMMAND_IO)) { |
1259 | return PCI_BAR_UNMAPPED; |
1260 | } |
1261 | new_addr = pci_get_long(d->config + bar) & ~(size - 1); |
1262 | last_addr = new_addr + size - 1; |
1263 | /* Check if 32 bit BAR wraps around explicitly. |
1264 | * TODO: make priorities correct and remove this work around. |
1265 | */ |
1266 | if (last_addr <= new_addr || last_addr >= UINT32_MAX || |
1267 | (!allow_0_address && new_addr == 0)) { |
1268 | return PCI_BAR_UNMAPPED; |
1269 | } |
1270 | return new_addr; |
1271 | } |
1272 | |
1273 | if (!(cmd & PCI_COMMAND_MEMORY)) { |
1274 | return PCI_BAR_UNMAPPED; |
1275 | } |
1276 | if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) { |
1277 | new_addr = pci_get_quad(d->config + bar); |
1278 | } else { |
1279 | new_addr = pci_get_long(d->config + bar); |
1280 | } |
1281 | /* the ROM slot has a specific enable bit */ |
1282 | if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) { |
1283 | return PCI_BAR_UNMAPPED; |
1284 | } |
1285 | new_addr &= ~(size - 1); |
1286 | last_addr = new_addr + size - 1; |
1287 | /* NOTE: we do not support wrapping */ |
1288 | /* XXX: as we cannot support really dynamic |
1289 | mappings, we handle specific values as invalid |
1290 | mappings. */ |
1291 | if (last_addr <= new_addr || last_addr == PCI_BAR_UNMAPPED || |
1292 | (!allow_0_address && new_addr == 0)) { |
1293 | return PCI_BAR_UNMAPPED; |
1294 | } |
1295 | |
1296 | /* Now pcibus_t is 64bit. |
1297 | * Check if 32 bit BAR wraps around explicitly. |
1298 | * Without this, PC ide doesn't work well. |
1299 | * TODO: remove this work around. |
1300 | */ |
1301 | if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) { |
1302 | return PCI_BAR_UNMAPPED; |
1303 | } |
1304 | |
1305 | /* |
1306 | * OS is allowed to set BAR beyond its addressable |
1307 | * bits. For example, 32 bit OS can set 64bit bar |
1308 | * to >4G. Check it. TODO: we might need to support |
1309 | * it in the future for e.g. PAE. |
1310 | */ |
1311 | if (last_addr >= HWADDR_MAX) { |
1312 | return PCI_BAR_UNMAPPED; |
1313 | } |
1314 | |
1315 | return new_addr; |
1316 | } |
1317 | |
1318 | static void pci_update_mappings(PCIDevice *d) |
1319 | { |
1320 | PCIIORegion *r; |
1321 | int i; |
1322 | pcibus_t new_addr; |
1323 | |
1324 | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
1325 | r = &d->io_regions[i]; |
1326 | |
1327 | /* this region isn't registered */ |
1328 | if (!r->size) |
1329 | continue; |
1330 | |
1331 | new_addr = pci_bar_address(d, i, r->type, r->size); |
1332 | |
1333 | /* This bar isn't changed */ |
1334 | if (new_addr == r->addr) |
1335 | continue; |
1336 | |
1337 | /* now do the real mapping */ |
1338 | if (r->addr != PCI_BAR_UNMAPPED) { |
1339 | trace_pci_update_mappings_del(d, pci_dev_bus_num(d), |
1340 | PCI_SLOT(d->devfn), |
1341 | PCI_FUNC(d->devfn), |
1342 | i, r->addr, r->size); |
1343 | memory_region_del_subregion(r->address_space, r->memory); |
1344 | } |
1345 | r->addr = new_addr; |
1346 | if (r->addr != PCI_BAR_UNMAPPED) { |
1347 | trace_pci_update_mappings_add(d, pci_dev_bus_num(d), |
1348 | PCI_SLOT(d->devfn), |
1349 | PCI_FUNC(d->devfn), |
1350 | i, r->addr, r->size); |
1351 | memory_region_add_subregion_overlap(r->address_space, |
1352 | r->addr, r->memory, 1); |
1353 | } |
1354 | } |
1355 | |
1356 | pci_update_vga(d); |
1357 | } |
1358 | |
1359 | static inline int pci_irq_disabled(PCIDevice *d) |
1360 | { |
1361 | return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE; |
1362 | } |
1363 | |
1364 | /* Called after interrupt disabled field update in config space, |
1365 | * assert/deassert interrupts if necessary. |
1366 | * Gets original interrupt disable bit value (before update). */ |
1367 | static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled) |
1368 | { |
1369 | int i, disabled = pci_irq_disabled(d); |
1370 | if (disabled == was_irq_disabled) |
1371 | return; |
1372 | for (i = 0; i < PCI_NUM_PINS; ++i) { |
1373 | int state = pci_irq_state(d, i); |
1374 | pci_change_irq_level(d, i, disabled ? -state : state); |
1375 | } |
1376 | } |
1377 | |
1378 | uint32_t pci_default_read_config(PCIDevice *d, |
1379 | uint32_t address, int len) |
1380 | { |
1381 | uint32_t val = 0; |
1382 | |
1383 | if (pci_is_express_downstream_port(d) && |
1384 | ranges_overlap(address, len, d->exp.exp_cap + PCI_EXP_LNKSTA, 2)) { |
1385 | pcie_sync_bridge_lnk(d); |
1386 | } |
1387 | memcpy(&val, d->config + address, len); |
1388 | return le32_to_cpu(val); |
1389 | } |
1390 | |
1391 | void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val_in, int l) |
1392 | { |
1393 | int i, was_irq_disabled = pci_irq_disabled(d); |
1394 | uint32_t val = val_in; |
1395 | |
1396 | for (i = 0; i < l; val >>= 8, ++i) { |
1397 | uint8_t wmask = d->wmask[addr + i]; |
1398 | uint8_t w1cmask = d->w1cmask[addr + i]; |
1399 | assert(!(wmask & w1cmask)); |
1400 | d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask); |
1401 | d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */ |
1402 | } |
1403 | if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) || |
1404 | ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) || |
1405 | ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) || |
1406 | range_covers_byte(addr, l, PCI_COMMAND)) |
1407 | pci_update_mappings(d); |
1408 | |
1409 | if (range_covers_byte(addr, l, PCI_COMMAND)) { |
1410 | pci_update_irq_disabled(d, was_irq_disabled); |
1411 | memory_region_set_enabled(&d->bus_master_enable_region, |
1412 | pci_get_word(d->config + PCI_COMMAND) |
1413 | & PCI_COMMAND_MASTER); |
1414 | } |
1415 | |
1416 | msi_write_config(d, addr, val_in, l); |
1417 | msix_write_config(d, addr, val_in, l); |
1418 | } |
1419 | |
1420 | /***********************************************************/ |
1421 | /* generic PCI irq support */ |
1422 | |
1423 | /* 0 <= irq_num <= 3. level must be 0 or 1 */ |
1424 | static void pci_irq_handler(void *opaque, int irq_num, int level) |
1425 | { |
1426 | PCIDevice *pci_dev = opaque; |
1427 | int change; |
1428 | |
1429 | change = level - pci_irq_state(pci_dev, irq_num); |
1430 | if (!change) |
1431 | return; |
1432 | |
1433 | pci_set_irq_state(pci_dev, irq_num, level); |
1434 | pci_update_irq_status(pci_dev); |
1435 | if (pci_irq_disabled(pci_dev)) |
1436 | return; |
1437 | pci_change_irq_level(pci_dev, irq_num, change); |
1438 | } |
1439 | |
1440 | static inline int pci_intx(PCIDevice *pci_dev) |
1441 | { |
1442 | return pci_get_byte(pci_dev->config + PCI_INTERRUPT_PIN) - 1; |
1443 | } |
1444 | |
1445 | qemu_irq pci_allocate_irq(PCIDevice *pci_dev) |
1446 | { |
1447 | int intx = pci_intx(pci_dev); |
1448 | |
1449 | return qemu_allocate_irq(pci_irq_handler, pci_dev, intx); |
1450 | } |
1451 | |
1452 | void pci_set_irq(PCIDevice *pci_dev, int level) |
1453 | { |
1454 | int intx = pci_intx(pci_dev); |
1455 | pci_irq_handler(pci_dev, intx, level); |
1456 | } |
1457 | |
1458 | /* Special hooks used by device assignment */ |
1459 | void pci_bus_set_route_irq_fn(PCIBus *bus, pci_route_irq_fn route_intx_to_irq) |
1460 | { |
1461 | assert(pci_bus_is_root(bus)); |
1462 | bus->route_intx_to_irq = route_intx_to_irq; |
1463 | } |
1464 | |
1465 | PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin) |
1466 | { |
1467 | PCIBus *bus; |
1468 | |
1469 | do { |
1470 | bus = pci_get_bus(dev); |
1471 | pin = bus->map_irq(dev, pin); |
1472 | dev = bus->parent_dev; |
1473 | } while (dev); |
1474 | |
1475 | if (!bus->route_intx_to_irq) { |
1476 | error_report("PCI: Bug - unimplemented PCI INTx routing (%s)" , |
1477 | object_get_typename(OBJECT(bus->qbus.parent))); |
1478 | return (PCIINTxRoute) { PCI_INTX_DISABLED, -1 }; |
1479 | } |
1480 | |
1481 | return bus->route_intx_to_irq(bus->irq_opaque, pin); |
1482 | } |
1483 | |
1484 | bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new) |
1485 | { |
1486 | return old->mode != new->mode || old->irq != new->irq; |
1487 | } |
1488 | |
1489 | void pci_bus_fire_intx_routing_notifier(PCIBus *bus) |
1490 | { |
1491 | PCIDevice *dev; |
1492 | PCIBus *sec; |
1493 | int i; |
1494 | |
1495 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
1496 | dev = bus->devices[i]; |
1497 | if (dev && dev->intx_routing_notifier) { |
1498 | dev->intx_routing_notifier(dev); |
1499 | } |
1500 | } |
1501 | |
1502 | QLIST_FOREACH(sec, &bus->child, sibling) { |
1503 | pci_bus_fire_intx_routing_notifier(sec); |
1504 | } |
1505 | } |
1506 | |
1507 | void pci_device_set_intx_routing_notifier(PCIDevice *dev, |
1508 | PCIINTxRoutingNotifier notifier) |
1509 | { |
1510 | dev->intx_routing_notifier = notifier; |
1511 | } |
1512 | |
1513 | /* |
1514 | * PCI-to-PCI bridge specification |
1515 | * 9.1: Interrupt routing. Table 9-1 |
1516 | * |
1517 | * the PCI Express Base Specification, Revision 2.1 |
1518 | * 2.2.8.1: INTx interrutp signaling - Rules |
1519 | * the Implementation Note |
1520 | * Table 2-20 |
1521 | */ |
1522 | /* |
1523 | * 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD |
1524 | * 0-origin unlike PCI interrupt pin register. |
1525 | */ |
1526 | int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin) |
1527 | { |
1528 | return pci_swizzle(PCI_SLOT(pci_dev->devfn), pin); |
1529 | } |
1530 | |
1531 | /***********************************************************/ |
1532 | /* monitor info on PCI */ |
1533 | |
1534 | typedef struct { |
1535 | uint16_t class; |
1536 | const char *desc; |
1537 | const char *fw_name; |
1538 | uint16_t fw_ign_bits; |
1539 | } pci_class_desc; |
1540 | |
1541 | static const pci_class_desc pci_class_descriptions[] = |
1542 | { |
1543 | { 0x0001, "VGA controller" , "display" }, |
1544 | { 0x0100, "SCSI controller" , "scsi" }, |
1545 | { 0x0101, "IDE controller" , "ide" }, |
1546 | { 0x0102, "Floppy controller" , "fdc" }, |
1547 | { 0x0103, "IPI controller" , "ipi" }, |
1548 | { 0x0104, "RAID controller" , "raid" }, |
1549 | { 0x0106, "SATA controller" }, |
1550 | { 0x0107, "SAS controller" }, |
1551 | { 0x0180, "Storage controller" }, |
1552 | { 0x0200, "Ethernet controller" , "ethernet" }, |
1553 | { 0x0201, "Token Ring controller" , "token-ring" }, |
1554 | { 0x0202, "FDDI controller" , "fddi" }, |
1555 | { 0x0203, "ATM controller" , "atm" }, |
1556 | { 0x0280, "Network controller" }, |
1557 | { 0x0300, "VGA controller" , "display" , 0x00ff}, |
1558 | { 0x0301, "XGA controller" }, |
1559 | { 0x0302, "3D controller" }, |
1560 | { 0x0380, "Display controller" }, |
1561 | { 0x0400, "Video controller" , "video" }, |
1562 | { 0x0401, "Audio controller" , "sound" }, |
1563 | { 0x0402, "Phone" }, |
1564 | { 0x0403, "Audio controller" , "sound" }, |
1565 | { 0x0480, "Multimedia controller" }, |
1566 | { 0x0500, "RAM controller" , "memory" }, |
1567 | { 0x0501, "Flash controller" , "flash" }, |
1568 | { 0x0580, "Memory controller" }, |
1569 | { 0x0600, "Host bridge" , "host" }, |
1570 | { 0x0601, "ISA bridge" , "isa" }, |
1571 | { 0x0602, "EISA bridge" , "eisa" }, |
1572 | { 0x0603, "MC bridge" , "mca" }, |
1573 | { 0x0604, "PCI bridge" , "pci-bridge" }, |
1574 | { 0x0605, "PCMCIA bridge" , "pcmcia" }, |
1575 | { 0x0606, "NUBUS bridge" , "nubus" }, |
1576 | { 0x0607, "CARDBUS bridge" , "cardbus" }, |
1577 | { 0x0608, "RACEWAY bridge" }, |
1578 | { 0x0680, "Bridge" }, |
1579 | { 0x0700, "Serial port" , "serial" }, |
1580 | { 0x0701, "Parallel port" , "parallel" }, |
1581 | { 0x0800, "Interrupt controller" , "interrupt-controller" }, |
1582 | { 0x0801, "DMA controller" , "dma-controller" }, |
1583 | { 0x0802, "Timer" , "timer" }, |
1584 | { 0x0803, "RTC" , "rtc" }, |
1585 | { 0x0900, "Keyboard" , "keyboard" }, |
1586 | { 0x0901, "Pen" , "pen" }, |
1587 | { 0x0902, "Mouse" , "mouse" }, |
1588 | { 0x0A00, "Dock station" , "dock" , 0x00ff}, |
1589 | { 0x0B00, "i386 cpu" , "cpu" , 0x00ff}, |
1590 | { 0x0c00, "Fireware contorller" , "fireware" }, |
1591 | { 0x0c01, "Access bus controller" , "access-bus" }, |
1592 | { 0x0c02, "SSA controller" , "ssa" }, |
1593 | { 0x0c03, "USB controller" , "usb" }, |
1594 | { 0x0c04, "Fibre channel controller" , "fibre-channel" }, |
1595 | { 0x0c05, "SMBus" }, |
1596 | { 0, NULL} |
1597 | }; |
1598 | |
1599 | static void pci_for_each_device_under_bus_reverse(PCIBus *bus, |
1600 | void (*fn)(PCIBus *b, |
1601 | PCIDevice *d, |
1602 | void *opaque), |
1603 | void *opaque) |
1604 | { |
1605 | PCIDevice *d; |
1606 | int devfn; |
1607 | |
1608 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1609 | d = bus->devices[ARRAY_SIZE(bus->devices) - 1 - devfn]; |
1610 | if (d) { |
1611 | fn(bus, d, opaque); |
1612 | } |
1613 | } |
1614 | } |
1615 | |
1616 | void pci_for_each_device_reverse(PCIBus *bus, int bus_num, |
1617 | void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1618 | void *opaque) |
1619 | { |
1620 | bus = pci_find_bus_nr(bus, bus_num); |
1621 | |
1622 | if (bus) { |
1623 | pci_for_each_device_under_bus_reverse(bus, fn, opaque); |
1624 | } |
1625 | } |
1626 | |
1627 | static void pci_for_each_device_under_bus(PCIBus *bus, |
1628 | void (*fn)(PCIBus *b, PCIDevice *d, |
1629 | void *opaque), |
1630 | void *opaque) |
1631 | { |
1632 | PCIDevice *d; |
1633 | int devfn; |
1634 | |
1635 | for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1636 | d = bus->devices[devfn]; |
1637 | if (d) { |
1638 | fn(bus, d, opaque); |
1639 | } |
1640 | } |
1641 | } |
1642 | |
1643 | void pci_for_each_device(PCIBus *bus, int bus_num, |
1644 | void (*fn)(PCIBus *b, PCIDevice *d, void *opaque), |
1645 | void *opaque) |
1646 | { |
1647 | bus = pci_find_bus_nr(bus, bus_num); |
1648 | |
1649 | if (bus) { |
1650 | pci_for_each_device_under_bus(bus, fn, opaque); |
1651 | } |
1652 | } |
1653 | |
1654 | static const pci_class_desc *get_class_desc(int class) |
1655 | { |
1656 | const pci_class_desc *desc; |
1657 | |
1658 | desc = pci_class_descriptions; |
1659 | while (desc->desc && class != desc->class) { |
1660 | desc++; |
1661 | } |
1662 | |
1663 | return desc; |
1664 | } |
1665 | |
1666 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num); |
1667 | |
1668 | static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev) |
1669 | { |
1670 | PciMemoryRegionList *head = NULL, *cur_item = NULL; |
1671 | int i; |
1672 | |
1673 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
1674 | const PCIIORegion *r = &dev->io_regions[i]; |
1675 | PciMemoryRegionList *region; |
1676 | |
1677 | if (!r->size) { |
1678 | continue; |
1679 | } |
1680 | |
1681 | region = g_malloc0(sizeof(*region)); |
1682 | region->value = g_malloc0(sizeof(*region->value)); |
1683 | |
1684 | if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { |
1685 | region->value->type = g_strdup("io" ); |
1686 | } else { |
1687 | region->value->type = g_strdup("memory" ); |
1688 | region->value->has_prefetch = true; |
1689 | region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH); |
1690 | region->value->has_mem_type_64 = true; |
1691 | region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64); |
1692 | } |
1693 | |
1694 | region->value->bar = i; |
1695 | region->value->address = r->addr; |
1696 | region->value->size = r->size; |
1697 | |
1698 | /* XXX: waiting for the qapi to support GSList */ |
1699 | if (!cur_item) { |
1700 | head = cur_item = region; |
1701 | } else { |
1702 | cur_item->next = region; |
1703 | cur_item = region; |
1704 | } |
1705 | } |
1706 | |
1707 | return head; |
1708 | } |
1709 | |
1710 | static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus, |
1711 | int bus_num) |
1712 | { |
1713 | PciBridgeInfo *info; |
1714 | PciMemoryRange *range; |
1715 | |
1716 | info = g_new0(PciBridgeInfo, 1); |
1717 | |
1718 | info->bus = g_new0(PciBusInfo, 1); |
1719 | info->bus->number = dev->config[PCI_PRIMARY_BUS]; |
1720 | info->bus->secondary = dev->config[PCI_SECONDARY_BUS]; |
1721 | info->bus->subordinate = dev->config[PCI_SUBORDINATE_BUS]; |
1722 | |
1723 | range = info->bus->io_range = g_new0(PciMemoryRange, 1); |
1724 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO); |
1725 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO); |
1726 | |
1727 | range = info->bus->memory_range = g_new0(PciMemoryRange, 1); |
1728 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1729 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); |
1730 | |
1731 | range = info->bus->prefetchable_range = g_new0(PciMemoryRange, 1); |
1732 | range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
1733 | range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
1734 | |
1735 | if (dev->config[PCI_SECONDARY_BUS] != 0) { |
1736 | PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]); |
1737 | if (child_bus) { |
1738 | info->has_devices = true; |
1739 | info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]); |
1740 | } |
1741 | } |
1742 | |
1743 | return info; |
1744 | } |
1745 | |
1746 | static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus, |
1747 | int bus_num) |
1748 | { |
1749 | const pci_class_desc *desc; |
1750 | PciDeviceInfo *info; |
1751 | uint8_t type; |
1752 | int class; |
1753 | |
1754 | info = g_new0(PciDeviceInfo, 1); |
1755 | info->bus = bus_num; |
1756 | info->slot = PCI_SLOT(dev->devfn); |
1757 | info->function = PCI_FUNC(dev->devfn); |
1758 | |
1759 | info->class_info = g_new0(PciDeviceClass, 1); |
1760 | class = pci_get_word(dev->config + PCI_CLASS_DEVICE); |
1761 | info->class_info->q_class = class; |
1762 | desc = get_class_desc(class); |
1763 | if (desc->desc) { |
1764 | info->class_info->has_desc = true; |
1765 | info->class_info->desc = g_strdup(desc->desc); |
1766 | } |
1767 | |
1768 | info->id = g_new0(PciDeviceId, 1); |
1769 | info->id->vendor = pci_get_word(dev->config + PCI_VENDOR_ID); |
1770 | info->id->device = pci_get_word(dev->config + PCI_DEVICE_ID); |
1771 | info->regions = qmp_query_pci_regions(dev); |
1772 | info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "" ); |
1773 | |
1774 | if (dev->config[PCI_INTERRUPT_PIN] != 0) { |
1775 | info->has_irq = true; |
1776 | info->irq = dev->config[PCI_INTERRUPT_LINE]; |
1777 | } |
1778 | |
1779 | type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION; |
1780 | if (type == PCI_HEADER_TYPE_BRIDGE) { |
1781 | info->has_pci_bridge = true; |
1782 | info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num); |
1783 | } else if (type == PCI_HEADER_TYPE_NORMAL) { |
1784 | info->id->has_subsystem = info->id->has_subsystem_vendor = true; |
1785 | info->id->subsystem = pci_get_word(dev->config + PCI_SUBSYSTEM_ID); |
1786 | info->id->subsystem_vendor = |
1787 | pci_get_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID); |
1788 | } else if (type == PCI_HEADER_TYPE_CARDBUS) { |
1789 | info->id->has_subsystem = info->id->has_subsystem_vendor = true; |
1790 | info->id->subsystem = pci_get_word(dev->config + PCI_CB_SUBSYSTEM_ID); |
1791 | info->id->subsystem_vendor = |
1792 | pci_get_word(dev->config + PCI_CB_SUBSYSTEM_VENDOR_ID); |
1793 | } |
1794 | |
1795 | return info; |
1796 | } |
1797 | |
1798 | static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num) |
1799 | { |
1800 | PciDeviceInfoList *info, *head = NULL, *cur_item = NULL; |
1801 | PCIDevice *dev; |
1802 | int devfn; |
1803 | |
1804 | for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { |
1805 | dev = bus->devices[devfn]; |
1806 | if (dev) { |
1807 | info = g_malloc0(sizeof(*info)); |
1808 | info->value = qmp_query_pci_device(dev, bus, bus_num); |
1809 | |
1810 | /* XXX: waiting for the qapi to support GSList */ |
1811 | if (!cur_item) { |
1812 | head = cur_item = info; |
1813 | } else { |
1814 | cur_item->next = info; |
1815 | cur_item = info; |
1816 | } |
1817 | } |
1818 | } |
1819 | |
1820 | return head; |
1821 | } |
1822 | |
1823 | static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num) |
1824 | { |
1825 | PciInfo *info = NULL; |
1826 | |
1827 | bus = pci_find_bus_nr(bus, bus_num); |
1828 | if (bus) { |
1829 | info = g_malloc0(sizeof(*info)); |
1830 | info->bus = bus_num; |
1831 | info->devices = qmp_query_pci_devices(bus, bus_num); |
1832 | } |
1833 | |
1834 | return info; |
1835 | } |
1836 | |
1837 | PciInfoList *qmp_query_pci(Error **errp) |
1838 | { |
1839 | PciInfoList *info, *head = NULL, *cur_item = NULL; |
1840 | PCIHostState *host_bridge; |
1841 | |
1842 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
1843 | info = g_malloc0(sizeof(*info)); |
1844 | info->value = qmp_query_pci_bus(host_bridge->bus, |
1845 | pci_bus_num(host_bridge->bus)); |
1846 | |
1847 | /* XXX: waiting for the qapi to support GSList */ |
1848 | if (!cur_item) { |
1849 | head = cur_item = info; |
1850 | } else { |
1851 | cur_item->next = info; |
1852 | cur_item = info; |
1853 | } |
1854 | } |
1855 | |
1856 | return head; |
1857 | } |
1858 | |
1859 | /* Initialize a PCI NIC. */ |
1860 | PCIDevice *pci_nic_init_nofail(NICInfo *nd, PCIBus *rootbus, |
1861 | const char *default_model, |
1862 | const char *default_devaddr) |
1863 | { |
1864 | const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr; |
1865 | GSList *list; |
1866 | GPtrArray *pci_nic_models; |
1867 | PCIBus *bus; |
1868 | PCIDevice *pci_dev; |
1869 | DeviceState *dev; |
1870 | int devfn; |
1871 | int i; |
1872 | int dom, busnr; |
1873 | unsigned slot; |
1874 | |
1875 | if (nd->model && !strcmp(nd->model, "virtio" )) { |
1876 | g_free(nd->model); |
1877 | nd->model = g_strdup("virtio-net-pci" ); |
1878 | } |
1879 | |
1880 | list = object_class_get_list_sorted(TYPE_PCI_DEVICE, false); |
1881 | pci_nic_models = g_ptr_array_new(); |
1882 | while (list) { |
1883 | DeviceClass *dc = OBJECT_CLASS_CHECK(DeviceClass, list->data, |
1884 | TYPE_DEVICE); |
1885 | GSList *next; |
1886 | if (test_bit(DEVICE_CATEGORY_NETWORK, dc->categories) && |
1887 | dc->user_creatable) { |
1888 | const char *name = object_class_get_name(list->data); |
1889 | g_ptr_array_add(pci_nic_models, (gpointer)name); |
1890 | } |
1891 | next = list->next; |
1892 | g_slist_free_1(list); |
1893 | list = next; |
1894 | } |
1895 | g_ptr_array_add(pci_nic_models, NULL); |
1896 | |
1897 | if (qemu_show_nic_models(nd->model, (const char **)pci_nic_models->pdata)) { |
1898 | exit(0); |
1899 | } |
1900 | |
1901 | i = qemu_find_nic_model(nd, (const char **)pci_nic_models->pdata, |
1902 | default_model); |
1903 | if (i < 0) { |
1904 | exit(1); |
1905 | } |
1906 | |
1907 | if (!rootbus) { |
1908 | error_report("No primary PCI bus" ); |
1909 | exit(1); |
1910 | } |
1911 | |
1912 | assert(!rootbus->parent_dev); |
1913 | |
1914 | if (!devaddr) { |
1915 | devfn = -1; |
1916 | busnr = 0; |
1917 | } else { |
1918 | if (pci_parse_devaddr(devaddr, &dom, &busnr, &slot, NULL) < 0) { |
1919 | error_report("Invalid PCI device address %s for device %s" , |
1920 | devaddr, nd->model); |
1921 | exit(1); |
1922 | } |
1923 | |
1924 | if (dom != 0) { |
1925 | error_report("No support for non-zero PCI domains" ); |
1926 | exit(1); |
1927 | } |
1928 | |
1929 | devfn = PCI_DEVFN(slot, 0); |
1930 | } |
1931 | |
1932 | bus = pci_find_bus_nr(rootbus, busnr); |
1933 | if (!bus) { |
1934 | error_report("Invalid PCI device address %s for device %s" , |
1935 | devaddr, nd->model); |
1936 | exit(1); |
1937 | } |
1938 | |
1939 | pci_dev = pci_create(bus, devfn, nd->model); |
1940 | dev = &pci_dev->qdev; |
1941 | qdev_set_nic_properties(dev, nd); |
1942 | qdev_init_nofail(dev); |
1943 | g_ptr_array_free(pci_nic_models, true); |
1944 | return pci_dev; |
1945 | } |
1946 | |
1947 | PCIDevice *pci_vga_init(PCIBus *bus) |
1948 | { |
1949 | switch (vga_interface_type) { |
1950 | case VGA_CIRRUS: |
1951 | return pci_create_simple(bus, -1, "cirrus-vga" ); |
1952 | case VGA_QXL: |
1953 | return pci_create_simple(bus, -1, "qxl-vga" ); |
1954 | case VGA_STD: |
1955 | return pci_create_simple(bus, -1, "VGA" ); |
1956 | case VGA_VMWARE: |
1957 | return pci_create_simple(bus, -1, "vmware-svga" ); |
1958 | case VGA_VIRTIO: |
1959 | return pci_create_simple(bus, -1, "virtio-vga" ); |
1960 | case VGA_NONE: |
1961 | default: /* Other non-PCI types. Checking for unsupported types is already |
1962 | done in vl.c. */ |
1963 | return NULL; |
1964 | } |
1965 | } |
1966 | |
1967 | /* Whether a given bus number is in range of the secondary |
1968 | * bus of the given bridge device. */ |
1969 | static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num) |
1970 | { |
1971 | return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) & |
1972 | PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ && |
1973 | dev->config[PCI_SECONDARY_BUS] <= bus_num && |
1974 | bus_num <= dev->config[PCI_SUBORDINATE_BUS]; |
1975 | } |
1976 | |
1977 | /* Whether a given bus number is in a range of a root bus */ |
1978 | static bool pci_root_bus_in_range(PCIBus *bus, int bus_num) |
1979 | { |
1980 | int i; |
1981 | |
1982 | for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) { |
1983 | PCIDevice *dev = bus->devices[i]; |
1984 | |
1985 | if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { |
1986 | if (pci_secondary_bus_in_range(dev, bus_num)) { |
1987 | return true; |
1988 | } |
1989 | } |
1990 | } |
1991 | |
1992 | return false; |
1993 | } |
1994 | |
1995 | static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num) |
1996 | { |
1997 | PCIBus *sec; |
1998 | |
1999 | if (!bus) { |
2000 | return NULL; |
2001 | } |
2002 | |
2003 | if (pci_bus_num(bus) == bus_num) { |
2004 | return bus; |
2005 | } |
2006 | |
2007 | /* Consider all bus numbers in range for the host pci bridge. */ |
2008 | if (!pci_bus_is_root(bus) && |
2009 | !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) { |
2010 | return NULL; |
2011 | } |
2012 | |
2013 | /* try child bus */ |
2014 | for (; bus; bus = sec) { |
2015 | QLIST_FOREACH(sec, &bus->child, sibling) { |
2016 | if (pci_bus_num(sec) == bus_num) { |
2017 | return sec; |
2018 | } |
2019 | /* PXB buses assumed to be children of bus 0 */ |
2020 | if (pci_bus_is_root(sec)) { |
2021 | if (pci_root_bus_in_range(sec, bus_num)) { |
2022 | break; |
2023 | } |
2024 | } else { |
2025 | if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) { |
2026 | break; |
2027 | } |
2028 | } |
2029 | } |
2030 | } |
2031 | |
2032 | return NULL; |
2033 | } |
2034 | |
2035 | void pci_for_each_bus_depth_first(PCIBus *bus, |
2036 | void *(*begin)(PCIBus *bus, void *parent_state), |
2037 | void (*end)(PCIBus *bus, void *state), |
2038 | void *parent_state) |
2039 | { |
2040 | PCIBus *sec; |
2041 | void *state; |
2042 | |
2043 | if (!bus) { |
2044 | return; |
2045 | } |
2046 | |
2047 | if (begin) { |
2048 | state = begin(bus, parent_state); |
2049 | } else { |
2050 | state = parent_state; |
2051 | } |
2052 | |
2053 | QLIST_FOREACH(sec, &bus->child, sibling) { |
2054 | pci_for_each_bus_depth_first(sec, begin, end, state); |
2055 | } |
2056 | |
2057 | if (end) { |
2058 | end(bus, state); |
2059 | } |
2060 | } |
2061 | |
2062 | |
2063 | PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn) |
2064 | { |
2065 | bus = pci_find_bus_nr(bus, bus_num); |
2066 | |
2067 | if (!bus) |
2068 | return NULL; |
2069 | |
2070 | return bus->devices[devfn]; |
2071 | } |
2072 | |
2073 | static void pci_qdev_realize(DeviceState *qdev, Error **errp) |
2074 | { |
2075 | PCIDevice *pci_dev = (PCIDevice *)qdev; |
2076 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev); |
2077 | ObjectClass *klass = OBJECT_CLASS(pc); |
2078 | Error *local_err = NULL; |
2079 | bool is_default_rom; |
2080 | |
2081 | /* initialize cap_present for pci_is_express() and pci_config_size(), |
2082 | * Note that hybrid PCIs are not set automatically and need to manage |
2083 | * QEMU_PCI_CAP_EXPRESS manually */ |
2084 | if (object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE) && |
2085 | !object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE)) { |
2086 | pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS; |
2087 | } |
2088 | |
2089 | pci_dev = do_pci_register_device(pci_dev, |
2090 | object_get_typename(OBJECT(qdev)), |
2091 | pci_dev->devfn, errp); |
2092 | if (pci_dev == NULL) |
2093 | return; |
2094 | |
2095 | if (pc->realize) { |
2096 | pc->realize(pci_dev, &local_err); |
2097 | if (local_err) { |
2098 | error_propagate(errp, local_err); |
2099 | do_pci_unregister_device(pci_dev); |
2100 | return; |
2101 | } |
2102 | } |
2103 | |
2104 | /* rom loading */ |
2105 | is_default_rom = false; |
2106 | if (pci_dev->romfile == NULL && pc->romfile != NULL) { |
2107 | pci_dev->romfile = g_strdup(pc->romfile); |
2108 | is_default_rom = true; |
2109 | } |
2110 | |
2111 | pci_add_option_rom(pci_dev, is_default_rom, &local_err); |
2112 | if (local_err) { |
2113 | error_propagate(errp, local_err); |
2114 | pci_qdev_unrealize(DEVICE(pci_dev), NULL); |
2115 | return; |
2116 | } |
2117 | } |
2118 | |
2119 | PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction, |
2120 | const char *name) |
2121 | { |
2122 | DeviceState *dev; |
2123 | |
2124 | dev = qdev_create(&bus->qbus, name); |
2125 | qdev_prop_set_int32(dev, "addr" , devfn); |
2126 | qdev_prop_set_bit(dev, "multifunction" , multifunction); |
2127 | return PCI_DEVICE(dev); |
2128 | } |
2129 | |
2130 | PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn, |
2131 | bool multifunction, |
2132 | const char *name) |
2133 | { |
2134 | PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name); |
2135 | qdev_init_nofail(&dev->qdev); |
2136 | return dev; |
2137 | } |
2138 | |
2139 | PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name) |
2140 | { |
2141 | return pci_create_multifunction(bus, devfn, false, name); |
2142 | } |
2143 | |
2144 | PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name) |
2145 | { |
2146 | return pci_create_simple_multifunction(bus, devfn, false, name); |
2147 | } |
2148 | |
2149 | static uint8_t pci_find_space(PCIDevice *pdev, uint8_t size) |
2150 | { |
2151 | int offset = PCI_CONFIG_HEADER_SIZE; |
2152 | int i; |
2153 | for (i = PCI_CONFIG_HEADER_SIZE; i < PCI_CONFIG_SPACE_SIZE; ++i) { |
2154 | if (pdev->used[i]) |
2155 | offset = i + 1; |
2156 | else if (i - offset + 1 == size) |
2157 | return offset; |
2158 | } |
2159 | return 0; |
2160 | } |
2161 | |
2162 | static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id, |
2163 | uint8_t *prev_p) |
2164 | { |
2165 | uint8_t next, prev; |
2166 | |
2167 | if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST)) |
2168 | return 0; |
2169 | |
2170 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); |
2171 | prev = next + PCI_CAP_LIST_NEXT) |
2172 | if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id) |
2173 | break; |
2174 | |
2175 | if (prev_p) |
2176 | *prev_p = prev; |
2177 | return next; |
2178 | } |
2179 | |
2180 | static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset) |
2181 | { |
2182 | uint8_t next, prev, found = 0; |
2183 | |
2184 | if (!(pdev->used[offset])) { |
2185 | return 0; |
2186 | } |
2187 | |
2188 | assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST); |
2189 | |
2190 | for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]); |
2191 | prev = next + PCI_CAP_LIST_NEXT) { |
2192 | if (next <= offset && next > found) { |
2193 | found = next; |
2194 | } |
2195 | } |
2196 | return found; |
2197 | } |
2198 | |
2199 | /* Patch the PCI vendor and device ids in a PCI rom image if necessary. |
2200 | This is needed for an option rom which is used for more than one device. */ |
2201 | static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size) |
2202 | { |
2203 | uint16_t vendor_id; |
2204 | uint16_t device_id; |
2205 | uint16_t rom_vendor_id; |
2206 | uint16_t rom_device_id; |
2207 | uint16_t rom_magic; |
2208 | uint16_t pcir_offset; |
2209 | uint8_t checksum; |
2210 | |
2211 | /* Words in rom data are little endian (like in PCI configuration), |
2212 | so they can be read / written with pci_get_word / pci_set_word. */ |
2213 | |
2214 | /* Only a valid rom will be patched. */ |
2215 | rom_magic = pci_get_word(ptr); |
2216 | if (rom_magic != 0xaa55) { |
2217 | PCI_DPRINTF("Bad ROM magic %04x\n" , rom_magic); |
2218 | return; |
2219 | } |
2220 | pcir_offset = pci_get_word(ptr + 0x18); |
2221 | if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR" , 4)) { |
2222 | PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n" , pcir_offset); |
2223 | return; |
2224 | } |
2225 | |
2226 | vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID); |
2227 | device_id = pci_get_word(pdev->config + PCI_DEVICE_ID); |
2228 | rom_vendor_id = pci_get_word(ptr + pcir_offset + 4); |
2229 | rom_device_id = pci_get_word(ptr + pcir_offset + 6); |
2230 | |
2231 | PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n" , pdev->romfile, |
2232 | vendor_id, device_id, rom_vendor_id, rom_device_id); |
2233 | |
2234 | checksum = ptr[6]; |
2235 | |
2236 | if (vendor_id != rom_vendor_id) { |
2237 | /* Patch vendor id and checksum (at offset 6 for etherboot roms). */ |
2238 | checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8); |
2239 | checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8); |
2240 | PCI_DPRINTF("ROM checksum %02x / %02x\n" , ptr[6], checksum); |
2241 | ptr[6] = checksum; |
2242 | pci_set_word(ptr + pcir_offset + 4, vendor_id); |
2243 | } |
2244 | |
2245 | if (device_id != rom_device_id) { |
2246 | /* Patch device id and checksum (at offset 6 for etherboot roms). */ |
2247 | checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8); |
2248 | checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8); |
2249 | PCI_DPRINTF("ROM checksum %02x / %02x\n" , ptr[6], checksum); |
2250 | ptr[6] = checksum; |
2251 | pci_set_word(ptr + pcir_offset + 6, device_id); |
2252 | } |
2253 | } |
2254 | |
2255 | /* Add an option rom for the device */ |
2256 | static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, |
2257 | Error **errp) |
2258 | { |
2259 | int size; |
2260 | char *path; |
2261 | void *ptr; |
2262 | char name[32]; |
2263 | const VMStateDescription *vmsd; |
2264 | |
2265 | if (!pdev->romfile) |
2266 | return; |
2267 | if (strlen(pdev->romfile) == 0) |
2268 | return; |
2269 | |
2270 | if (!pdev->rom_bar) { |
2271 | /* |
2272 | * Load rom via fw_cfg instead of creating a rom bar, |
2273 | * for 0.11 compatibility. |
2274 | */ |
2275 | int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE); |
2276 | |
2277 | /* |
2278 | * Hot-plugged devices can't use the option ROM |
2279 | * if the rom bar is disabled. |
2280 | */ |
2281 | if (DEVICE(pdev)->hotplugged) { |
2282 | error_setg(errp, "Hot-plugged device without ROM bar" |
2283 | " can't have an option ROM" ); |
2284 | return; |
2285 | } |
2286 | |
2287 | if (class == 0x0300) { |
2288 | rom_add_vga(pdev->romfile); |
2289 | } else { |
2290 | rom_add_option(pdev->romfile, -1); |
2291 | } |
2292 | return; |
2293 | } |
2294 | |
2295 | path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile); |
2296 | if (path == NULL) { |
2297 | path = g_strdup(pdev->romfile); |
2298 | } |
2299 | |
2300 | size = get_image_size(path); |
2301 | if (size < 0) { |
2302 | error_setg(errp, "failed to find romfile \"%s\"" , pdev->romfile); |
2303 | g_free(path); |
2304 | return; |
2305 | } else if (size == 0) { |
2306 | error_setg(errp, "romfile \"%s\" is empty" , pdev->romfile); |
2307 | g_free(path); |
2308 | return; |
2309 | } |
2310 | size = pow2ceil(size); |
2311 | |
2312 | vmsd = qdev_get_vmsd(DEVICE(pdev)); |
2313 | |
2314 | if (vmsd) { |
2315 | snprintf(name, sizeof(name), "%s.rom" , vmsd->name); |
2316 | } else { |
2317 | snprintf(name, sizeof(name), "%s.rom" , object_get_typename(OBJECT(pdev))); |
2318 | } |
2319 | pdev->has_rom = true; |
2320 | memory_region_init_rom(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); |
2321 | ptr = memory_region_get_ram_ptr(&pdev->rom); |
2322 | if (load_image_size(path, ptr, size) < 0) { |
2323 | error_setg(errp, "failed to load romfile \"%s\"" , pdev->romfile); |
2324 | g_free(path); |
2325 | return; |
2326 | } |
2327 | g_free(path); |
2328 | |
2329 | if (is_default_rom) { |
2330 | /* Only the default rom images will be patched (if needed). */ |
2331 | pci_patch_ids(pdev, ptr, size); |
2332 | } |
2333 | |
2334 | pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom); |
2335 | } |
2336 | |
2337 | static void pci_del_option_rom(PCIDevice *pdev) |
2338 | { |
2339 | if (!pdev->has_rom) |
2340 | return; |
2341 | |
2342 | vmstate_unregister_ram(&pdev->rom, &pdev->qdev); |
2343 | pdev->has_rom = false; |
2344 | } |
2345 | |
2346 | /* |
2347 | * On success, pci_add_capability() returns a positive value |
2348 | * that the offset of the pci capability. |
2349 | * On failure, it sets an error and returns a negative error |
2350 | * code. |
2351 | */ |
2352 | int pci_add_capability(PCIDevice *pdev, uint8_t cap_id, |
2353 | uint8_t offset, uint8_t size, |
2354 | Error **errp) |
2355 | { |
2356 | uint8_t *config; |
2357 | int i, overlapping_cap; |
2358 | |
2359 | if (!offset) { |
2360 | offset = pci_find_space(pdev, size); |
2361 | /* out of PCI config space is programming error */ |
2362 | assert(offset); |
2363 | } else { |
2364 | /* Verify that capabilities don't overlap. Note: device assignment |
2365 | * depends on this check to verify that the device is not broken. |
2366 | * Should never trigger for emulated devices, but it's helpful |
2367 | * for debugging these. */ |
2368 | for (i = offset; i < offset + size; i++) { |
2369 | overlapping_cap = pci_find_capability_at_offset(pdev, i); |
2370 | if (overlapping_cap) { |
2371 | error_setg(errp, "%s:%02x:%02x.%x " |
2372 | "Attempt to add PCI capability %x at offset " |
2373 | "%x overlaps existing capability %x at offset %x" , |
2374 | pci_root_bus_path(pdev), pci_dev_bus_num(pdev), |
2375 | PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), |
2376 | cap_id, offset, overlapping_cap, i); |
2377 | return -EINVAL; |
2378 | } |
2379 | } |
2380 | } |
2381 | |
2382 | config = pdev->config + offset; |
2383 | config[PCI_CAP_LIST_ID] = cap_id; |
2384 | config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST]; |
2385 | pdev->config[PCI_CAPABILITY_LIST] = offset; |
2386 | pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST; |
2387 | memset(pdev->used + offset, 0xFF, QEMU_ALIGN_UP(size, 4)); |
2388 | /* Make capability read-only by default */ |
2389 | memset(pdev->wmask + offset, 0, size); |
2390 | /* Check capability by default */ |
2391 | memset(pdev->cmask + offset, 0xFF, size); |
2392 | return offset; |
2393 | } |
2394 | |
2395 | /* Unlink capability from the pci config space. */ |
2396 | void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size) |
2397 | { |
2398 | uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev); |
2399 | if (!offset) |
2400 | return; |
2401 | pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT]; |
2402 | /* Make capability writable again */ |
2403 | memset(pdev->wmask + offset, 0xff, size); |
2404 | memset(pdev->w1cmask + offset, 0, size); |
2405 | /* Clear cmask as device-specific registers can't be checked */ |
2406 | memset(pdev->cmask + offset, 0, size); |
2407 | memset(pdev->used + offset, 0, QEMU_ALIGN_UP(size, 4)); |
2408 | |
2409 | if (!pdev->config[PCI_CAPABILITY_LIST]) |
2410 | pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST; |
2411 | } |
2412 | |
2413 | uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id) |
2414 | { |
2415 | return pci_find_capability_list(pdev, cap_id, NULL); |
2416 | } |
2417 | |
2418 | static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent) |
2419 | { |
2420 | PCIDevice *d = (PCIDevice *)dev; |
2421 | const pci_class_desc *desc; |
2422 | char ctxt[64]; |
2423 | PCIIORegion *r; |
2424 | int i, class; |
2425 | |
2426 | class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
2427 | desc = pci_class_descriptions; |
2428 | while (desc->desc && class != desc->class) |
2429 | desc++; |
2430 | if (desc->desc) { |
2431 | snprintf(ctxt, sizeof(ctxt), "%s" , desc->desc); |
2432 | } else { |
2433 | snprintf(ctxt, sizeof(ctxt), "Class %04x" , class); |
2434 | } |
2435 | |
2436 | monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, " |
2437 | "pci id %04x:%04x (sub %04x:%04x)\n" , |
2438 | indent, "" , ctxt, pci_dev_bus_num(d), |
2439 | PCI_SLOT(d->devfn), PCI_FUNC(d->devfn), |
2440 | pci_get_word(d->config + PCI_VENDOR_ID), |
2441 | pci_get_word(d->config + PCI_DEVICE_ID), |
2442 | pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID), |
2443 | pci_get_word(d->config + PCI_SUBSYSTEM_ID)); |
2444 | for (i = 0; i < PCI_NUM_REGIONS; i++) { |
2445 | r = &d->io_regions[i]; |
2446 | if (!r->size) |
2447 | continue; |
2448 | monitor_printf(mon, "%*sbar %d: %s at 0x%" FMT_PCIBUS |
2449 | " [0x%" FMT_PCIBUS"]\n" , |
2450 | indent, "" , |
2451 | i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem" , |
2452 | r->addr, r->addr + r->size - 1); |
2453 | } |
2454 | } |
2455 | |
2456 | static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len) |
2457 | { |
2458 | PCIDevice *d = (PCIDevice *)dev; |
2459 | const char *name = NULL; |
2460 | const pci_class_desc *desc = pci_class_descriptions; |
2461 | int class = pci_get_word(d->config + PCI_CLASS_DEVICE); |
2462 | |
2463 | while (desc->desc && |
2464 | (class & ~desc->fw_ign_bits) != |
2465 | (desc->class & ~desc->fw_ign_bits)) { |
2466 | desc++; |
2467 | } |
2468 | |
2469 | if (desc->desc) { |
2470 | name = desc->fw_name; |
2471 | } |
2472 | |
2473 | if (name) { |
2474 | pstrcpy(buf, len, name); |
2475 | } else { |
2476 | snprintf(buf, len, "pci%04x,%04x" , |
2477 | pci_get_word(d->config + PCI_VENDOR_ID), |
2478 | pci_get_word(d->config + PCI_DEVICE_ID)); |
2479 | } |
2480 | |
2481 | return buf; |
2482 | } |
2483 | |
2484 | static char *pcibus_get_fw_dev_path(DeviceState *dev) |
2485 | { |
2486 | PCIDevice *d = (PCIDevice *)dev; |
2487 | char path[50], name[33]; |
2488 | int off; |
2489 | |
2490 | off = snprintf(path, sizeof(path), "%s@%x" , |
2491 | pci_dev_fw_name(dev, name, sizeof name), |
2492 | PCI_SLOT(d->devfn)); |
2493 | if (PCI_FUNC(d->devfn)) |
2494 | snprintf(path + off, sizeof(path) + off, ",%x" , PCI_FUNC(d->devfn)); |
2495 | return g_strdup(path); |
2496 | } |
2497 | |
2498 | static char *pcibus_get_dev_path(DeviceState *dev) |
2499 | { |
2500 | PCIDevice *d = container_of(dev, PCIDevice, qdev); |
2501 | PCIDevice *t; |
2502 | int slot_depth; |
2503 | /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function. |
2504 | * 00 is added here to make this format compatible with |
2505 | * domain:Bus:Slot.Func for systems without nested PCI bridges. |
2506 | * Slot.Function list specifies the slot and function numbers for all |
2507 | * devices on the path from root to the specific device. */ |
2508 | const char *root_bus_path; |
2509 | int root_bus_len; |
2510 | char slot[] = ":SS.F" ; |
2511 | int slot_len = sizeof slot - 1 /* For '\0' */; |
2512 | int path_len; |
2513 | char *path, *p; |
2514 | int s; |
2515 | |
2516 | root_bus_path = pci_root_bus_path(d); |
2517 | root_bus_len = strlen(root_bus_path); |
2518 | |
2519 | /* Calculate # of slots on path between device and root. */; |
2520 | slot_depth = 0; |
2521 | for (t = d; t; t = pci_get_bus(t)->parent_dev) { |
2522 | ++slot_depth; |
2523 | } |
2524 | |
2525 | path_len = root_bus_len + slot_len * slot_depth; |
2526 | |
2527 | /* Allocate memory, fill in the terminating null byte. */ |
2528 | path = g_malloc(path_len + 1 /* For '\0' */); |
2529 | path[path_len] = '\0'; |
2530 | |
2531 | memcpy(path, root_bus_path, root_bus_len); |
2532 | |
2533 | /* Fill in slot numbers. We walk up from device to root, so need to print |
2534 | * them in the reverse order, last to first. */ |
2535 | p = path + path_len; |
2536 | for (t = d; t; t = pci_get_bus(t)->parent_dev) { |
2537 | p -= slot_len; |
2538 | s = snprintf(slot, sizeof slot, ":%02x.%x" , |
2539 | PCI_SLOT(t->devfn), PCI_FUNC(t->devfn)); |
2540 | assert(s == slot_len); |
2541 | memcpy(p, slot, slot_len); |
2542 | } |
2543 | |
2544 | return path; |
2545 | } |
2546 | |
2547 | static int pci_qdev_find_recursive(PCIBus *bus, |
2548 | const char *id, PCIDevice **pdev) |
2549 | { |
2550 | DeviceState *qdev = qdev_find_recursive(&bus->qbus, id); |
2551 | if (!qdev) { |
2552 | return -ENODEV; |
2553 | } |
2554 | |
2555 | /* roughly check if given qdev is pci device */ |
2556 | if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) { |
2557 | *pdev = PCI_DEVICE(qdev); |
2558 | return 0; |
2559 | } |
2560 | return -EINVAL; |
2561 | } |
2562 | |
2563 | int pci_qdev_find_device(const char *id, PCIDevice **pdev) |
2564 | { |
2565 | PCIHostState *host_bridge; |
2566 | int rc = -ENODEV; |
2567 | |
2568 | QLIST_FOREACH(host_bridge, &pci_host_bridges, next) { |
2569 | int tmp = pci_qdev_find_recursive(host_bridge->bus, id, pdev); |
2570 | if (!tmp) { |
2571 | rc = 0; |
2572 | break; |
2573 | } |
2574 | if (tmp != -ENODEV) { |
2575 | rc = tmp; |
2576 | } |
2577 | } |
2578 | |
2579 | return rc; |
2580 | } |
2581 | |
2582 | MemoryRegion *pci_address_space(PCIDevice *dev) |
2583 | { |
2584 | return pci_get_bus(dev)->address_space_mem; |
2585 | } |
2586 | |
2587 | MemoryRegion *pci_address_space_io(PCIDevice *dev) |
2588 | { |
2589 | return pci_get_bus(dev)->address_space_io; |
2590 | } |
2591 | |
2592 | static void pci_device_class_init(ObjectClass *klass, void *data) |
2593 | { |
2594 | DeviceClass *k = DEVICE_CLASS(klass); |
2595 | |
2596 | k->realize = pci_qdev_realize; |
2597 | k->unrealize = pci_qdev_unrealize; |
2598 | k->bus_type = TYPE_PCI_BUS; |
2599 | k->props = pci_props; |
2600 | } |
2601 | |
2602 | static void pci_device_class_base_init(ObjectClass *klass, void *data) |
2603 | { |
2604 | if (!object_class_is_abstract(klass)) { |
2605 | ObjectClass *conventional = |
2606 | object_class_dynamic_cast(klass, INTERFACE_CONVENTIONAL_PCI_DEVICE); |
2607 | ObjectClass *pcie = |
2608 | object_class_dynamic_cast(klass, INTERFACE_PCIE_DEVICE); |
2609 | assert(conventional || pcie); |
2610 | } |
2611 | } |
2612 | |
2613 | AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) |
2614 | { |
2615 | PCIBus *bus = pci_get_bus(dev); |
2616 | PCIBus *iommu_bus = bus; |
2617 | |
2618 | while(iommu_bus && !iommu_bus->iommu_fn && iommu_bus->parent_dev) { |
2619 | iommu_bus = pci_get_bus(iommu_bus->parent_dev); |
2620 | } |
2621 | if (iommu_bus && iommu_bus->iommu_fn) { |
2622 | return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, dev->devfn); |
2623 | } |
2624 | return &address_space_memory; |
2625 | } |
2626 | |
2627 | void pci_setup_iommu(PCIBus *bus, PCIIOMMUFunc fn, void *opaque) |
2628 | { |
2629 | bus->iommu_fn = fn; |
2630 | bus->iommu_opaque = opaque; |
2631 | } |
2632 | |
2633 | static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) |
2634 | { |
2635 | Range *range = opaque; |
2636 | PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); |
2637 | uint16_t cmd = pci_get_word(dev->config + PCI_COMMAND); |
2638 | int i; |
2639 | |
2640 | if (!(cmd & PCI_COMMAND_MEMORY)) { |
2641 | return; |
2642 | } |
2643 | |
2644 | if (pc->is_bridge) { |
2645 | pcibus_t base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
2646 | pcibus_t limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); |
2647 | |
2648 | base = MAX(base, 0x1ULL << 32); |
2649 | |
2650 | if (limit >= base) { |
2651 | Range pref_range; |
2652 | range_set_bounds(&pref_range, base, limit); |
2653 | range_extend(range, &pref_range); |
2654 | } |
2655 | } |
2656 | for (i = 0; i < PCI_NUM_REGIONS; ++i) { |
2657 | PCIIORegion *r = &dev->io_regions[i]; |
2658 | pcibus_t lob, upb; |
2659 | Range region_range; |
2660 | |
2661 | if (!r->size || |
2662 | (r->type & PCI_BASE_ADDRESS_SPACE_IO) || |
2663 | !(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64)) { |
2664 | continue; |
2665 | } |
2666 | |
2667 | lob = pci_bar_address(dev, i, r->type, r->size); |
2668 | upb = lob + r->size - 1; |
2669 | if (lob == PCI_BAR_UNMAPPED) { |
2670 | continue; |
2671 | } |
2672 | |
2673 | lob = MAX(lob, 0x1ULL << 32); |
2674 | |
2675 | if (upb >= lob) { |
2676 | range_set_bounds(®ion_range, lob, upb); |
2677 | range_extend(range, ®ion_range); |
2678 | } |
2679 | } |
2680 | } |
2681 | |
2682 | void pci_bus_get_w64_range(PCIBus *bus, Range *range) |
2683 | { |
2684 | range_make_empty(range); |
2685 | pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); |
2686 | } |
2687 | |
2688 | static bool pcie_has_upstream_port(PCIDevice *dev) |
2689 | { |
2690 | PCIDevice *parent_dev = pci_bridge_get_device(pci_get_bus(dev)); |
2691 | |
2692 | /* Device associated with an upstream port. |
2693 | * As there are several types of these, it's easier to check the |
2694 | * parent device: upstream ports are always connected to |
2695 | * root or downstream ports. |
2696 | */ |
2697 | return parent_dev && |
2698 | pci_is_express(parent_dev) && |
2699 | parent_dev->exp.exp_cap && |
2700 | (pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_ROOT_PORT || |
2701 | pcie_cap_get_type(parent_dev) == PCI_EXP_TYPE_DOWNSTREAM); |
2702 | } |
2703 | |
2704 | PCIDevice *pci_get_function_0(PCIDevice *pci_dev) |
2705 | { |
2706 | PCIBus *bus = pci_get_bus(pci_dev); |
2707 | |
2708 | if(pcie_has_upstream_port(pci_dev)) { |
2709 | /* With an upstream PCIe port, we only support 1 device at slot 0 */ |
2710 | return bus->devices[0]; |
2711 | } else { |
2712 | /* Other bus types might support multiple devices at slots 0-31 */ |
2713 | return bus->devices[PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 0)]; |
2714 | } |
2715 | } |
2716 | |
2717 | MSIMessage pci_get_msi_message(PCIDevice *dev, int vector) |
2718 | { |
2719 | MSIMessage msg; |
2720 | if (msix_enabled(dev)) { |
2721 | msg = msix_get_message(dev, vector); |
2722 | } else if (msi_enabled(dev)) { |
2723 | msg = msi_get_message(dev, vector); |
2724 | } else { |
2725 | /* Should never happen */ |
2726 | error_report("%s: unknown interrupt type" , __func__); |
2727 | abort(); |
2728 | } |
2729 | return msg; |
2730 | } |
2731 | |
2732 | static const TypeInfo pci_device_type_info = { |
2733 | .name = TYPE_PCI_DEVICE, |
2734 | .parent = TYPE_DEVICE, |
2735 | .instance_size = sizeof(PCIDevice), |
2736 | .abstract = true, |
2737 | .class_size = sizeof(PCIDeviceClass), |
2738 | .class_init = pci_device_class_init, |
2739 | .class_base_init = pci_device_class_base_init, |
2740 | }; |
2741 | |
2742 | static void pci_register_types(void) |
2743 | { |
2744 | type_register_static(&pci_bus_info); |
2745 | type_register_static(&pcie_bus_info); |
2746 | type_register_static(&conventional_pci_interface_info); |
2747 | type_register_static(&pcie_interface_info); |
2748 | type_register_static(&pci_device_type_info); |
2749 | } |
2750 | |
2751 | type_init(pci_register_types) |
2752 | |