1/*
2 * QEMU PowerPC 405 evaluation boards emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "qemu/osdep.h"
26#include "qemu/units.h"
27#include "qapi/error.h"
28#include "qemu-common.h"
29#include "cpu.h"
30#include "hw/ppc/ppc.h"
31#include "ppc405.h"
32#include "hw/timer/m48t59.h"
33#include "hw/block/flash.h"
34#include "sysemu/sysemu.h"
35#include "sysemu/qtest.h"
36#include "sysemu/reset.h"
37#include "sysemu/block-backend.h"
38#include "hw/boards.h"
39#include "qemu/log.h"
40#include "qemu/error-report.h"
41#include "hw/loader.h"
42#include "exec/address-spaces.h"
43
44#define BIOS_FILENAME "ppc405_rom.bin"
45#define BIOS_SIZE (2 * MiB)
46
47#define KERNEL_LOAD_ADDR 0x00000000
48#define INITRD_LOAD_ADDR 0x01800000
49
50#define USE_FLASH_BIOS
51
52/*****************************************************************************/
53/* PPC405EP reference board (IBM) */
54/* Standalone board with:
55 * - PowerPC 405EP CPU
56 * - SDRAM (0x00000000)
57 * - Flash (0xFFF80000)
58 * - SRAM (0xFFF00000)
59 * - NVRAM (0xF0000000)
60 * - FPGA (0xF0300000)
61 */
62typedef struct ref405ep_fpga_t ref405ep_fpga_t;
63struct ref405ep_fpga_t {
64 uint8_t reg0;
65 uint8_t reg1;
66};
67
68static uint64_t ref405ep_fpga_readb(void *opaque, hwaddr addr, unsigned size)
69{
70 ref405ep_fpga_t *fpga;
71 uint32_t ret;
72
73 fpga = opaque;
74 switch (addr) {
75 case 0x0:
76 ret = fpga->reg0;
77 break;
78 case 0x1:
79 ret = fpga->reg1;
80 break;
81 default:
82 ret = 0;
83 break;
84 }
85
86 return ret;
87}
88
89static void ref405ep_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
90 unsigned size)
91{
92 ref405ep_fpga_t *fpga;
93
94 fpga = opaque;
95 switch (addr) {
96 case 0x0:
97 /* Read only */
98 break;
99 case 0x1:
100 fpga->reg1 = value;
101 break;
102 default:
103 break;
104 }
105}
106
107static const MemoryRegionOps ref405ep_fpga_ops = {
108 .read = ref405ep_fpga_readb,
109 .write = ref405ep_fpga_writeb,
110 .impl.min_access_size = 1,
111 .impl.max_access_size = 1,
112 .valid.min_access_size = 1,
113 .valid.max_access_size = 4,
114 .endianness = DEVICE_BIG_ENDIAN,
115};
116
117static void ref405ep_fpga_reset (void *opaque)
118{
119 ref405ep_fpga_t *fpga;
120
121 fpga = opaque;
122 fpga->reg0 = 0x00;
123 fpga->reg1 = 0x0F;
124}
125
126static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
127{
128 ref405ep_fpga_t *fpga;
129 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
130
131 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
132 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
133 "fpga", 0x00000100);
134 memory_region_add_subregion(sysmem, base, fpga_memory);
135 qemu_register_reset(&ref405ep_fpga_reset, fpga);
136}
137
138static void ref405ep_init(MachineState *machine)
139{
140 ram_addr_t ram_size = machine->ram_size;
141 const char *kernel_filename = machine->kernel_filename;
142 const char *kernel_cmdline = machine->kernel_cmdline;
143 const char *initrd_filename = machine->initrd_filename;
144 char *filename;
145 ppc4xx_bd_info_t bd;
146 CPUPPCState *env;
147 qemu_irq *pic;
148 MemoryRegion *bios;
149 MemoryRegion *sram = g_new(MemoryRegion, 1);
150 ram_addr_t bdloc;
151 MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
152 hwaddr ram_bases[2], ram_sizes[2];
153 target_ulong sram_size;
154 long bios_size;
155 //int phy_addr = 0;
156 //static int phy_addr = 1;
157 target_ulong kernel_base, initrd_base;
158 long kernel_size, initrd_size;
159 int linux_boot;
160 int len;
161 DriveInfo *dinfo;
162 MemoryRegion *sysmem = get_system_memory();
163
164 /* XXX: fix this */
165 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
166 0x08000000);
167 ram_bases[0] = 0;
168 ram_sizes[0] = 0x08000000;
169 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
170 ram_bases[1] = 0x00000000;
171 ram_sizes[1] = 0x00000000;
172 ram_size = 128 * MiB;
173 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
174 33333333, &pic, kernel_filename == NULL ? 0 : 1);
175 /* allocate SRAM */
176 sram_size = 512 * KiB;
177 memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size,
178 &error_fatal);
179 memory_region_add_subregion(sysmem, 0xFFF00000, sram);
180 /* allocate and load BIOS */
181#ifdef USE_FLASH_BIOS
182 dinfo = drive_get(IF_PFLASH, 0, 0);
183 if (dinfo) {
184 bios_size = 8 * MiB;
185 pflash_cfi02_register((uint32_t)(-bios_size),
186 "ef405ep.bios", bios_size,
187 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
188 64 * KiB, 1,
189 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
190 1);
191 } else
192#endif
193 {
194 bios = g_new(MemoryRegion, 1);
195 memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE,
196 &error_fatal);
197
198 if (bios_name == NULL)
199 bios_name = BIOS_FILENAME;
200 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
201 if (filename) {
202 bios_size = load_image_size(filename,
203 memory_region_get_ram_ptr(bios),
204 BIOS_SIZE);
205 g_free(filename);
206 if (bios_size < 0) {
207 error_report("Could not load PowerPC BIOS '%s'", bios_name);
208 exit(1);
209 }
210 bios_size = (bios_size + 0xfff) & ~0xfff;
211 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
212 } else if (!qtest_enabled() || kernel_filename != NULL) {
213 error_report("Could not load PowerPC BIOS '%s'", bios_name);
214 exit(1);
215 } else {
216 /* Avoid an uninitialized variable warning */
217 bios_size = -1;
218 }
219 memory_region_set_readonly(bios, true);
220 }
221 /* Register FPGA */
222 ref405ep_fpga_init(sysmem, 0xF0300000);
223 /* Register NVRAM */
224 m48t59_init(NULL, 0xF0000000, 0, 8192, 1968, 8);
225 /* Load kernel */
226 linux_boot = (kernel_filename != NULL);
227 if (linux_boot) {
228 memset(&bd, 0, sizeof(bd));
229 bd.bi_memstart = 0x00000000;
230 bd.bi_memsize = ram_size;
231 bd.bi_flashstart = -bios_size;
232 bd.bi_flashsize = -bios_size;
233 bd.bi_flashoffset = 0;
234 bd.bi_sramstart = 0xFFF00000;
235 bd.bi_sramsize = sram_size;
236 bd.bi_bootflags = 0;
237 bd.bi_intfreq = 133333333;
238 bd.bi_busfreq = 33333333;
239 bd.bi_baudrate = 115200;
240 bd.bi_s_version[0] = 'Q';
241 bd.bi_s_version[1] = 'M';
242 bd.bi_s_version[2] = 'U';
243 bd.bi_s_version[3] = '\0';
244 bd.bi_r_version[0] = 'Q';
245 bd.bi_r_version[1] = 'E';
246 bd.bi_r_version[2] = 'M';
247 bd.bi_r_version[3] = 'U';
248 bd.bi_r_version[4] = '\0';
249 bd.bi_procfreq = 133333333;
250 bd.bi_plb_busfreq = 33333333;
251 bd.bi_pci_busfreq = 33333333;
252 bd.bi_opbfreq = 33333333;
253 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
254 env->gpr[3] = bdloc;
255 kernel_base = KERNEL_LOAD_ADDR;
256 /* now we can load the kernel */
257 kernel_size = load_image_targphys(kernel_filename, kernel_base,
258 ram_size - kernel_base);
259 if (kernel_size < 0) {
260 error_report("could not load kernel '%s'", kernel_filename);
261 exit(1);
262 }
263 printf("Load kernel size %ld at " TARGET_FMT_lx,
264 kernel_size, kernel_base);
265 /* load initrd */
266 if (initrd_filename) {
267 initrd_base = INITRD_LOAD_ADDR;
268 initrd_size = load_image_targphys(initrd_filename, initrd_base,
269 ram_size - initrd_base);
270 if (initrd_size < 0) {
271 error_report("could not load initial ram disk '%s'",
272 initrd_filename);
273 exit(1);
274 }
275 } else {
276 initrd_base = 0;
277 initrd_size = 0;
278 }
279 env->gpr[4] = initrd_base;
280 env->gpr[5] = initrd_size;
281 if (kernel_cmdline != NULL) {
282 len = strlen(kernel_cmdline);
283 bdloc -= ((len + 255) & ~255);
284 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
285 env->gpr[6] = bdloc;
286 env->gpr[7] = bdloc + len;
287 } else {
288 env->gpr[6] = 0;
289 env->gpr[7] = 0;
290 }
291 env->nip = KERNEL_LOAD_ADDR;
292 } else {
293 kernel_base = 0;
294 kernel_size = 0;
295 initrd_base = 0;
296 initrd_size = 0;
297 bdloc = 0;
298 }
299}
300
301static void ref405ep_class_init(ObjectClass *oc, void *data)
302{
303 MachineClass *mc = MACHINE_CLASS(oc);
304
305 mc->desc = "ref405ep";
306 mc->init = ref405ep_init;
307}
308
309static const TypeInfo ref405ep_type = {
310 .name = MACHINE_TYPE_NAME("ref405ep"),
311 .parent = TYPE_MACHINE,
312 .class_init = ref405ep_class_init,
313};
314
315/*****************************************************************************/
316/* AMCC Taihu evaluation board */
317/* - PowerPC 405EP processor
318 * - SDRAM 128 MB at 0x00000000
319 * - Boot flash 2 MB at 0xFFE00000
320 * - Application flash 32 MB at 0xFC000000
321 * - 2 serial ports
322 * - 2 ethernet PHY
323 * - 1 USB 1.1 device 0x50000000
324 * - 1 LCD display 0x50100000
325 * - 1 CPLD 0x50100000
326 * - 1 I2C EEPROM
327 * - 1 I2C thermal sensor
328 * - a set of LEDs
329 * - bit-bang SPI port using GPIOs
330 * - 1 EBC interface connector 0 0x50200000
331 * - 1 cardbus controller + expansion slot.
332 * - 1 PCI expansion slot.
333 */
334typedef struct taihu_cpld_t taihu_cpld_t;
335struct taihu_cpld_t {
336 uint8_t reg0;
337 uint8_t reg1;
338};
339
340static uint64_t taihu_cpld_read(void *opaque, hwaddr addr, unsigned size)
341{
342 taihu_cpld_t *cpld;
343 uint32_t ret;
344
345 cpld = opaque;
346 switch (addr) {
347 case 0x0:
348 ret = cpld->reg0;
349 break;
350 case 0x1:
351 ret = cpld->reg1;
352 break;
353 default:
354 ret = 0;
355 break;
356 }
357
358 return ret;
359}
360
361static void taihu_cpld_write(void *opaque, hwaddr addr,
362 uint64_t value, unsigned size)
363{
364 taihu_cpld_t *cpld;
365
366 cpld = opaque;
367 switch (addr) {
368 case 0x0:
369 /* Read only */
370 break;
371 case 0x1:
372 cpld->reg1 = value;
373 break;
374 default:
375 break;
376 }
377}
378
379static const MemoryRegionOps taihu_cpld_ops = {
380 .read = taihu_cpld_read,
381 .write = taihu_cpld_write,
382 .impl = {
383 .min_access_size = 1,
384 .max_access_size = 1,
385 },
386 .endianness = DEVICE_NATIVE_ENDIAN,
387};
388
389static void taihu_cpld_reset (void *opaque)
390{
391 taihu_cpld_t *cpld;
392
393 cpld = opaque;
394 cpld->reg0 = 0x01;
395 cpld->reg1 = 0x80;
396}
397
398static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
399{
400 taihu_cpld_t *cpld;
401 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
402
403 cpld = g_malloc0(sizeof(taihu_cpld_t));
404 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
405 memory_region_add_subregion(sysmem, base, cpld_memory);
406 qemu_register_reset(&taihu_cpld_reset, cpld);
407}
408
409static void taihu_405ep_init(MachineState *machine)
410{
411 ram_addr_t ram_size = machine->ram_size;
412 const char *kernel_filename = machine->kernel_filename;
413 const char *initrd_filename = machine->initrd_filename;
414 char *filename;
415 qemu_irq *pic;
416 MemoryRegion *sysmem = get_system_memory();
417 MemoryRegion *bios;
418 MemoryRegion *ram_memories = g_new(MemoryRegion, 2);
419 MemoryRegion *ram = g_malloc0(sizeof(*ram));
420 hwaddr ram_bases[2], ram_sizes[2];
421 long bios_size;
422 target_ulong kernel_base, initrd_base;
423 long kernel_size, initrd_size;
424 int linux_boot;
425 int fl_idx;
426 DriveInfo *dinfo;
427
428 /* RAM is soldered to the board so the size cannot be changed */
429 ram_size = 0x08000000;
430 memory_region_allocate_system_memory(ram, NULL, "taihu_405ep.ram",
431 ram_size);
432
433 ram_bases[0] = 0;
434 ram_sizes[0] = 0x04000000;
435 memory_region_init_alias(&ram_memories[0], NULL,
436 "taihu_405ep.ram-0", ram, ram_bases[0],
437 ram_sizes[0]);
438 ram_bases[1] = 0x04000000;
439 ram_sizes[1] = 0x04000000;
440 memory_region_init_alias(&ram_memories[1], NULL,
441 "taihu_405ep.ram-1", ram, ram_bases[1],
442 ram_sizes[1]);
443 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
444 33333333, &pic, kernel_filename == NULL ? 0 : 1);
445 /* allocate and load BIOS */
446 fl_idx = 0;
447#if defined(USE_FLASH_BIOS)
448 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
449 if (dinfo) {
450 bios_size = 2 * MiB;
451 pflash_cfi02_register(0xFFE00000,
452 "taihu_405ep.bios", bios_size,
453 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
454 64 * KiB, 1,
455 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
456 1);
457 fl_idx++;
458 } else
459#endif
460 {
461 if (bios_name == NULL)
462 bios_name = BIOS_FILENAME;
463 bios = g_new(MemoryRegion, 1);
464 memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE,
465 &error_fatal);
466 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
467 if (filename) {
468 bios_size = load_image_size(filename,
469 memory_region_get_ram_ptr(bios),
470 BIOS_SIZE);
471 g_free(filename);
472 if (bios_size < 0) {
473 error_report("Could not load PowerPC BIOS '%s'", bios_name);
474 exit(1);
475 }
476 bios_size = (bios_size + 0xfff) & ~0xfff;
477 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
478 } else if (!qtest_enabled()) {
479 error_report("Could not load PowerPC BIOS '%s'", bios_name);
480 exit(1);
481 }
482 memory_region_set_readonly(bios, true);
483 }
484 /* Register Linux flash */
485 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
486 if (dinfo) {
487 bios_size = 32 * MiB;
488 pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
489 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
490 64 * KiB, 1,
491 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
492 1);
493 fl_idx++;
494 }
495 /* Register CLPD & LCD display */
496 taihu_cpld_init(sysmem, 0x50100000);
497 /* Load kernel */
498 linux_boot = (kernel_filename != NULL);
499 if (linux_boot) {
500 kernel_base = KERNEL_LOAD_ADDR;
501 /* now we can load the kernel */
502 kernel_size = load_image_targphys(kernel_filename, kernel_base,
503 ram_size - kernel_base);
504 if (kernel_size < 0) {
505 error_report("could not load kernel '%s'", kernel_filename);
506 exit(1);
507 }
508 /* load initrd */
509 if (initrd_filename) {
510 initrd_base = INITRD_LOAD_ADDR;
511 initrd_size = load_image_targphys(initrd_filename, initrd_base,
512 ram_size - initrd_base);
513 if (initrd_size < 0) {
514 error_report("could not load initial ram disk '%s'",
515 initrd_filename);
516 exit(1);
517 }
518 } else {
519 initrd_base = 0;
520 initrd_size = 0;
521 }
522 } else {
523 kernel_base = 0;
524 kernel_size = 0;
525 initrd_base = 0;
526 initrd_size = 0;
527 }
528}
529
530static void taihu_class_init(ObjectClass *oc, void *data)
531{
532 MachineClass *mc = MACHINE_CLASS(oc);
533
534 mc->desc = "taihu";
535 mc->init = taihu_405ep_init;
536}
537
538static const TypeInfo taihu_type = {
539 .name = MACHINE_TYPE_NAME("taihu"),
540 .parent = TYPE_MACHINE,
541 .class_init = taihu_class_init,
542};
543
544static void ppc405_machine_init(void)
545{
546 type_register_static(&ref405ep_type);
547 type_register_static(&taihu_type);
548}
549
550type_init(ppc405_machine_init)
551