1/*
2 * QEMU SiFive Test Finisher
3 *
4 * Copyright (c) 2018 SiFive, Inc.
5 *
6 * Test finisher memory mapped device used to exit simulation
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2 or later, as published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include "qemu/osdep.h"
22#include "hw/hw.h"
23#include "hw/sysbus.h"
24#include "qemu/module.h"
25#include "target/riscv/cpu.h"
26#include "hw/hw.h"
27#include "hw/riscv/sifive_test.h"
28
29static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size)
30{
31 return 0;
32}
33
34static void sifive_test_write(void *opaque, hwaddr addr,
35 uint64_t val64, unsigned int size)
36{
37 if (addr == 0) {
38 int status = val64 & 0xffff;
39 int code = (val64 >> 16) & 0xffff;
40 switch (status) {
41 case FINISHER_FAIL:
42 exit(code);
43 case FINISHER_PASS:
44 exit(0);
45 default:
46 break;
47 }
48 }
49 hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
50 __func__, (int)addr, val64);
51}
52
53static const MemoryRegionOps sifive_test_ops = {
54 .read = sifive_test_read,
55 .write = sifive_test_write,
56 .endianness = DEVICE_NATIVE_ENDIAN,
57 .valid = {
58 .min_access_size = 4,
59 .max_access_size = 4
60 }
61};
62
63static void sifive_test_init(Object *obj)
64{
65 SiFiveTestState *s = SIFIVE_TEST(obj);
66
67 memory_region_init_io(&s->mmio, obj, &sifive_test_ops, s,
68 TYPE_SIFIVE_TEST, 0x1000);
69 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
70}
71
72static const TypeInfo sifive_test_info = {
73 .name = TYPE_SIFIVE_TEST,
74 .parent = TYPE_SYS_BUS_DEVICE,
75 .instance_size = sizeof(SiFiveTestState),
76 .instance_init = sifive_test_init,
77};
78
79static void sifive_test_register_types(void)
80{
81 type_register_static(&sifive_test_info);
82}
83
84type_init(sifive_test_register_types)
85
86
87/*
88 * Create Test device.
89 */
90DeviceState *sifive_test_create(hwaddr addr)
91{
92 DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_TEST);
93 qdev_init_nofail(dev);
94 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
95 return dev;
96}
97