1 | /* |
2 | * Raspberry Pi (BCM2835) SD Host Controller |
3 | * |
4 | * Copyright (c) 2017 Antfield SAS |
5 | * |
6 | * Authors: |
7 | * Clement Deschamps <clement.deschamps@antfield.fr> |
8 | * Luc Michel <luc.michel@antfield.fr> |
9 | * |
10 | * This work is licensed under the terms of the GNU GPL, version 2 or later. |
11 | * See the COPYING file in the top-level directory. |
12 | */ |
13 | |
14 | #include "qemu/osdep.h" |
15 | #include "qemu/log.h" |
16 | #include "qemu/module.h" |
17 | #include "sysemu/blockdev.h" |
18 | #include "hw/irq.h" |
19 | #include "hw/sd/bcm2835_sdhost.h" |
20 | #include "migration/vmstate.h" |
21 | #include "trace.h" |
22 | |
23 | #define TYPE_BCM2835_SDHOST_BUS "bcm2835-sdhost-bus" |
24 | #define BCM2835_SDHOST_BUS(obj) \ |
25 | OBJECT_CHECK(SDBus, (obj), TYPE_BCM2835_SDHOST_BUS) |
26 | |
27 | #define SDCMD 0x00 /* Command to SD card - 16 R/W */ |
28 | #define SDARG 0x04 /* Argument to SD card - 32 R/W */ |
29 | #define SDTOUT 0x08 /* Start value for timeout counter - 32 R/W */ |
30 | #define SDCDIV 0x0c /* Start value for clock divider - 11 R/W */ |
31 | #define SDRSP0 0x10 /* SD card rsp (31:0) - 32 R */ |
32 | #define SDRSP1 0x14 /* SD card rsp (63:32) - 32 R */ |
33 | #define SDRSP2 0x18 /* SD card rsp (95:64) - 32 R */ |
34 | #define SDRSP3 0x1c /* SD card rsp (127:96) - 32 R */ |
35 | #define SDHSTS 0x20 /* SD host status - 11 R */ |
36 | #define SDVDD 0x30 /* SD card power control - 1 R/W */ |
37 | #define SDEDM 0x34 /* Emergency Debug Mode - 13 R/W */ |
38 | #define SDHCFG 0x38 /* Host configuration - 2 R/W */ |
39 | #define SDHBCT 0x3c /* Host byte count (debug) - 32 R/W */ |
40 | #define SDDATA 0x40 /* Data to/from SD card - 32 R/W */ |
41 | #define SDHBLC 0x50 /* Host block count (SDIO/SDHC) - 9 R/W */ |
42 | |
43 | #define SDCMD_NEW_FLAG 0x8000 |
44 | #define SDCMD_FAIL_FLAG 0x4000 |
45 | #define SDCMD_BUSYWAIT 0x800 |
46 | #define SDCMD_NO_RESPONSE 0x400 |
47 | #define SDCMD_LONG_RESPONSE 0x200 |
48 | #define SDCMD_WRITE_CMD 0x80 |
49 | #define SDCMD_READ_CMD 0x40 |
50 | #define SDCMD_CMD_MASK 0x3f |
51 | |
52 | #define SDCDIV_MAX_CDIV 0x7ff |
53 | |
54 | #define SDHSTS_BUSY_IRPT 0x400 |
55 | #define SDHSTS_BLOCK_IRPT 0x200 |
56 | #define SDHSTS_SDIO_IRPT 0x100 |
57 | #define SDHSTS_REW_TIME_OUT 0x80 |
58 | #define SDHSTS_CMD_TIME_OUT 0x40 |
59 | #define SDHSTS_CRC16_ERROR 0x20 |
60 | #define SDHSTS_CRC7_ERROR 0x10 |
61 | #define SDHSTS_FIFO_ERROR 0x08 |
62 | /* Reserved */ |
63 | /* Reserved */ |
64 | #define SDHSTS_DATA_FLAG 0x01 |
65 | |
66 | #define SDHCFG_BUSY_IRPT_EN (1 << 10) |
67 | #define SDHCFG_BLOCK_IRPT_EN (1 << 8) |
68 | #define SDHCFG_SDIO_IRPT_EN (1 << 5) |
69 | #define SDHCFG_DATA_IRPT_EN (1 << 4) |
70 | #define SDHCFG_SLOW_CARD (1 << 3) |
71 | #define SDHCFG_WIDE_EXT_BUS (1 << 2) |
72 | #define SDHCFG_WIDE_INT_BUS (1 << 1) |
73 | #define SDHCFG_REL_CMD_LINE (1 << 0) |
74 | |
75 | #define SDEDM_FORCE_DATA_MODE (1 << 19) |
76 | #define SDEDM_CLOCK_PULSE (1 << 20) |
77 | #define SDEDM_BYPASS (1 << 21) |
78 | |
79 | #define SDEDM_WRITE_THRESHOLD_SHIFT 9 |
80 | #define SDEDM_READ_THRESHOLD_SHIFT 14 |
81 | #define SDEDM_THRESHOLD_MASK 0x1f |
82 | |
83 | #define SDEDM_FSM_MASK 0xf |
84 | #define SDEDM_FSM_IDENTMODE 0x0 |
85 | #define SDEDM_FSM_DATAMODE 0x1 |
86 | #define SDEDM_FSM_READDATA 0x2 |
87 | #define SDEDM_FSM_WRITEDATA 0x3 |
88 | #define SDEDM_FSM_READWAIT 0x4 |
89 | #define SDEDM_FSM_READCRC 0x5 |
90 | #define SDEDM_FSM_WRITECRC 0x6 |
91 | #define SDEDM_FSM_WRITEWAIT1 0x7 |
92 | #define SDEDM_FSM_POWERDOWN 0x8 |
93 | #define SDEDM_FSM_POWERUP 0x9 |
94 | #define SDEDM_FSM_WRITESTART1 0xa |
95 | #define SDEDM_FSM_WRITESTART2 0xb |
96 | #define SDEDM_FSM_GENPULSES 0xc |
97 | #define SDEDM_FSM_WRITEWAIT2 0xd |
98 | #define SDEDM_FSM_STARTPOWDOWN 0xf |
99 | |
100 | #define SDDATA_FIFO_WORDS 16 |
101 | |
102 | static void bcm2835_sdhost_update_irq(BCM2835SDHostState *s) |
103 | { |
104 | uint32_t irq = s->status & |
105 | (SDHSTS_BUSY_IRPT | SDHSTS_BLOCK_IRPT | SDHSTS_SDIO_IRPT); |
106 | trace_bcm2835_sdhost_update_irq(irq); |
107 | qemu_set_irq(s->irq, !!irq); |
108 | } |
109 | |
110 | static void bcm2835_sdhost_send_command(BCM2835SDHostState *s) |
111 | { |
112 | SDRequest request; |
113 | uint8_t rsp[16]; |
114 | int rlen; |
115 | |
116 | request.cmd = s->cmd & SDCMD_CMD_MASK; |
117 | request.arg = s->cmdarg; |
118 | |
119 | rlen = sdbus_do_command(&s->sdbus, &request, rsp); |
120 | if (rlen < 0) { |
121 | goto error; |
122 | } |
123 | if (!(s->cmd & SDCMD_NO_RESPONSE)) { |
124 | if (rlen == 0 || (rlen == 4 && (s->cmd & SDCMD_LONG_RESPONSE))) { |
125 | goto error; |
126 | } |
127 | if (rlen != 4 && rlen != 16) { |
128 | goto error; |
129 | } |
130 | if (rlen == 4) { |
131 | s->rsp[0] = ldl_be_p(&rsp[0]); |
132 | s->rsp[1] = s->rsp[2] = s->rsp[3] = 0; |
133 | } else { |
134 | s->rsp[0] = ldl_be_p(&rsp[12]); |
135 | s->rsp[1] = ldl_be_p(&rsp[8]); |
136 | s->rsp[2] = ldl_be_p(&rsp[4]); |
137 | s->rsp[3] = ldl_be_p(&rsp[0]); |
138 | } |
139 | } |
140 | /* We never really delay commands, so if this was a 'busywait' command |
141 | * then we've completed it now and can raise the interrupt. |
142 | */ |
143 | if ((s->cmd & SDCMD_BUSYWAIT) && (s->config & SDHCFG_BUSY_IRPT_EN)) { |
144 | s->status |= SDHSTS_BUSY_IRPT; |
145 | } |
146 | return; |
147 | |
148 | error: |
149 | s->cmd |= SDCMD_FAIL_FLAG; |
150 | s->status |= SDHSTS_CMD_TIME_OUT; |
151 | } |
152 | |
153 | static void bcm2835_sdhost_fifo_push(BCM2835SDHostState *s, uint32_t value) |
154 | { |
155 | int n; |
156 | |
157 | if (s->fifo_len == BCM2835_SDHOST_FIFO_LEN) { |
158 | /* FIFO overflow */ |
159 | return; |
160 | } |
161 | n = (s->fifo_pos + s->fifo_len) & (BCM2835_SDHOST_FIFO_LEN - 1); |
162 | s->fifo_len++; |
163 | s->fifo[n] = value; |
164 | } |
165 | |
166 | static uint32_t bcm2835_sdhost_fifo_pop(BCM2835SDHostState *s) |
167 | { |
168 | uint32_t value; |
169 | |
170 | if (s->fifo_len == 0) { |
171 | /* FIFO underflow */ |
172 | return 0; |
173 | } |
174 | value = s->fifo[s->fifo_pos]; |
175 | s->fifo_len--; |
176 | s->fifo_pos = (s->fifo_pos + 1) & (BCM2835_SDHOST_FIFO_LEN - 1); |
177 | return value; |
178 | } |
179 | |
180 | static void bcm2835_sdhost_fifo_run(BCM2835SDHostState *s) |
181 | { |
182 | uint32_t value = 0; |
183 | int n; |
184 | int is_read; |
185 | int is_write; |
186 | |
187 | is_read = (s->cmd & SDCMD_READ_CMD) != 0; |
188 | is_write = (s->cmd & SDCMD_WRITE_CMD) != 0; |
189 | if (s->datacnt != 0 && (is_write || sdbus_data_ready(&s->sdbus))) { |
190 | if (is_read) { |
191 | n = 0; |
192 | while (s->datacnt && s->fifo_len < BCM2835_SDHOST_FIFO_LEN) { |
193 | value |= (uint32_t)sdbus_read_data(&s->sdbus) << (n * 8); |
194 | s->datacnt--; |
195 | n++; |
196 | if (n == 4) { |
197 | bcm2835_sdhost_fifo_push(s, value); |
198 | s->status |= SDHSTS_DATA_FLAG; |
199 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
200 | s->status |= SDHSTS_SDIO_IRPT; |
201 | } |
202 | n = 0; |
203 | value = 0; |
204 | } |
205 | } |
206 | if (n != 0) { |
207 | bcm2835_sdhost_fifo_push(s, value); |
208 | s->status |= SDHSTS_DATA_FLAG; |
209 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
210 | s->status |= SDHSTS_SDIO_IRPT; |
211 | } |
212 | } |
213 | } else if (is_write) { /* write */ |
214 | n = 0; |
215 | while (s->datacnt > 0 && (s->fifo_len > 0 || n > 0)) { |
216 | if (n == 0) { |
217 | value = bcm2835_sdhost_fifo_pop(s); |
218 | s->status |= SDHSTS_DATA_FLAG; |
219 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
220 | s->status |= SDHSTS_SDIO_IRPT; |
221 | } |
222 | n = 4; |
223 | } |
224 | n--; |
225 | s->datacnt--; |
226 | sdbus_write_data(&s->sdbus, value & 0xff); |
227 | value >>= 8; |
228 | } |
229 | } |
230 | if (s->datacnt == 0) { |
231 | s->edm &= ~SDEDM_FSM_MASK; |
232 | s->edm |= SDEDM_FSM_DATAMODE; |
233 | trace_bcm2835_sdhost_edm_change("datacnt 0" , s->edm); |
234 | } |
235 | if (is_write) { |
236 | /* set block interrupt at end of each block transfer */ |
237 | if (s->hbct && s->datacnt % s->hbct == 0 && |
238 | (s->config & SDHCFG_BLOCK_IRPT_EN)) { |
239 | s->status |= SDHSTS_BLOCK_IRPT; |
240 | } |
241 | /* set data interrupt after each transfer */ |
242 | s->status |= SDHSTS_DATA_FLAG; |
243 | if (s->config & SDHCFG_DATA_IRPT_EN) { |
244 | s->status |= SDHSTS_SDIO_IRPT; |
245 | } |
246 | } |
247 | } |
248 | |
249 | bcm2835_sdhost_update_irq(s); |
250 | |
251 | s->edm &= ~(0x1f << 4); |
252 | s->edm |= ((s->fifo_len & 0x1f) << 4); |
253 | trace_bcm2835_sdhost_edm_change("fifo run" , s->edm); |
254 | } |
255 | |
256 | static uint64_t bcm2835_sdhost_read(void *opaque, hwaddr offset, |
257 | unsigned size) |
258 | { |
259 | BCM2835SDHostState *s = (BCM2835SDHostState *)opaque; |
260 | uint32_t res = 0; |
261 | |
262 | switch (offset) { |
263 | case SDCMD: |
264 | res = s->cmd; |
265 | break; |
266 | case SDHSTS: |
267 | res = s->status; |
268 | break; |
269 | case SDRSP0: |
270 | res = s->rsp[0]; |
271 | break; |
272 | case SDRSP1: |
273 | res = s->rsp[1]; |
274 | break; |
275 | case SDRSP2: |
276 | res = s->rsp[2]; |
277 | break; |
278 | case SDRSP3: |
279 | res = s->rsp[3]; |
280 | break; |
281 | case SDEDM: |
282 | res = s->edm; |
283 | break; |
284 | case SDVDD: |
285 | res = s->vdd; |
286 | break; |
287 | case SDDATA: |
288 | res = bcm2835_sdhost_fifo_pop(s); |
289 | bcm2835_sdhost_fifo_run(s); |
290 | break; |
291 | case SDHBCT: |
292 | res = s->hbct; |
293 | break; |
294 | case SDHBLC: |
295 | res = s->hblc; |
296 | break; |
297 | |
298 | default: |
299 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %" HWADDR_PRIx"\n" , |
300 | __func__, offset); |
301 | res = 0; |
302 | break; |
303 | } |
304 | |
305 | trace_bcm2835_sdhost_read(offset, res, size); |
306 | |
307 | return res; |
308 | } |
309 | |
310 | static void bcm2835_sdhost_write(void *opaque, hwaddr offset, |
311 | uint64_t value, unsigned size) |
312 | { |
313 | BCM2835SDHostState *s = (BCM2835SDHostState *)opaque; |
314 | |
315 | trace_bcm2835_sdhost_write(offset, value, size); |
316 | |
317 | switch (offset) { |
318 | case SDCMD: |
319 | s->cmd = value; |
320 | if (value & SDCMD_NEW_FLAG) { |
321 | bcm2835_sdhost_send_command(s); |
322 | bcm2835_sdhost_fifo_run(s); |
323 | s->cmd &= ~SDCMD_NEW_FLAG; |
324 | } |
325 | break; |
326 | case SDTOUT: |
327 | break; |
328 | case SDCDIV: |
329 | break; |
330 | case SDHSTS: |
331 | s->status &= ~value; |
332 | bcm2835_sdhost_update_irq(s); |
333 | break; |
334 | case SDARG: |
335 | s->cmdarg = value; |
336 | break; |
337 | case SDEDM: |
338 | if ((value & 0xf) == 0xf) { |
339 | /* power down */ |
340 | value &= ~0xf; |
341 | } |
342 | s->edm = value; |
343 | trace_bcm2835_sdhost_edm_change("guest register write" , s->edm); |
344 | break; |
345 | case SDHCFG: |
346 | s->config = value; |
347 | bcm2835_sdhost_fifo_run(s); |
348 | break; |
349 | case SDVDD: |
350 | s->vdd = value; |
351 | break; |
352 | case SDDATA: |
353 | bcm2835_sdhost_fifo_push(s, value); |
354 | bcm2835_sdhost_fifo_run(s); |
355 | break; |
356 | case SDHBCT: |
357 | s->hbct = value; |
358 | break; |
359 | case SDHBLC: |
360 | s->hblc = value; |
361 | s->datacnt = s->hblc * s->hbct; |
362 | bcm2835_sdhost_fifo_run(s); |
363 | break; |
364 | |
365 | default: |
366 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %" HWADDR_PRIx"\n" , |
367 | __func__, offset); |
368 | break; |
369 | } |
370 | } |
371 | |
372 | static const MemoryRegionOps bcm2835_sdhost_ops = { |
373 | .read = bcm2835_sdhost_read, |
374 | .write = bcm2835_sdhost_write, |
375 | .endianness = DEVICE_NATIVE_ENDIAN, |
376 | }; |
377 | |
378 | static const VMStateDescription vmstate_bcm2835_sdhost = { |
379 | .name = TYPE_BCM2835_SDHOST, |
380 | .version_id = 1, |
381 | .minimum_version_id = 1, |
382 | .fields = (VMStateField[]) { |
383 | VMSTATE_UINT32(cmd, BCM2835SDHostState), |
384 | VMSTATE_UINT32(cmdarg, BCM2835SDHostState), |
385 | VMSTATE_UINT32(status, BCM2835SDHostState), |
386 | VMSTATE_UINT32_ARRAY(rsp, BCM2835SDHostState, 4), |
387 | VMSTATE_UINT32(config, BCM2835SDHostState), |
388 | VMSTATE_UINT32(edm, BCM2835SDHostState), |
389 | VMSTATE_UINT32(vdd, BCM2835SDHostState), |
390 | VMSTATE_UINT32(hbct, BCM2835SDHostState), |
391 | VMSTATE_UINT32(hblc, BCM2835SDHostState), |
392 | VMSTATE_INT32(fifo_pos, BCM2835SDHostState), |
393 | VMSTATE_INT32(fifo_len, BCM2835SDHostState), |
394 | VMSTATE_UINT32_ARRAY(fifo, BCM2835SDHostState, BCM2835_SDHOST_FIFO_LEN), |
395 | VMSTATE_UINT32(datacnt, BCM2835SDHostState), |
396 | VMSTATE_END_OF_LIST() |
397 | } |
398 | }; |
399 | |
400 | static void bcm2835_sdhost_init(Object *obj) |
401 | { |
402 | BCM2835SDHostState *s = BCM2835_SDHOST(obj); |
403 | |
404 | qbus_create_inplace(&s->sdbus, sizeof(s->sdbus), |
405 | TYPE_BCM2835_SDHOST_BUS, DEVICE(s), "sd-bus" ); |
406 | |
407 | memory_region_init_io(&s->iomem, obj, &bcm2835_sdhost_ops, s, |
408 | TYPE_BCM2835_SDHOST, 0x1000); |
409 | sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem); |
410 | sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq); |
411 | } |
412 | |
413 | static void bcm2835_sdhost_reset(DeviceState *dev) |
414 | { |
415 | BCM2835SDHostState *s = BCM2835_SDHOST(dev); |
416 | |
417 | s->cmd = 0; |
418 | s->cmdarg = 0; |
419 | s->edm = 0x0000c60f; |
420 | trace_bcm2835_sdhost_edm_change("device reset" , s->edm); |
421 | s->config = 0; |
422 | s->hbct = 0; |
423 | s->hblc = 0; |
424 | s->datacnt = 0; |
425 | s->fifo_pos = 0; |
426 | s->fifo_len = 0; |
427 | } |
428 | |
429 | static void bcm2835_sdhost_class_init(ObjectClass *klass, void *data) |
430 | { |
431 | DeviceClass *dc = DEVICE_CLASS(klass); |
432 | |
433 | dc->reset = bcm2835_sdhost_reset; |
434 | dc->vmsd = &vmstate_bcm2835_sdhost; |
435 | } |
436 | |
437 | static TypeInfo bcm2835_sdhost_info = { |
438 | .name = TYPE_BCM2835_SDHOST, |
439 | .parent = TYPE_SYS_BUS_DEVICE, |
440 | .instance_size = sizeof(BCM2835SDHostState), |
441 | .class_init = bcm2835_sdhost_class_init, |
442 | .instance_init = bcm2835_sdhost_init, |
443 | }; |
444 | |
445 | static const TypeInfo bcm2835_sdhost_bus_info = { |
446 | .name = TYPE_BCM2835_SDHOST_BUS, |
447 | .parent = TYPE_SD_BUS, |
448 | .instance_size = sizeof(SDBus), |
449 | }; |
450 | |
451 | static void bcm2835_sdhost_register_types(void) |
452 | { |
453 | type_register_static(&bcm2835_sdhost_info); |
454 | type_register_static(&bcm2835_sdhost_bus_info); |
455 | } |
456 | |
457 | type_init(bcm2835_sdhost_register_types) |
458 | |